[AMDGPU] Add support for the .reloc directive

[arsenm]

LGTM

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

public:
 
   bool mayNeedRelaxation(const MCInst &Inst,
                          const MCSubtargetInfo &STI) const override;
 
   unsigned getMinimumNopSize() const override;
   bool writeNopData(raw_ostream &OS, uint64_t Count,
                     const MCSubtargetInfo *STI) const override;
 
+  Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
+  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
+                             const MCValue &Target) override;
 };
 
 } //End anonymous namespace
 
 void AMDGPUAsmBackend::relaxInstruction(MCInst &Inst,
                                         const MCSubtargetInfo &STI) const {
   MCInst Res;
   unsigned RelaxedOpcode = AMDGPU::getSOPPWithRelaxation(Inst.getOpcode());
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
   }
 }
 
 void AMDGPUAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                                   const MCValue &Target,
                                   MutableArrayRef<char> Data, uint64_t Value,
                                   bool IsResolved,
                                   const MCSubtargetInfo *STI) const {
+  if (Fixup.getKind() >= FirstLiteralRelocationKind)
+    return;
+
   Value = adjustFixupValue(Fixup, Value, &Asm.getContext());
   if (!Value)
     return; // Doesn't change encoding.
 
   MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
 
   // Shift the value into position.
   Value <<= Info.TargetOffset;
 
   unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
   uint32_t Offset = Fixup.getOffset();
   assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
 
   // For each byte of the fragment that the fixup touches, mask in the bits from
   // the fixup value.
   for (unsigned i = 0; i != NumBytes; ++i)
     Data[Offset + i] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff);
 }
 
+Optional<MCFixupKind> AMDGPUAsmBackend::getFixupKind(StringRef Name) const {
+  return StringSwitch<Optional<MCFixupKind>>(Name)
+#define ELF_RELOC(Name, Value)                                                 \
+  .Case(#Name, MCFixupKind(FirstLiteralRelocationKind + Value))
+#include "llvm/BinaryFormat/ELFRelocs/AMDGPU.def"
+#undef ELF_RELOC
+      .Default(None);
+}
+
 const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
                                                        MCFixupKind Kind) const {
   const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
     // name                   offset bits  flags
     { "fixup_si_sopp_br",     0,     16,   MCFixupKindInfo::FKF_IsPCRel },
   };
 
+  if (Kind >= FirstLiteralRelocationKind)
+    return MCAsmBackend::getFixupKindInfo(FK_NONE);
+
   if (Kind < FirstTargetFixupKind)
     return MCAsmBackend::getFixupKindInfo(Kind);
 
   return Infos[Kind - FirstTargetFixupKind];
 }
 
+bool AMDGPUAsmBackend::shouldForceRelocation(const MCAssembler &,
+                                             const MCFixup &Fixup,
+                                             const MCValue &) {
+  return Fixup.getKind() >= FirstLiteralRelocationKind;
+}
+
 unsigned AMDGPUAsmBackend::getMinimumNopSize() const {
   return 4;
 }
 
 bool AMDGPUAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
                                     const MCSubtargetInfo *STI) const {
   // If the count is not 4-byte aligned, we must be writing data into the text
   // section (otherwise we have unaligned instructions, and thus have far

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp

unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
   case MCSymbolRefExpr::VK_AMDGPU_REL32_LO:
     return ELF::R_AMDGPU_REL32_LO;
   case MCSymbolRefExpr::VK_AMDGPU_REL32_HI:
     return ELF::R_AMDGPU_REL32_HI;
   case MCSymbolRefExpr::VK_AMDGPU_REL64:
     return ELF::R_AMDGPU_REL64;
   }
 
-  switch (Fixup.getKind()) {
+  MCFixupKind Kind = Fixup.getKind();
+  if (Kind >= FirstLiteralRelocationKind)
+    return Kind - FirstLiteralRelocationKind;
+  switch (Kind) {
   default: break;
   case FK_PCRel_4:
     return ELF::R_AMDGPU_REL32;
   case FK_Data_4:
   case FK_SecRel_4:
     return ELF::R_AMDGPU_ABS32;
   case FK_Data_8:
     return ELF::R_AMDGPU_ABS64;

llvm/test/MC/AMDGPU/reloc-directive.s

+# RUN: llvm-mc -triple=amdgcn--amdhsa %s | FileCheck --check-prefix=PRINT %s
+
+# RUN: llvm-mc -filetype=obj -triple=amdgcn--amdhsa %s -o %t
+# RUN: llvm-readobj -r %t | FileCheck %s
+
+# PRINT:      .reloc 2, R_AMDGPU_NONE, .data
+# PRINT-NEXT: .reloc 1, R_AMDGPU_NONE, foo+4
+# PRINT-NEXT: .reloc 0, R_AMDGPU_NONE, 8
+# PRINT-NEXT: .reloc 0, R_AMDGPU_ABS32_LO, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_ABS32_HI, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_ABS64, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_REL32, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_REL64, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_ABS32, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_GOTPCREL, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_GOTPCREL32_LO, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_GOTPCREL32_HI, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_REL32_LO, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_REL32_HI, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_RELATIVE64, .data
+# PRINT-NEXT: .reloc 0, R_AMDGPU_REL16, .data
+
+# CHECK:      0x2 R_AMDGPU_NONE .data
+# CHECK-NEXT: 0x1 R_AMDGPU_NONE foo 0x4
+# CHECK-NEXT: 0x0 R_AMDGPU_NONE - 0x8
+# CHECK-NEXT: 0x0 R_AMDGPU_ABS32_LO .data
+# CHECK-NEXT: 0x0 R_AMDGPU_ABS32_HI .data
+# CHECK-NEXT: 0x0 R_AMDGPU_ABS64 .data
+# CHECK-NEXT: 0x0 R_AMDGPU_REL32 .data
+# CHECK-NEXT: 0x0 R_AMDGPU_REL64 .data
+# CHECK-NEXT: 0x0 R_AMDGPU_ABS32 .data
+# CHECK-NEXT: 0x0 R_AMDGPU_GOTPCREL .data
+# CHECK-NEXT: 0x0 R_AMDGPU_GOTPCREL32_LO .data
+# CHECK-NEXT: 0x0 R_AMDGPU_GOTPCREL32_HI .data
+# CHECK-NEXT: 0x0 R_AMDGPU_REL32_LO .data
+# CHECK-NEXT: 0x0 R_AMDGPU_REL32_HI .data
+# CHECK-NEXT: 0x0 R_AMDGPU_RELATIVE64 .data
+# CHECK-NEXT: 0x0 R_AMDGPU_REL16 .data
+
+.text
+  s_nop 0
+  s_nop 0
+  .reloc 2, R_AMDGPU_NONE, .data
+  .reloc 1, R_AMDGPU_NONE, foo+4
+  .reloc 0, R_AMDGPU_NONE, 8
+  .reloc 0, R_AMDGPU_ABS32_LO, .data
+  .reloc 0, R_AMDGPU_ABS32_HI, .data
+  .reloc 0, R_AMDGPU_ABS64, .data
+  .reloc 0, R_AMDGPU_REL32, .data
+  .reloc 0, R_AMDGPU_REL64, .data
+  .reloc 0, R_AMDGPU_ABS32, .data
+  .reloc 0, R_AMDGPU_GOTPCREL, .data
+  .reloc 0, R_AMDGPU_GOTPCREL32_LO, .data
+  .reloc 0, R_AMDGPU_GOTPCREL32_HI, .data
+  .reloc 0, R_AMDGPU_REL32_LO, .data
+  .reloc 0, R_AMDGPU_REL32_HI, .data
+  .reloc 0, R_AMDGPU_RELATIVE64, .data
+  .reloc 0, R_AMDGPU_REL16, .data
+
+.data
+.globl foo
+foo:
+  .long 0
+  .long 0