This is an archive of the discontinued LLVM Phabricator instance.

Revert "[X86] combineConcatVectorOps - add support for concatenation VSELECT/BLENDV nodes"
AcceptedPublic

Authored by srj on Jun 3 2022, 11:53 AM.

Details

Reviewers
RKSimon
echristo
Summary

This reverts commit ea8fb3b6019642a3a032fd65588eb8460439d2f9.

Causes code-generation failures for x86-32 SIMD code in Halide. See original commit for example of a repro case.

Diff Detail

Event Timeline

srj created this revision.Jun 3 2022, 11:53 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 3 2022, 11:53 AM
srj requested review of this revision.Jun 3 2022, 11:53 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 3 2022, 11:53 AM
srj added a reviewer: RKSimon.Jun 3 2022, 11:58 AM
echristo accepted this revision.Jun 3 2022, 12:01 PM
echristo added a subscriber: echristo.

OK for revert to green.

This revision is now accepted and ready to land.Jun 3 2022, 12:01 PM