LLVM does not distinguish Cortex-M4 from Cortex-M4F neither Cortex-R5 from R5F

[labrinea]

Summary

LLVM currently treats Cortex-M4 and Cortex-R5 as having an FPU. However it distinguishes other arm processors that come optionally with an FPU. These are: cortex-r4, arm1136j-s, arm1176jz-s, mpcore, and arm1156t2-s. Apparently Target Parser and ARM.td are not synchronized.

[meadori]

lib/Target/ARM/ARM.td

470

Do our processor names always correspond to real processor names? It was my understanding that there is no such thing as a "Cortex-M4F" processor: http://sourceware.org/ml/binutils/2010-09/msg00184.html So, GCC & binutils definitely don't have "cortex-m4f".

FWIW, if we don't, then I think we should strive to always use actual processor names.

[rengolin]

Adding Tim as a reviewer, as he was working on M-class Darwin. I'm not sure this change is welcome, or even valid, there.

I'm not particularly bothered by having the F variants per se, but this may create a conflict when using the GNU linker (which we do), so I wouldn't want to have to fix that, given that it was already refused once by Matt.

Alexandros, any special reason why you're adding this?

cheers,
--renato

test/CodeGen/ARM/darwin-eabi.ll

4

Not to mention that this is changing Darwin CPU names, which are normally a lot more strict than the rest...

[labrinea]

One reason I proposed this is that tools/clang/test/CodeGen/arm-target-features.c currently tests cortex-r5f and cortex-m4f but llvm does not recognize these processor names since they are missing from lib/Target/ARM/ARM.td. The tests are passing and that is the reason I did not notice this issue before, when I was writing these tests (http://reviews.llvm.org/D11299). Another way to solve this is changing the tests and also removing the corresponding entries of cortex-r5f and cortex-m4f from Target Parser.

I am not sure what we want though, since I noticed that the processors which I listed above (cortex-r4, arm1136j-s, arm1176jz-s, mpcore, and arm1156t2-s) have "f" versions. That's why I asked for feedback about this patch in llvm-dev.

[richard.barton.arm]

Hi Alexandros

My understanding is that clang wants to match gcc for -mcpu and similar options which means supporting the inconsistency as Renato says. From checking with my 4.9.3 arm-none-eabi toolchain I think this means not supporting Cortex-M4F and Cortex-R5F, but supporting Cortex-R4F unfortunately.

Ta
Rich

[labrinea]

Previous approach was not very welcome to llvm-dev. Since we want to mimic gcc behaviour I am removing r5f and m4f entries from Target Parser. Updating r5 and m4 FPUs accordingly. A clang patch is required for these changes otherwise there will be regressions.

[rengolin]

Hi Alexandros, Richard,

It's not that we want to mimic GCC, but we also don't want to create new names that will never be used by binutils (which we still rely on).

Moreover, this change is more in sync to the LLVM philosophy that we should map the most common representation of a core, not the bare minimum. If the default configuration of R5s and M4s is to have VFP, then we shall represent it that way and let the minority of users disable them via flags.

LGTM, thanks!

[labrinea]

committed as r247136

lib/Target/ARM/ARM.td

 def : ProcessorModel<"cortex-r4f",  CortexA8Model,
                                     [ProcR4,
                                      FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
                                      FeatureVFP3, FeatureD16]>;
 
 // FIXME: R5 has currently the same ProcessorModel as A8.
 def : ProcessorModel<"cortex-r5",   CortexA8Model,
                                     [ProcR5, HasV7Ops, FeatureDB,
+                                     FeatureDSPThumb2,
+                                     FeatureHasRAS,
+                                     FeatureRClass]>;
+
+// FIXME: R5F has currently the same ProcessorModel as A8.
+def : ProcessorModel<"cortex-r5f",  CortexA8Model,
+                                    [ProcR5, HasV7Ops, FeatureDB,
                                      FeatureVFP3, FeatureDSPThumb2,
                                      FeatureHasRAS,
                                      FeatureD16, FeatureRClass]>;
 
 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
 def : ProcessorModel<"cortex-r7",   CortexA8Model,
                                     [ProcR5, HasV7Ops, FeatureDB,
                                      FeatureVFP3, FeatureDSPThumb2,
                                      FeatureHasRAS, FeatureVFPOnlySP,
                                      FeatureD16, FeatureMP, FeatureRClass]>;
 
 // V7M Processors.
 def : ProcNoItin<"cortex-m3",       [HasV7Ops,
                                      FeatureThumb2, FeatureNoARM, FeatureDB,
                                      FeatureHWDiv, FeatureMClass]>;
 def : ProcNoItin<"sc300",           [HasV7Ops,
                                      FeatureThumb2, FeatureNoARM, FeatureDB,
                                      FeatureHWDiv, FeatureMClass]>;
 
 // V7EM Processors.
 def : ProcNoItin<"cortex-m4",       [HasV7Ops,
                                      FeatureThumb2, FeatureNoARM, FeatureDB,
                                      FeatureHWDiv, FeatureDSPThumb2,
+                                     FeatureT2XtPk,
+                                     FeatureMClass]>;
+
+def : ProcNoItin<"cortex-m4f",       [HasV7Ops,
+                                     FeatureThumb2, FeatureNoARM, FeatureDB,
+                                     FeatureHWDiv, FeatureDSPThumb2,
                                      FeatureT2XtPk, FeatureVFP4,
                                      FeatureVFPOnlySP, FeatureD16,
                                      FeatureMClass]>;
+
 def : ProcNoItin<"cortex-m7",       [HasV7Ops,
                                      FeatureThumb2, FeatureNoARM, FeatureDB,
                                      FeatureHWDiv, FeatureDSPThumb2,
                                      FeatureT2XtPk, FeatureFPARMv8,
                                      FeatureD16, FeatureMClass]>;
 
-
 // Swift uArch Processors.
 def : ProcessorModel<"swift",       SwiftModel,
                                     [ProcSwift, HasV7Ops, FeatureNEON,
                                      FeatureDB, FeatureDSPThumb2,
                                      FeatureHasRAS, FeatureAClass]>;
 
 // V8 Processors
 def : ProcNoItin<"cortex-a53",      [ProcA53, HasV8Ops, FeatureAClass,

test/CodeGen/ARM/aapcs-hfa-code.ll

 ; RUN: llc < %s -mtriple=armv7-linux-gnueabihf -o - | FileCheck %s
-; RUN: llc < %s -mtriple=thumbv7em-none-eabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CHECK-M4F
+; RUN: llc < %s -mtriple=thumbv7em-none-eabi -mcpu=cortex-m4f | FileCheck %s --check-prefix=CHECK-M4F
 
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"
 
 define arm_aapcs_vfpcc void @test_1float({ float } %a) {
   call arm_aapcs_vfpcc void @test_1float({ float } { float 1.0 })
   ret void
 
 ; CHECK-LABEL: test_1float:

test/CodeGen/ARM/build-attributes.ll

 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 -mattr=+strict-align  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=SC000-FAST
 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=CORTEX-M3
 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M3-FAST
 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=sc300 | FileCheck %s --check-prefix=SC300
 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=sc300  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=SC300-FAST
 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=sc300 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
-; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT
-; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M4-SOFT-FAST
-; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-M4-HARD
-; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M4-HARD-FAST
-; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
+; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CORTEX-M4
+; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4f -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4F-SOFT
+; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4f -float-abi=soft -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M4F-SOFT-FAST
+; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4f -float-abi=hard | FileCheck %s --check-prefix=CORTEX-M4F-HARD
+; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4f -float-abi=hard  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M4F-HARD-FAST
+; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4f -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-SOFT
 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=-vfp2  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M7-NOFPU-FAST
 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=+fp-only-sp | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-SINGLE
 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=+fp-only-sp  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M7-FAST
 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 | FileCheck %s --check-prefix=CORTEX-M7-DOUBLE
 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r4 | FileCheck %s --check-prefix=CORTEX-R4
 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r4f | FileCheck %s --check-prefix=CORTEX-R4F
 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5
+; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5f | FileCheck %s --check-prefix=CORTEX-R5F
 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-R5-FAST
 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 | FileCheck %s --check-prefix=CORTEX-R7
 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-R7-FAST
 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 | FileCheck %s --check-prefix=CORTEX-A53
 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53  -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A53-FAST
 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING

 ;; Despite there being no FPU, we chose to flush to zero preserving
 ;; sign. This matches what the hardware would do for this architecture
 ;; revision.
 ; SC300-FAST:  .eabi_attribute 20, 2
 ; SC300-FAST-NOT:  .eabi_attribute 21
 ; SC300-FAST-NOT:  .eabi_attribute 22
 ; SC300-FAST:  .eabi_attribute 23, 1
 
-; CORTEX-M4-SOFT:  .cpu cortex-m4
-; CORTEX-M4-SOFT:  .eabi_attribute 6, 13
-; CORTEX-M4-SOFT:  .eabi_attribute 7, 77
-; CORTEX-M4-SOFT:  .eabi_attribute 8, 0
-; CORTEX-M4-SOFT:  .eabi_attribute 9, 2
-; CORTEX-M4-SOFT:  .fpu fpv4-sp-d16
-; CORTEX-M4-SOFT-NOT:   .eabi_attribute 19
-;; We default to IEEE 754 compliance
-; CORTEX-M4-SOFT:  .eabi_attribute 20, 1
-; CORTEX-M4-SOFT:  .eabi_attribute 21, 1
-; CORTEX-M4-SOFT-NOT:  .eabi_attribute 22
-; CORTEX-M4-SOFT:  .eabi_attribute 23, 3
-; CORTEX-M4-SOFT:  .eabi_attribute 24, 1
-; CORTEX-M4-SOFT:  .eabi_attribute 25, 1
-; CORTEX-M4-SOFT:  .eabi_attribute 27, 1
-; CORTEX-M4-SOFT-NOT:  .eabi_attribute 28
-; CORTEX-M4-SOFT:  .eabi_attribute 36, 1
-; CORTEX-M4-SOFT:  .eabi_attribute 38, 1
-; CORTEX-M4-SOFT-NOT:  .eabi_attribute 42
-; CORTEX-M4-SOFT-NOT:  .eabi_attribute 44
-; CORTEX-M4-SOFT-NOT:  .eabi_attribute 68
+; CORTEX-M4:  .cpu cortex-m4
+; CORTEX-M4:  .eabi_attribute 6, 13
+; CORTEX-M4:  .eabi_attribute 7, 77
+; CORTEX-M4:  .eabi_attribute 8, 0
+; CORTEX-M4:  .eabi_attribute 9, 2
+; CORTEX-M4-NOT:   .fpu fpv4-sp-d16
+; CORTEX-M4-NOT:   .eabi_attribute 19
+;; We default to IEEE 754 compliance
+; CORTEX-M4:  .eabi_attribute 20, 1
+; CORTEX-M4:  .eabi_attribute 21, 1
+; CORTEX-M4-NOT:  .eabi_attribute 22
+; CORTEX-M4:  .eabi_attribute 23, 3
+; CORTEX-M4:  .eabi_attribute 24, 1
+; CORTEX-M4:  .eabi_attribute 25, 1
+; CORTEX-M4-NOT:  .eabi_attribute 27
+; CORTEX-M4-NOT:  .eabi_attribute 28
+; CORTEX-M4-NOT:  .eabi_attribute 36
+; CORTEX-M4:  .eabi_attribute 38, 1
+; CORTEX-M4-NOT:  .eabi_attribute 42
+; CORTEX-M4-NOT:  .eabi_attribute 44
+; CORTEX-M4-NOT:  .eabi_attribute 68
+
+; CORTEX-M4F-SOFT:  .cpu cortex-m4f
+; CORTEX-M4F-SOFT:  .eabi_attribute 6, 13
+; CORTEX-M4F-SOFT:  .eabi_attribute 7, 77
+; CORTEX-M4F-SOFT:  .eabi_attribute 8, 0
+; CORTEX-M4F-SOFT:  .eabi_attribute 9, 2
+; CORTEX-M4F-SOFT:  .fpu fpv4-sp-d16
+; CORTEX-M4F-SOFT-NOT:   .eabi_attribute 19
+;; We default to IEEE 754 compliance
+; CORTEX-M4F-SOFT:  .eabi_attribute 20, 1
+; CORTEX-M4F-SOFT:  .eabi_attribute 21, 1
+; CORTEX-M4F-SOFT-NOT:  .eabi_attribute 22
+; CORTEX-M4F-SOFT:  .eabi_attribute 23, 3
+; CORTEX-M4F-SOFT:  .eabi_attribute 24, 1
+; CORTEX-M4F-SOFT:  .eabi_attribute 25, 1
+; CORTEX-M4F-SOFT:  .eabi_attribute 27, 1
+; CORTEX-M4F-SOFT-NOT:  .eabi_attribute 28
+; CORTEX-M4F-SOFT:  .eabi_attribute 36, 1
+; CORTEX-M4F-SOFT:  .eabi_attribute 38, 1
+; CORTEX-M4F-SOFT-NOT:  .eabi_attribute 42
+; CORTEX-M4F-SOFT-NOT:  .eabi_attribute 44
+; CORTEX-M4F-SOFT-NOT:  .eabi_attribute 68
 
-; CORTEX-M4-SOFT-FAST-NOT:   .eabi_attribute 19
-;; The M4 defaults to a VFPv4 FPU, so it flushes preseving sign when
+; CORTEX-M4F-SOFT-FAST-NOT:   .eabi_attribute 19
+;; The M4F defaults to a VFPv4 FPU, so it flushes preseving sign when
 ;; -ffast-math is specified.
-; CORTEX-M4-SOFT-FAST:  .eabi_attribute 20, 2
-; CORTEX-M4-SOFT-FAST-NOT:  .eabi_attribute 21
-; CORTEX-M4-SOFT-FAST-NOT:  .eabi_attribute 22
-; CORTEX-M4-SOFT-FAST:  .eabi_attribute 23, 1
-
-; CORTEX-M4-HARD:  .cpu cortex-m4
-; CORTEX-M4-HARD:  .eabi_attribute 6, 13
-; CORTEX-M4-HARD:  .eabi_attribute 7, 77
-; CORTEX-M4-HARD:  .eabi_attribute 8, 0
-; CORTEX-M4-HARD:  .eabi_attribute 9, 2
-; CORTEX-M4-HARD:  .fpu fpv4-sp-d16
-; CORTEX-M4-HARD-NOT:   .eabi_attribute 19
-;; We default to IEEE 754 compliance
-; CORTEX-M4-HARD:  .eabi_attribute 20, 1
-; CORTEX-M4-HARD:  .eabi_attribute 21, 1
-; CORTEX-M4-HARD-NOT:  .eabi_attribute 22
-; CORTEX-M4-HARD:  .eabi_attribute 23, 3
-; CORTEX-M4-HARD:  .eabi_attribute 24, 1
-; CORTEX-M4-HARD:  .eabi_attribute 25, 1
-; CORTEX-M4-HARD:  .eabi_attribute 27, 1
-; CORTEX-M4-HARD:  .eabi_attribute 28, 1
-; CORTEX-M4-HARD:  .eabi_attribute 36, 1
-; CORTEX-M4-HARD:  .eabi_attribute 38, 1
-; CORTEX-M4-HARD-NOT:  .eabi_attribute 42
-; CORTEX-M4-HARD-NOT:  .eabi_attribute 44
-; CORTEX-M4-HARD-NOT:  .eabi_attribute 68
+; CORTEX-M4F-SOFT-FAST:  .eabi_attribute 20, 2
+; CORTEX-M4F-SOFT-FAST-NOT:  .eabi_attribute 21
+; CORTEX-M4F-SOFT-FAST-NOT:  .eabi_attribute 22
+; CORTEX-M4F-SOFT-FAST:  .eabi_attribute 23, 1
+
+; CORTEX-M4F-HARD:  .cpu cortex-m4f
+; CORTEX-M4F-HARD:  .eabi_attribute 6, 13
+; CORTEX-M4F-HARD:  .eabi_attribute 7, 77
+; CORTEX-M4F-HARD:  .eabi_attribute 8, 0
+; CORTEX-M4F-HARD:  .eabi_attribute 9, 2
+; CORTEX-M4F-HARD:   .fpu fpv4-sp-d16
+; CORTEX-M4F-HARD-NOT:   .eabi_attribute 19
+;; We default to IEEE 754 compliance
+; CORTEX-M4F-HARD:  .eabi_attribute 20, 1
+; CORTEX-M4F-HARD:  .eabi_attribute 21, 1
+; CORTEX-M4F-HARD-NOT:  .eabi_attribute 22
+; CORTEX-M4F-HARD:  .eabi_attribute 23, 3
+; CORTEX-M4F-HARD:  .eabi_attribute 24, 1
+; CORTEX-M4F-HARD:  .eabi_attribute 25, 1
+; CORTEX-M4F-HARD:  .eabi_attribute 27, 1
+; CORTEX-M4F-HARD:  .eabi_attribute 28, 1
+; CORTEX-M4F-HARD:  .eabi_attribute 36, 1
+; CORTEX-M4F-HARD:  .eabi_attribute 38, 1
+; CORTEX-M4F-HARD-NOT:  .eabi_attribute 42
+; CORTEX-M4F-HARD-NOT:  .eabi_attribute 44
+; CORTEX-M4F-HARD-NOT:  .eabi_attribute 68
 
-; CORTEX-M4-HARD-FAST-NOT:   .eabi_attribute 19
-;; The M4 defaults to a VFPv4 FPU, so it flushes preseving sign when
+; CORTEX-M4F-HARD-FAST-NOT:   .eabi_attribute 19
+;; The M4F defaults to a VFPv4 FPU, so it flushes preseving sign when
 ;; -ffast-math is specified.
-; CORTEX-M4-HARD-FAST:  .eabi_attribute 20, 2
-; CORTEX-M4-HARD-FAST-NOT:  .eabi_attribute 21
-; CORTEX-M4-HARD-FAST-NOT:  .eabi_attribute 22
-; CORTEX-M4-HARD-FAST:  .eabi_attribute 23, 1
+; CORTEX-M4F-HARD-FAST:  .eabi_attribute 20, 2
+; CORTEX-M4F-HARD-FAST-NOT:  .eabi_attribute 21
+; CORTEX-M4F-HARD-FAST-NOT:  .eabi_attribute 22
+; CORTEX-M4F-HARD-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-M7:  .cpu    cortex-m7
 ; CORTEX-M7:  .eabi_attribute 6, 13
 ; CORTEX-M7:  .eabi_attribute 7, 77
 ; CORTEX-M7:  .eabi_attribute 8, 0
 ; CORTEX-M7:  .eabi_attribute 9, 2
 ; CORTEX-M7-SOFT-NOT: .fpu
 ; CORTEX-M7-SINGLE:  .fpu fpv5-sp-d16

 ; CORTEX-R4F-NOT:  .eabi_attribute 44
 ; CORTEX-R4F-NOT:  .eabi_attribute 68
 
 ; CORTEX-R5:  .cpu cortex-r5
 ; CORTEX-R5:  .eabi_attribute 6, 10
 ; CORTEX-R5:  .eabi_attribute 7, 82
 ; CORTEX-R5:  .eabi_attribute 8, 1
 ; CORTEX-R5:  .eabi_attribute 9, 2
-; CORTEX-R5:  .fpu vfpv3-d16
+; CORTEX-R5-NOT:   .fpu vfpv3-d16
 ; CORTEX-R5-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-R5:  .eabi_attribute 20, 1
 ; CORTEX-R5:  .eabi_attribute 21, 1
 ; CORTEX-R5-NOT:  .eabi_attribute 22
 ; CORTEX-R5:  .eabi_attribute 23, 3
 ; CORTEX-R5:  .eabi_attribute 24, 1
 ; CORTEX-R5:  .eabi_attribute 25, 1
 ; CORTEX-R5-NOT:  .eabi_attribute 27, 1
 ; CORTEX-R5-NOT:  .eabi_attribute 28
 ; CORTEX-R5-NOT:  .eabi_attribute 36
 ; CORTEX-R5:  .eabi_attribute 38, 1
 ; CORTEX-R5-NOT:  .eabi_attribute 42
 ; CORTEX-R5:  .eabi_attribute 44, 2
 ; CORTEX-R5-NOT:  .eabi_attribute 68
 
+; CORTEX-R5F:  .cpu cortex-r5f
+; CORTEX-R5F:  .eabi_attribute 6, 10
+; CORTEX-R5F:  .eabi_attribute 7, 82
+; CORTEX-R5F:  .eabi_attribute 8, 1
+; CORTEX-R5F:  .eabi_attribute 9, 2
+; CORTEX-R5F:  .fpu vfpv3-d16
+; CORTEX-R5F-NOT:   .eabi_attribute 19
+;; We default to IEEE 754 compliance
+; CORTEX-R5F:  .eabi_attribute 20, 1
+; CORTEX-R5F:  .eabi_attribute 21, 1
+; CORTEX-R5F-NOT:  .eabi_attribute 22
+; CORTEX-R5F:  .eabi_attribute 23, 3
+; CORTEX-R5F:  .eabi_attribute 24, 1
+; CORTEX-R5F:  .eabi_attribute 25, 1
+; CORTEX-R5F-NOT:  .eabi_attribute 27
+; CORTEX-R5F-NOT:  .eabi_attribute 28
+; CORTEX-R5F-NOT:  .eabi_attribute 36
+; CORTEX-R5F:  .eabi_attribute 38, 1
+; CORTEX-R5F-NOT:  .eabi_attribute 42
+; CORTEX-R5F:  .eabi_attribute 44, 2
+; CORTEX-R5F-NOT:  .eabi_attribute 68
+
 ; CORTEX-R5-FAST-NOT:   .eabi_attribute 19
 ;; The R5 has the VFPv3 FP unit, which always flushes preserving sign.
 ; CORTEX-R5-FAST:  .eabi_attribute 20, 2
 ; CORTEX-R5-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-R5-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-R5-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-R7:  .cpu cortex-r7

test/CodeGen/ARM/darwin-eabi.ll

 ; RUN: llc -mtriple=thumbv7m-apple-darwin -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-M3
-; RUN: llc -mtriple=thumbv7em-apple-darwin -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-M4
+; RUN: llc -mtriple=thumbv7em-apple-darwin -mcpu=cortex-m4f < %s | FileCheck %s --check-prefix=CHECK-M4F
 ; RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-M3
-; RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-M4
+; RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4f < %s | FileCheck %s --check-prefix=CHECK-M4F
 
 define float @float_op(float %lhs, float %rhs) {
   %sum = fadd float %lhs, %rhs
   ret float %sum
 ; CHECK-M3-LABEL: float_op:
 ; CHECK-M3: bl ___addsf3
 
-; CHECK-M4-LABEL: float_op:
-; CHECK-M4: vadd.f32
+; CHECK-M4F-LABEL: float_op:
+; CHECK-M4F: vadd.f32
 }
 
 define double @double_op(double %lhs, double %rhs) {
   %sum = fadd double %lhs, %rhs
   ret double %sum
 ; CHECK-M3-LABEL: double_op:
 ; CHECK-M3: bl ___adddf3
 
-; CHECK-M4-LABEL: double_op:
-; CHECK-M4: {{(blx|b.w)}} ___adddf3
+; CHECK-M4F-LABEL: double_op:
+; CHECK-M4F: {{(blx|b.w)}} ___adddf3
 }

test/CodeGen/ARM/special-reg.ll

 ; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ARM --check-prefix=ACORE
-; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=ARM --check-prefix=MCORE
+; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4f 2>&1 | FileCheck %s --check-prefix=ARM --check-prefix=MCORE
 
 define i32 @read_i32_encoded_register() nounwind {
 entry:
 ; ARM-LABEL: read_i32_encoded_register:
 ; ARM: mrc p1, #2, r0, c3, c4, #5
   %reg = call i32 @llvm.read_register.i32(metadata !0)
   ret i32 %reg
 }

test/CodeGen/Thumb2/cortex-fp.ll

 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM3
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM4
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m4f | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM4F
 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM7
 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXA8
 
 
 define float @foo(float %a, float %b) {
 entry:
 ; CHECK-LABEL: foo:
 ; CORTEXM3: bl ___mulsf3
-; CORTEXM4: vmul.f32  s
+; CORTEXM4F: vmul.f32  s
 ; CORTEXM7: vmul.f32  s
 ; CORTEXA8: vmul.f32  d
   %0 = fmul float %a, %b
   ret float %0
 }
 
 define double @bar(double %a, double %b) {
 entry:
 ; CHECK-LABEL: bar:
   %0 = fmul double %a, %b
 ; CORTEXM3: bl ___muldf3
-; CORTEXM4: {{bl|b.w}} ___muldf3
+; CORTEXM4F: {{bl|b.w}} ___muldf3
 ; CORTEXM7: vmul.f64  d
 ; CORTEXA8: vmul.f64  d
   ret double %0
 }

test/CodeGen/Thumb2/float-cmp.ll

 ; RUN: llc < %s -mtriple=thumbv7-none-eabi   -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=NONE
-; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4f | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP
 
 
 
 define i1 @cmp_f_false(float %a, float %b) {
 ; CHECK-LABEL: cmp_f_false:
 ; NONE: movs r0, #0

test/CodeGen/Thumb2/float-intrinsics-double.ll

 ; RUN: llc < %s -mtriple=thumbv7-none-eabi   -mcpu=cortex-m3                    | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE
-; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4                    | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4f                   | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7                    | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP  -check-prefix=FP-ARMv8
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 -mattr=+fp-only-sp | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7                    | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=VFP4
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a57                   | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=FP-ARMv8
 
 declare double     @llvm.sqrt.f64(double %Val)
 define double @sqrt_d(double %a) {
 ; CHECK-LABEL: sqrt_d:

test/CodeGen/Thumb2/float-intrinsics-float.ll

 ; RUN: llc < %s -mtriple=thumbv7-none-eabi   -mcpu=cortex-m3                    | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE
-; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4                    | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=VMLA
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4f                   | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=VMLA
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7                    | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP  -check-prefix=FP-ARMv8  -check-prefix=VMLA
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 -mattr=+fp-only-sp | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=FP-ARMv8 -check-prefix=VMLA
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7                    | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=VFP4 -check-prefix=NO-VMLA
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a57                   | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=FP-ARMv8 -check-prefix=VMLA
 
 declare float     @llvm.sqrt.f32(float %Val)
 define float @sqrt_f(float %a) {
 ; CHECK-LABEL: sqrt_f:

test/CodeGen/Thumb2/float-ops.ll

 ; RUN: llc < %s -mtriple=thumbv7-none-eabi   -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=NONE
-; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=VFP4-ALL
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4f | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=VFP4-ALL
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=FP-ARMv8
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP4-ALL -check-prefix=VFP4-DP
 
 define float @add_f(float %a, float %b) {
 entry:
 ; CHECK-LABEL: add_f:
 ; NONE: bl __aeabi_fadd
 ; HARD: vadd.f32  s0, s0, s1

test/MC/ARM/vfp4.s

 @ RUN: llvm-mc < %s -triple armv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4   | FileCheck %s --check-prefix=ARM
 @ RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=THUMB
-@ RUN: not llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mcpu=cortex-m4 > %t 2> %t2
+@ RUN: not llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mcpu=cortex-m4f > %t 2> %t2
 @ RUN:     FileCheck %s < %t --check-prefix=THUMB_V7EM
 @ RUN:     FileCheck %s < %t2 --check-prefix=THUMB_V7EM-ERRORS
 
 @ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee]
 @ THUMB: vfma.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xa1,0x0b]
 @ THUMB_V7EM-ERRORS: error: invalid operand for instruction
 @ THUMB_V7EM-ERRORS-NEXT: vfma.f64 d16, d18, d17
 vfma.f64 d16, d18, d17