[ARM SEH 6] [ARM] Add SEH opcodes in frame lowering

[mstorsjo]

Summary

Skip inserting regular CFI instructions if using WinCFI.

This is based a fair amount on the corresponding ARM64 implementation,
but instead of trying to insert the SEH opcodes one by one where
we generate other prolog/epilog instructions, we try to walk over the
whole prolog/epilog range and insert them. This is done because in
many cases, the exact number of instructions inserted is abstracted
away deeper.

For some cases, we manually insert specific SEH opcodes directly where
instructions are generated, where the automatic mapping of instructions
to SEH opcodes doesn't hold up (e.g. for __chkstk stack probes).

[mstorsjo]

FYI regarding this patchset; this set of patches allows generating SEH unwind info for plain unwind tables, and it works fine for itanium exception handling in mingw mode.

For the MSVC mode SEH __try, and MSVC mode C++ exceptions, more code generation changes are needed. Hopefully those changes are kinda straightforward (I presume it should be possible to just borrow bits from the AArch64 target), but I haven't implemented them - hopefully someone else can pick that up if the rest of these changes end up mergeable at some point.

[efriedma]

llvm/lib/Target/ARM/ARMFrameLowering.cpp

1126

We shouldn't be encoding stack realignment into the unwind data. It's basically a dynamic allocation: we have to emit a frame pointer before we realign the stack, and we should cut off the unwind prologue immediately after the frame pointer is set up.

[mstorsjo]

llvm/lib/Target/ARM/ARMFrameLowering.cpp

1126

Right, that'd be even cleaner. (This part gets tested only in the next patch which tweaks the frame pointers, and all the later opcodes are nops in that case. So cutting off the prologue at that point sounds like a good strategy.)

[mstorsjo]

Updated to cut the prologue short, omitting parts that realign the stack. Updated to use separate .seh_nop directives for epilogues.

[mstorsjo]

Since the beginning, I've had to disable PostRAScheduler, because it would reshuffle instructions independently of their associated SEH_* machineinstructions. I tried to compare it to the AArch64 implementation, but there, PostRAScheduler doesn't seem to be executed at all, so that didn't give any extra info about how to avoid it. So for this case, I tweaked ARMSubtarget::enablePostRAScheduler to disable the pass when producing SEH.

Compared to the AArch64 case, the ends of epilogues are slightly more problematic here. On AArch64, the epilogue end is before the ret instruction. On ARM, e.g. an bx lr (ARM::tBX_RET) is now followed by a ARM::SEH_Nop and ARM::SEH_EpilogEnd. As the ARM::tBX_RET is a terminator, the SEH_Nop and SEH_EpilogEnd that follows it also must be terminators, otherwise the machine instruction verifier bails out. Due to this, I've added a separate ARM::SEH_Nop_Ret which is marked a terminator.

After updating to use separate nop instructions, the end of an epilogue tBX_RET, SEH_EpilogEnd (nop=1) was changed into tBX_RET, SEH_Nop_Ret, SEH_EpilogEnd. This causes the machine block placement pass to do tail merging of multiple such epilogues in one function (where it previously didn't), which loses the SEH_Nop_ Ret and SEH_EpilogEnd for all but one of those epilogues.

What's the correct way of making sure that tail merging doesn't try to touch the SEH_* instructions? This doesn't seem to be happening on AArch64.

I looked into making a bundle of the rBX_RET, SEH_Nop_Ret, SEH_EpilogEnd (with an finalizeBundle over those three instructions), but that later breaks assembly output with a failed assert "Cannot print this instruction.". I presume that would require something to unbundle them later?

When looking into the tail merging pass, I noticed that if MachineInstr::isCFIInstruction() would return true for the SEH_* instructions, it could be handled differently and maybe the pass wouldn't break them. But it doesn't seem trivial to test out making that return true for the SEH_* instructions, so I don't know if that would fix any of these issues or not.

[mstorsjo]

In D125648#3530563, @mstorsjo wrote:

When looking into the tail merging pass, I noticed that if MachineInstr::isCFIInstruction() would return true for the SEH_* instructions, it could be handled differently and maybe the pass wouldn't break them. But it doesn't seem trivial to test out making that return true for the SEH_* instructions, so I don't know if that would fix any of these issues or not.

I managed to make a PoC of that, where the core of the changes were this:

diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index cb6698c12d8e..15bdfdb5d7eb 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h 
@@ -112,6 +112,7 @@ public:
     NoMerge      = 1 << 15,             // Passes that drop source location info
                                         // (e.g. branch folding) should skip
                                         // this instruction.
+    CFILike      = 1 << 16,
   };
 
 private:
@@ -1207,7 +1208,7 @@ public:
   }
 
   // True if the instruction represents a position in the function.
-  bool isPosition() const { return isLabel() || isCFIInstruction(); }
+  bool isPosition() const { return isLabel() || isCFIInstruction() || getFlag(C
FILike); }
 
   bool isNonListDebugValue() const {
     return getOpcode() == TargetOpcode::DBG_VALUE;

diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding
.cpp
index 76f6a00b718e..de81ca874800 100644
--- a/llvm/lib/CodeGen/BranchFolding.cpp
+++ b/llvm/lib/CodeGen/BranchFolding.cpp
@@ -294,7 +294,7 @@ static unsigned HashEndOfMBB(const MachineBasicBlock &MBB) {
 
 /// Whether MI should be counted as an instruction when calculating common tail
.
 static bool countsAsInstruction(const MachineInstr &MI) {
-  return !(MI.isDebugInstr() || MI.isCFIInstruction());
+  return !(MI.isDebugInstr() || MI.isCFIInstruction() || MI.getFlag(MachineInst
r::CFILike));
 }
 
 /// Iterate backwards from the given iterator \p I, towards the beginning of th
e

This fixes the issue I was seeing (by setting that flag on all the SEH_* instructions). However, I'm not sure if that actually avoids the real issue (of splitting off the SEH_* instructions from the regular instructions) or if it just makes the tail merging no longer seem worthwhile doing. It doesn't fix the need to disable the PostRAScheduler in any case.

(Also, adding this new MachineInstr flag is problematic, as it requires widening MachineInstr::Flags from uint16_t to uint32_t.)

[efriedma]

For scheduling, the AArch64 backend overrides "isSchedulingBoundary()" for SEH instructions.

I don't think we ever ran into issues with tail merge... maybe setting MachineInstr:::NoMerge would work?

[mstorsjo]

In D125648#3531768, @efriedma wrote:

For scheduling, the AArch64 backend overrides "isSchedulingBoundary()" for SEH instructions.

Oh, thanks, that does fix the issue with PostRAScheduling - thanks!

I don't think we ever ran into issues with tail merge... maybe setting MachineInstr:::NoMerge would work?

Yup, that does seem to do the trick too. Thanks!

[mstorsjo]

No longer need to disable PostRAScheduler, and fixed tail merging by setting the MachineInst::NoMerge flag.

[mstorsjo]

Plain rebase, no functional change.

[efriedma]

llvm/lib/Target/ARM/ARMFrameLowering.cpp

300

report_fatal_error (here and other places you abort()).

304

Maybe add t2MOVi16/t2MOVTi16 here?

[mstorsjo]

Moved all SEH_Nop insertion for __chkstk into insertSEH (with only one SEH instruction being manually added there, for the SEH_StackAlloc after the __chkstk call).

Switched to report_fatal_error instead of a manual printout and std::abort().

[efriedma]

llvm/lib/Target/ARM/ARMFrameLowering.cpp

315

Looking at this again, this is actually sort of scary. In particular, this is dependent on looking into the future: trying to predict what Thumb2SizeReduction will do with a given instruction. Which is at best fragile, at worst broken if Thumb2SizeReduction doesn't run, or decides to do something different.

I guess you can sort of predict what will happen for t2MOVi16 and t2LDMIA_RET/t2LDMIA_UPD/t2STMDB_UPD. But it's less clear in other cases; we currently don't optimize t2SUBspImm, but we could. Or for TCRETURNdi, we don't actually decide the size until we hit the assembler.

I'm thinking we might want to disable Thumb2SizeReduction on instructions with SEH opcodes. (Or equivalently, on FrameSetup instructions if SEH unwind is enabled.)

[mstorsjo]

llvm/lib/Target/ARM/ARMFrameLowering.cpp

315

Thanks - this was indeed one of my fears initially. In practice, these guesses for what it will end up like have worked for all the code I've tested this on so far. But it's indeed brittle.

Skipping Thumb2SizeReduction for FrameSetup/FrameDestroy when SEH unwind is enabled seems to work fine though, so that alleviates most of the issue. (As a future TODO, one could maybe consider rewriting the MI to a narrow form already at this point, for the few opcodes where it matters?)

For TCRETURNdi, I also feared that it would be an issue, but it hasn't cropped up. (Or maybe the nondeterminate length of the instruction makes it unable to calculate the length of the epilogue at that point? And thus just skips the check...)

But it seems like the pseudo expansion of TCRETURNdi already has got such a case; MachO also requires strictly Thumb2 wide branches for tail calls, so we can opt in to that logic for SEH too.

[mstorsjo]

Skip Thumb2SizeReduction for SEH prologs/epilogs, and force tail calls to wide instructions (just like on MachO), to make sure that the unwind info actually matches the width of the final instructions without heuristics about what later passes will do.

[efriedma]

LGTM

llvm/lib/Target/ARM/ARMFrameLowering.cpp

315

I think you might need to implement narrowing for "push" and "pop", but probably not anything else. But in any case, it doesn't need to be in this patch.

llvm/lib/Target/ARM/ARMAsmPrinter.cpp

void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
   }
   case ARM::t2SpeculationBarrierSBEndBB: {
     // Print SB
     MCInst TmpInstSB;
     TmpInstSB.setOpcode(ARM::t2SB);
     EmitToStreamer(*OutStreamer, TmpInstSB);
     return;
   }
+
+  case ARM::SEH_StackAlloc:
+    ATS.emitARMWinCFIAllocStack(MI->getOperand(0).getImm(),
+                                MI->getOperand(1).getImm());
+    return;
+
+  case ARM::SEH_SaveRegs:
+  case ARM::SEH_SaveRegs_Ret:
+    ATS.emitARMWinCFISaveRegMask(MI->getOperand(0).getImm(),
+                                 MI->getOperand(1).getImm());
+    return;
+
+  case ARM::SEH_SetFP:
+    ATS.emitARMWinCFISetFP(MI->getOperand(0).getImm());
+    return;
+
+  case ARM::SEH_SaveFRegs:
+    ATS.emitARMWinCFISaveFRegs(MI->getOperand(0).getImm(),
+                               MI->getOperand(1).getImm());
+    return;
+
+  case ARM::SEH_SaveLR:
+    ATS.emitARMWinCFISaveLR(MI->getOperand(0).getImm());
+    return;
+
+  case ARM::SEH_Nop:
+    ATS.emitARMWinCFINop(MI->getOperand(0).getImm());
+    return;
+
+  case ARM::SEH_PrologEnd:
+    ATS.emitARMWinCFIPrologEnd();
+    return;
+
+  case ARM::SEH_EpilogStart:
+    ATS.emitARMWinCFIEpilogStart();
+    return;
+
+  case ARM::SEH_EpilogEnd:
+    ATS.emitARMWinCFIEpilogEnd(MI->getOperand(0).getImm(),
+                               MI->getOperand(1).getImm());
+    return;
   }
 
   MCInst TmpInst;
   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
 
   EmitToStreamer(*OutStreamer, TmpInst);
 }
 

llvm/lib/Target/ARM/ARMBaseRegisterInfo.h

bool shouldCoalesce(MachineInstr *MI,
                       unsigned DstSubReg,
                       const TargetRegisterClass *NewRC,
                       LiveIntervals &LIS) const override;
 
   bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
                             unsigned DefSubReg,
                             const TargetRegisterClass *SrcRC,
                             unsigned SrcSubReg) const override;
+
+  int getSEHRegNum(unsigned i) const { return getEncodingValue(i); }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

case ARM::VBSPq: {
       }
       MI.eraseFromParent();
       return true;
     }
 
     case ARM::TCRETURNdi:
     case ARM::TCRETURNri: {
       MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
+      if (MBBI->getOpcode() == ARM::SEH_EpilogEnd)
+        MBBI--;
       assert(MBBI->isReturn() &&
              "Can only insert epilog into returning blocks");
       unsigned RetOpcode = MBBI->getOpcode();
       DebugLoc dl = MBBI->getDebugLoc();
       const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
           MBB.getParent()->getSubtarget().getInstrInfo());
 
       // Tail call return: adjust the stack pointer and jump to callee.
       MBBI = MBB.getLastNonDebugInstr();
+      if (MBBI->getOpcode() == ARM::SEH_EpilogEnd)
+        MBBI--;
       MachineOperand &JumpTarget = MBBI->getOperand(0);
 
       // Jump to label or value in register.
       if (RetOpcode == ARM::TCRETURNdi) {
         unsigned TCOpcode =
             STI->isThumb()
                 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND)
                 : ARM::TAILJMPd;

llvm/lib/Target/ARM/ARMFrameLowering.cpp

 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TargetOpcodes.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/Attributes.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/IR/Function.h"
+#include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDwarf.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
if (IsTailCallReturn) {
     // LowerFormalArguments. This will, of course, be zero for the C calling
     // convention.
     ArgumentPopSize = AFI->getArgumentStackToRestore();
   }
 
   return ArgumentPopSize;
 }
 
+static bool needsWinCFI(const MachineFunction &MF) {
+  const Function &F = MF.getFunction();
+  return MF.getTarget().getMCAsmInfo()->usesWindowsCFI() &&
+         F.needsUnwindTableEntry();
+}
+
+// Given a load or a store instruction, generate an appropriate unwinding SEH
+// code on Windows.
+static MachineBasicBlock::iterator insertSEH(MachineBasicBlock::iterator MBBI,
+                                             const TargetInstrInfo &TII,
+                                             unsigned Flags) {
+  unsigned Opc = MBBI->getOpcode();
+  MachineBasicBlock *MBB = MBBI->getParent();
+  MachineFunction &MF = *MBB->getParent();
+  DebugLoc DL = MBBI->getDebugLoc();
+  MachineInstrBuilder MIB;
+  const ARMSubtarget &Subtarget = MF.getSubtarget<ARMSubtarget>();
+  const ARMBaseRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
+
+  switch (Opc) {
+  default:
+    errs() << "No SEH Opcode for instruction " << TII.getName(Opc) << "\n";
+    std::abort();
+    break;
+  case ARM::t2ADDri:   // add.w r11, sp, #xx
+  case ARM::t2ADDri12: // add.w r11, sp, #xx
+  case ARM::t2SUBri:   // sub.w r4, r11, #xx
+    // These arm harmless if used for just setting up a frame pointer,
+    // but that frame pointer can't be relied upon for unwinding, unless
+    // set up with SEH_SetFP.
+    MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop))
+              .addImm(/*Wide=*/1)
+              .setMIFlags(Flags);
+    break;
+  case ARM::t2LDMIA_RET:
+  case ARM::t2LDMIA_UPD:
+  case ARM::t2STMDB_UPD: {
+    unsigned Mask = 0;
+    bool Wide = false;
+    for (unsigned i = 4, NumOps = MBBI->getNumOperands(); i != NumOps; ++i) {
+      const MachineOperand &MO = MBBI->getOperand(i);
+      if (!MO.isReg() || MO.isImplicit())
+        continue;
+      unsigned Reg = RegInfo->getSEHRegNum(MO.getReg());
+      if (Reg == 15)
+        Reg = 14;
+      if (Reg >= 8 && Reg <= 13)
+        Wide = true;
+      else if (Opc == ARM::t2LDMIA_UPD && Reg == 14)
+        Wide = true;
+      Mask |= 1 << Reg;
+    }
+    unsigned SEHOpc =
+        (Opc == ARM::t2LDMIA_RET) ? ARM::SEH_SaveRegs_Ret : ARM::SEH_SaveRegs;
+    MIB = BuildMI(MF, DL, TII.get(SEHOpc))
+              .addImm(Mask)
+              .addImm(Wide ? 1 : 0)
+              .setMIFlags(Flags);
+    break;
+  }
+  case ARM::VSTMDDB_UPD:
+  case ARM::VLDMDIA_UPD: {
+    int First = -1, Last = 0;
+    for (unsigned i = 4, NumOps = MBBI->getNumOperands(); i != NumOps; ++i) {
+      const MachineOperand &MO = MBBI->getOperand(i);
+      unsigned Reg = RegInfo->getSEHRegNum(MO.getReg());
+      if (First == -1)
+        First = Reg;
+      Last = Reg;
+    }
+    MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveFRegs))
+              .addImm(First)
+              .addImm(Last)
+              .setMIFlags(Flags);
+    break;
+  }
+  case ARM::tSUBspi:
+  case ARM::tADDspi:
+    MIB = BuildMI(MF, DL, TII.get(ARM::SEH_StackAlloc))
+              .addImm(MBBI->getOperand(2).getImm() * 4)
+              .addImm(/*Wide=*/0)
+              .setMIFlags(Flags);
+    break;
+  case ARM::t2SUBspImm:
+  case ARM::t2SUBspImm12:
+  case ARM::t2ADDspImm:
+  case ARM::t2ADDspImm12:
+    MIB = BuildMI(MF, DL, TII.get(ARM::SEH_StackAlloc))
+              .addImm(MBBI->getOperand(2).getImm())
+              .addImm(/*Wide=*/1)
+              .setMIFlags(Flags);
+    break;
+
+  case ARM::tMOVr:
+    if (MBBI->getOperand(1).getReg() == ARM::SP &&
+        (Flags & MachineInstr::FrameSetup)) {
+      unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
+      MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SetFP))
+                .addImm(Reg)
+                .setMIFlags(Flags);
+    } else if (MBBI->getOperand(0).getReg() == ARM::SP &&
+               (Flags & MachineInstr::FrameDestroy)) {
+      unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
+      MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SetFP))
+                .addImm(Reg)
+                .setMIFlags(Flags);
+    } else {
+      MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop))
+                .addImm(/*Wide=*/0)
+                .setMIFlags(Flags);
+    }
+    break;
+
+  case ARM::t2BFC:
+    MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop))
+              .addImm(/*Wide=*/1)
+              .setMIFlags(Flags);
+    break;
+
+  case ARM::tBX_RET:
+  case ARM::TCRETURNri:
+    MIB = BuildMI(MF, DL, TII.get(ARM::SEH_EpilogEnd))
+              .addImm(/*Nop=*/1)
+              .addImm(/*Wide=*/0)
+              .setMIFlags(Flags);
+    break;
+
+  case ARM::TCRETURNdi:
+    MIB = BuildMI(MF, DL, TII.get(ARM::SEH_EpilogEnd))
+              .addImm(/*Nop=*/1)
+              .addImm(/*Wide=*/1)
+              .setMIFlags(Flags);
+    break;
+  }
+  auto I = MBB->insertAfter(MBBI, MIB);
+  switch (Opc) {
+  case ARM::t2LDMIA_RET:
+    MIB = BuildMI(MF, DL, TII.get(ARM::SEH_EpilogEnd))
+              .addImm(/*Nop=*/0)
+              .addImm(/*Wide=*/0)
+              .setMIFlags(Flags);
+    I = MBB->insertAfter(I, MIB);
+    break;
+  }
+  return I;
+}
+
+static bool isSEH(MachineBasicBlock::iterator &MBBI) {
+  unsigned Opc = MBBI->getOpcode();
+  switch (Opc) {
+  case ARM::SEH_StackAlloc:
+  case ARM::SEH_SaveRegs:
+  case ARM::SEH_SetFP:
+  case ARM::SEH_SaveFRegs:
+  case ARM::SEH_SaveLR:
+  case ARM::SEH_Nop:
+  case ARM::SEH_PrologEnd:
+  case ARM::SEH_EpilogStart:
+  case ARM::SEH_EpilogEnd:
+    return true;
+  default:
+    return false;
+  }
+}
+
+static MachineBasicBlock::iterator
+initMBBRange(MachineBasicBlock &MBB, const MachineBasicBlock::iterator &MBBI) {
+  if (MBBI == MBB.begin())
+    return MachineBasicBlock::iterator();
+  return std::prev(MBBI);
+}
+
+static void insertSEHRange(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator Start,
+                           const MachineBasicBlock::iterator &End,
+                           const ARMBaseInstrInfo &TII, unsigned MIFlags) {
+  if (Start.isValid())
+    Start = std::next(Start);
+  else
+    Start = MBB.begin();
+
+  for (auto MI = Start; MI != End;) {
+    auto Next = std::next(MI);
+    // Check if this instruction already has got a SEH opcode added. In that
+    // case, don't do this generic mapping.
+    if (Next != End && isSEH(Next)) {
+      MI = std::next(Next);
+      while (MI != End && isSEH(MI))
+        ++MI;
+      continue;
+    }
+    insertSEH(MI, TII, MIFlags);
+    MI = Next;
+  }
+}
+
 static void emitRegPlusImmediate(
     bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
     const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg,
     unsigned SrcReg, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags,
     ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
   if (isARM)
     emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
                             Pred, PredReg, TII, MIFlags);
void ARMFrameLowering::emitPrologue(MachineFunction &MF,
   assert(!AFI->isThumb1OnlyFunction() &&
          "This emitPrologue does not support Thumb1!");
   bool isARM = !AFI->isThumbFunction();
   Align Alignment = STI.getFrameLowering()->getStackAlign();
   unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
   unsigned NumBytes = MFI.getStackSize();
   const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
   int FPCXTSaveSize = 0;
+  bool NeedsWinCFI = needsWinCFI(MF);
 
   // Debug location must be unknown since the first debug location is used
   // to determine the end of the prologue.
   DebugLoc dl;
 
   Register FramePtr = RegInfo->getFrameRegister(MF);
 
   // Determine the sizes of each callee-save spill areas and record which frame
void ARMFrameLowering::emitPrologue(MachineFunction &MF,
 
   if (!AFI->hasStackFrame() &&
       (!STI.isTargetWindows() || !WindowsRequiresStackProbe(MF, NumBytes))) {
     if (NumBytes != 0) {
       emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
                    MachineInstr::FrameSetup);
       DefCFAOffsetCandidates.addInst(std::prev(MBBI), NumBytes, true);
     }
+    if (!NeedsWinCFI)
       DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP);
     return;
   }
 
   // Determine spill area sizes.
   for (const CalleeSavedInfo &I : CSI) {
     Register Reg = I.getReg();
     int FI = I.getFrameIdx();
     switch (Reg) {
if (AFI->getNumAlignedDPRCS2Regs() > 0) {
     // Adjust NumBytes to represent the stack slots below the DPRCS2 area.
     NumBytes += MFI.getObjectOffset(D8SpillFI);
   } else
     NumBytes = DPRCSOffset;
 
   if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) {
     uint32_t NumWords = NumBytes >> 2;
 
-    if (NumWords < 65536)
-      BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
+    MachineInstrBuilder Instr, SEH;
+    if (NumWords < 65536) {
+      Instr = BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
                   .addImm(NumWords)
                   .setMIFlags(MachineInstr::FrameSetup)
                   .add(predOps(ARMCC::AL));
-    else
-      BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
-        .addImm(NumWords)
+    } else {
+      Instr = BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
+                  .addImm(NumWords & 0xffff)
+                  .setMIFlags(MachineInstr::FrameSetup)
+                  .add(predOps(ARMCC::AL));
+      if (NeedsWinCFI) {
+        bool Wide = (NumWords & 0xffff) >= 256;
+        SEH = BuildMI(MF, dl, TII.get(ARM::SEH_Nop))
+                  .addImm(Wide ? 1 : 0)
+                  .setMIFlags(MachineInstr::FrameSetup);
+        MBB.insertAfter(Instr, SEH);
+      }
+      Instr = BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), ARM::R4)
+                  .addReg(ARM::R4)
+                  .addImm(NumWords >> 16)
+                  .setMIFlags(MachineInstr::FrameSetup)
+                  .add(predOps(ARMCC::AL));
+    }
+    if (NeedsWinCFI) {
+      SEH = BuildMI(MF, dl, TII.get(ARM::SEH_Nop))
+                .addImm(/*Wide=*/1)
                 .setMIFlags(MachineInstr::FrameSetup);
+      MBB.insertAfter(Instr, SEH);
+    }
 
     switch (TM.getCodeModel()) {
     case CodeModel::Tiny:
       llvm_unreachable("Tiny code model not available on ARM.");
     case CodeModel::Small:
     case CodeModel::Medium:
     case CodeModel::Kernel:
-      BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
+      Instr = BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
                   .add(predOps(ARMCC::AL))
                   .addExternalSymbol("__chkstk")
                   .addReg(ARM::R4, RegState::Implicit)
                   .setMIFlags(MachineInstr::FrameSetup);
+      if (NeedsWinCFI) {
+        SEH = BuildMI(MF, dl, TII.get(ARM::SEH_Nop))
+                  .addImm(/*Wide=*/1)
+                  .setMIFlags(MachineInstr::FrameSetup);
+        MBB.insertAfter(Instr, SEH);
+      }
       break;
     case CodeModel::Large:
-      BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
+      Instr = BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
                   .addExternalSymbol("__chkstk")
                   .setMIFlags(MachineInstr::FrameSetup);
+      if (NeedsWinCFI) {
+        // t2MOVi32imm above expands into two instructions; append two
+        // SEH_Nop after the pseudo instruction above. They won't get
+        // interleaved between the final movw/movt instructions, but it
+        // doesn't make any practical difference as long as the prolog/epilog
+        // start/end are in the right places.
+        for (int I = 0; I < 2; I++) {
+          SEH = BuildMI(MF, dl, TII.get(ARM::SEH_Nop))
+                    .addImm(/*Wide=*/1)
+                    .setMIFlags(MachineInstr::FrameSetup);
+          MBB.insertAfter(Instr, SEH);
+        }
+      }
 
-      BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
+      Instr = BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
                   .add(predOps(ARMCC::AL))
                   .addReg(ARM::R12, RegState::Kill)
                   .addReg(ARM::R4, RegState::Implicit)
                   .setMIFlags(MachineInstr::FrameSetup);
+      if (NeedsWinCFI) {
+        SEH = BuildMI(MF, dl, TII.get(ARM::SEH_Nop))
+                  .addImm(/*Wide=*/0)
+                  .setMIFlags(MachineInstr::FrameSetup);
+        MBB.insertAfter(Instr, SEH);
+      }
       break;
     }
 
-    BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP)
+    Instr = BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP)
                 .addReg(ARM::SP, RegState::Kill)
                 .addReg(ARM::R4, RegState::Kill)
                 .setMIFlags(MachineInstr::FrameSetup)
                 .add(predOps(ARMCC::AL))
                 .add(condCodeOp());
+    if (NeedsWinCFI) {
+      SEH = BuildMI(MF, dl, TII.get(ARM::SEH_StackAlloc))
+                .addImm(NumBytes)
+                .addImm(/*Wide=*/1)
+                .setMIFlags(MachineInstr::FrameSetup);
+      MBB.insertAfter(Instr, SEH);
+    }
     NumBytes = 0;
   }
 
   if (NumBytes) {
     // Adjust SP after all the callee-save spills.
     if (AFI->getNumAlignedDPRCS2Regs() == 0 &&
         tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, NumBytes))
       DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes);
void ARMFrameLowering::emitPrologue(MachineFunction &MF,
   // that push.
   if (HasFP) {
     MachineBasicBlock::iterator AfterPush = std::next(GPRCS1Push);
     unsigned PushSize = sizeOfSPAdjustment(*GPRCS1Push);
     emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush,
                          dl, TII, FramePtr, ARM::SP,
                          PushSize + FramePtrOffsetInPush,
                          MachineInstr::FrameSetup);
+    if (!NeedsWinCFI) {
       if (FramePtrOffsetInPush + PushSize != 0) {
         unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
             nullptr, MRI->getDwarfRegNum(FramePtr, true),
             FPCXTSaveSize + ArgRegsSaveSize - FramePtrOffsetInPush));
         BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
             .addCFIIndex(CFIIndex)
             .setMIFlags(MachineInstr::FrameSetup);
       } else {
         unsigned CFIIndex =
             MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
                 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
         BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
             .addCFIIndex(CFIIndex)
             .setMIFlags(MachineInstr::FrameSetup);
       }
     }
+  }
 
   // Now that the prologue's actual instructions are finalised, we can insert
   // the necessary DWARF cf instructions to describe the situation. Start by
   // recording where each register ended up:
-  if (GPRCS1Size > 0) {
+  if (GPRCS1Size > 0 && !NeedsWinCFI) {
     MachineBasicBlock::iterator Pos = std::next(GPRCS1Push);
     int CFIIndex;
     for (const auto &Entry : CSI) {
       Register Reg = Entry.getReg();
       int FI = Entry.getFrameIdx();
       switch (Reg) {
       case ARM::R8:
       case ARM::R9:
for (const auto &Entry : CSI) {
       Register Reg = Entry.getReg();
       int FI = Entry.getFrameIdx();
       switch (Reg) {
       case ARM::R8:
       case ARM::R9:
       case ARM::R10:
       case ARM::R11:
       case ARM::R12:
-        if (STI.splitFramePushPop(MF)) {
+        if (STI.splitFramePushPop(MF) && !NeedsWinCFI) {
           unsigned DwarfReg = MRI->getDwarfRegNum(
               Reg == ARM::R12 ? ARM::RA_AUTH_CODE : Reg, true);
           unsigned Offset = MFI.getObjectOffset(FI);
           unsigned CFIIndex = MF.addFrameInst(
               MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
           BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
               .addCFIIndex(CFIIndex)
               .setMIFlags(MachineInstr::FrameSetup);
         }
         break;
       }
     }
   }
 
   if (DPRCSSize > 0) {
     // Since vpush register list cannot have gaps, there may be multiple vpush
     // instructions in the prologue.
     MachineBasicBlock::iterator Pos = std::next(LastPush);
     for (const auto &Entry : CSI) {
       Register Reg = Entry.getReg();
       int FI = Entry.getFrameIdx();
       if ((Reg >= ARM::D0 && Reg <= ARM::D31) &&
-          (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) {
+          (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) &&
+          !NeedsWinCFI) {
         unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
         unsigned Offset = MFI.getObjectOffset(FI);
         unsigned CFIIndex = MF.addFrameInst(
             MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
         BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
             .addCFIIndex(CFIIndex)
             .setMIFlags(MachineInstr::FrameSetup);
       }
     }
   }
 
   // Now we can emit descriptions of where the canonical frame address was
   // throughout the process. If we have a frame pointer, it takes over the job
   // half-way through, so only the first few .cfi_def_cfa_offset instructions
   // actually get emitted.
+  if (!NeedsWinCFI)
     DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP);
 
   if (STI.isTargetELF() && hasFP(MF))
     MFI.setOffsetAdjustment(MFI.getOffsetAdjustment() -
                             AFI->getFramePtrSpillOffset());
 
   AFI->setFPCXTSaveAreaSize(FPCXTSaveSize);
   AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
   AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->hasStackRealignment(MF)) {
     } else {
       // We cannot use sp as source/dest register here, thus we're using r4 to
       // perform the calculations. We're emitting the following sequence:
       // mov r4, sp
       // -- use emitAligningInstructions to produce best sequence to zero
       // -- out lower bits in r4
       // mov sp, r4
       // FIXME: It will be better just to find spare register here.
-      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
+      auto Instr = BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
                        .addReg(ARM::SP, RegState::Kill)
                        .add(predOps(ARMCC::AL));
+      if (NeedsWinCFI) {
+        // This "mov r4, sp" would be mapped to ".seh_set_fp r4", but r4 doesn't
+        // contain a stable frame pointer, thus manually insert a .seh_nop
+        // here instead.
+        auto SEH = BuildMI(MF, dl, TII.get(ARM::SEH_Nop))
+                       .addImm(/*Wide=*/0)
+                       .setMIFlags(MachineInstr::FrameSetup);
+        MBB.insertAfter(Instr, SEH);
+      }
+
       emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign,
                                false);
       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
           .addReg(ARM::R4, RegState::Kill)
           .add(predOps(ARMCC::AL));
     }
 
     AFI->setShouldRestoreSPFromFP(true);
else
           .add(predOps(ARMCC::AL));
   }
 
   // If the frame has variable sized objects then the epilogue must restore
   // the sp from fp. We can assume there's an FP here since hasFP already
   // checks for hasVarSizedObjects.
   if (MFI.hasVarSizedObjects())
     AFI->setShouldRestoreSPFromFP(true);
+
+  // The very last FrameSetup instruction indicates the end of prologue. Emit a
+  // SEH opcode indicating the prologue end.
+  if (NeedsWinCFI && MBBI != MBB.begin()) {
+    insertSEHRange(MBB, {}, MBBI, TII, MachineInstr::FrameSetup);
+    BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_PrologEnd))
+        .setMIFlag(MachineInstr::FrameSetup);
+    MF.setHasWinCFI(true);
+  }
 }
 
 void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
                                     MachineBasicBlock &MBB) const {
   MachineFrameInfo &MFI = MF.getFrameInfo();
   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
   const ARMBaseInstrInfo &TII =
void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
   // prologue/epilogue.
   if (MF.getFunction().getCallingConv() == CallingConv::GHC)
     return;
 
   // First put ourselves on the first (from top) terminator instructions.
   MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
   DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
 
+  MachineBasicBlock::iterator RangeStart;
   if (!AFI->hasStackFrame()) {
+    if (MF.hasWinCFI()) {
+      BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_EpilogStart))
+          .setMIFlag(MachineInstr::FrameDestroy);
+      RangeStart = initMBBRange(MBB, MBBI);
+    }
+
     if (NumBytes + IncomingArgStackToRestore != 0)
       emitSPUpdate(isARM, MBB, MBBI, dl, TII,
                    NumBytes + IncomingArgStackToRestore,
                    MachineInstr::FrameDestroy);
   } else {
     // Unwind MBBI to point to first LDR / VLDRD.
     if (MBBI != MBB.begin()) {
       do {
         --MBBI;
       } while (MBBI != MBB.begin() &&
                MBBI->getFlag(MachineInstr::FrameDestroy));
       if (!MBBI->getFlag(MachineInstr::FrameDestroy))
         ++MBBI;
     }
 
+    if (MF.hasWinCFI()) {
+      BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_EpilogStart))
+          .setMIFlag(MachineInstr::FrameDestroy);
+      RangeStart = initMBBRange(MBB, MBBI);
+    }
+
     // Move SP to start of FP callee save spill area.
     NumBytes -= (ReservedArgStack +
                  AFI->getFPCXTSaveAreaSize() +
                  AFI->getGPRCalleeSavedArea1Size() +
                  AFI->getGPRCalleeSavedArea2Size() +
                  AFI->getDPRCalleeSavedGapSize() +
                  AFI->getDPRCalleeSavedAreaSize());
 
if (!AFI->hasStackFrame()) {
 
     // Validate PAC, It should have been already popped into R12. For CMSE entry
     // function, the validation instruction is emitted during expansion of the
     // tBXNS_RET, since the validation must use the value of SP at function
     // entry, before saving, resp. after restoring, FPCXTNS.
     if (AFI->shouldSignReturnAddress() && !AFI->isCmseNSEntryFunction())
       BuildMI(MBB, MBBI, DebugLoc(), STI.getInstrInfo()->get(ARM::t2AUT));
   }
+
+  if (MF.hasWinCFI())
+    insertSEHRange(MBB, RangeStart, MBB.end(), TII, MachineInstr::FrameDestroy);
 }
 
 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
 /// debug info.  It's the same as what we use for resolving the code-gen
 /// references for now.  FIXME: This can go wrong when references are
 /// SP-relative and simple call frames aren't used.
 StackOffset ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF,
                                                      int FI,
BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD))
         .addReg(ARM::SP)
         .add(predOps(ARMCC::AL))
         .addReg(ScratchReg0)
         .addReg(ScratchReg1);
   }
 
   // Emit the relevant DWARF information about the change in stack pointer as
   // well as where to find both r4 and r5 (the callee-save registers)
+  if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
     CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 8));
     BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
         .addCFIIndex(CFIIndex);
     CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
         nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4));
     BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
         .addCFIIndex(CFIIndex);
     CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
         nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8));
     BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
         .addCFIIndex(CFIIndex);
+  }
 
   // mov SR1, sp
   if (Thumb) {
     BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1)
         .addReg(ARM::SP)
         .add(predOps(ARMCC::AL));
   } else if (CompareStackPointer) {
     BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)
BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD))
         .addReg(ARM::SP, RegState::Define)
         .addReg(ARM::SP)
         .add(predOps(ARMCC::AL))
         .addReg(ARM::LR);
   }
 
   // Emit the DWARF info about the change in stack as well as where to find the
   // previous link register
+  if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
     CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 12));
     BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
         .addCFIIndex(CFIIndex);
     CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
         nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12));
     BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
         .addCFIIndex(CFIIndex);
+  }
 
   // Call __morestack().
   if (Thumb) {
     BuildMI(AllocMBB, DL, TII.get(ARM::tBL))
         .add(predOps(ARMCC::AL))
         .addExternalSymbol("__morestack");
   } else {
     BuildMI(AllocMBB, DL, TII.get(ARM::BL))
BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
         .addReg(ARM::SP, RegState::Define)
         .addReg(ARM::SP)
         .add(predOps(ARMCC::AL))
         .addReg(ScratchReg0)
         .addReg(ScratchReg1);
   }
 
   // Update the CFA offset now that we've popped
+  if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
     CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0));
     BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
         .addCFIIndex(CFIIndex);
+  }
 
   // Return from this function.
   BuildMI(AllocMBB, DL, TII.get(ST->getReturnOpcode())).add(predOps(ARMCC::AL));
 
   // Restore SR0 and SR1 in case of __morestack() was not called.
   // pop {SR0, SR1}
   if (Thumb) {
     BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP))
         .add(predOps(ARMCC::AL))
         .addReg(ScratchReg0)
         .addReg(ScratchReg1);
   } else {
     BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD))
         .addReg(ARM::SP, RegState::Define)
         .addReg(ARM::SP)
         .add(predOps(ARMCC::AL))
         .addReg(ScratchReg0)
         .addReg(ScratchReg1);
   }
 
   // Update the CFA offset now that we've popped
+  if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
     CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0));
     BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
         .addCFIIndex(CFIIndex);
 
     // Tell debuggers that r4 and r5 are now the same as they were in the
     // previous function, that they're the "Same Value".
     CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
         nullptr, MRI->getDwarfRegNum(ScratchReg0, true)));
     BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
         .addCFIIndex(CFIIndex);
     CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
         nullptr, MRI->getDwarfRegNum(ScratchReg1, true)));
     BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
         .addCFIIndex(CFIIndex);
+  }
 
   // Organizing MBB lists
   PostStackMBB->addSuccessor(&PrologueMBB);
 
   AllocMBB->addSuccessor(PostStackMBB);
 
   GetMBB->addSuccessor(PostStackMBB);
   GetMBB->addSuccessor(AllocMBB);

llvm/lib/Target/ARM/ARMInstrInfo.td

 
 def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary,
                                  [(atomic_fence timm:$ordering, 0)]> {
   let hasSideEffects = 1;
   let Size = 0;
   let AsmString = "@ COMPILER BARRIER";
   let hasNoSchedulingInfo = 1;
 }
+
+//===----------------------------------------------------------------------===//
+// Instructions used for emitting unwind opcodes on Windows.
+//===----------------------------------------------------------------------===//
+let isPseudo = 1 in {
+  def SEH_StackAlloc : PseudoInst<(outs), (ins i32imm:$size, i32imm:$wide), NoItinerary, []>, Sched<[]>;
+  def SEH_SaveRegs : PseudoInst<(outs), (ins i32imm:$mask, i32imm:$wide), NoItinerary, []>, Sched<[]>;
+  let isTerminator = 1 in
+  def SEH_SaveRegs_Ret : PseudoInst<(outs), (ins i32imm:$mask, i32imm:$wide), NoItinerary, []>, Sched<[]>;
+  def SEH_SetFP : PseudoInst<(outs), (ins i32imm:$reg), NoItinerary, []>, Sched<[]>;
+  def SEH_SaveFRegs : PseudoInst<(outs), (ins i32imm:$first, i32imm:$last), NoItinerary, []>, Sched<[]>;
+  let isTerminator = 1 in
+  def SEH_SaveLR : PseudoInst<(outs), (ins i32imm:$offst), NoItinerary, []>, Sched<[]>;
+  def SEH_Nop : PseudoInst<(outs), (ins i32imm:$wide), NoItinerary, []>, Sched<[]>;
+  def SEH_PrologEnd : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
+  def SEH_EpilogStart : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
+  let isTerminator = 1 in
+  def SEH_EpilogEnd : PseudoInst<(outs), (ins i32imm:$nop, i32imm:$wide), NoItinerary, []>, Sched<[]>;
+}

llvm/lib/Target/ARM/ARMSubtarget.cpp

 bool ARMSubtarget::useDFAforSMS() const { return false; }
 
 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
 bool ARMSubtarget::enablePostRAScheduler() const {
   if (enableMachineScheduler())
     return false;
   if (disablePostRAScheduler())
     return false;
+  // PostRAScheduler shuffles the SEH opcodes wrt the rest of the prologue.
+  if (TM.getMCAsmInfo() && TM.getMCAsmInfo()->usesWindowsCFI())
+    return false;
   // Thumb1 cores will generally not benefit from post-ra scheduling
   return !isThumb1Only();
 }
 
 bool ARMSubtarget::enablePostRAMachineScheduler() const {
   if (!enableMachineScheduler())
     return false;
   if (disablePostRAScheduler())

llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll

+;; Check that this produces the expected assembly output
+; RUN: llc -mtriple=thumbv7-windows -o - %s | FileCheck %s
+;; Also try to write an object file, which verifies that the SEH opcodes
+;; match the actual prologue/epilogue length.
+; RUN: llc -mtriple=thumbv7-windows -filetype=obj -o %t.obj %s
+
+; CHECK-LABEL: clobberR4Frame:
+; CHECK-NEXT: .seh_proc clobberR4Frame
+; CHECK-NEXT: @ %bb.0:                                @ %entry
+; CHECK-NEXT:         push.w  {r4, r7, r11, lr}
+; CHECK-NEXT:         .seh_save_regs_w        {r4, r7, r11, lr}
+; CHECK-NEXT:         add.w   r11, sp, #8
+; CHECK-NEXT:         .seh_nop_w
+; CHECK-NEXT:         .seh_endprologue
+; CHECK-NEXT:         bl      other
+
+; CHECK:              .seh_startepilogue
+; CHECK-NEXT:         pop.w   {r4, r7, r11, pc}
+; CHECK-NEXT:         .seh_save_regs_w        {r4, r7, r11, lr}
+; CHECK-NEXT:         .seh_endepilogue
+; CHECK-NEXT:         .seh_endproc
+
+define arm_aapcs_vfpcc void @clobberR4Frame() uwtable "frame-pointer"="all" {
+entry:
+  call arm_aapcs_vfpcc void @other()
+  call void asm sideeffect "", "~{r4}"()
+  ret void
+}
+
+; CHECK-LABEL: clobberR4NoFrame:
+; CHECK-NEXT: .seh_proc clobberR4NoFrame
+; CHECK-NEXT: @ %bb.0:                                @ %entry
+; CHECK-NEXT:         push    {r4, lr}
+; CHECK-NEXT:         .seh_save_regs  {r4, lr}
+; CHECK-NEXT:         .seh_endprologue
+; CHECK-NEXT:         bl      other
+
+; CHECK:              .seh_startepilogue
+; CHECK-NEXT:         pop     {r4, pc}
+; CHECK-NEXT:         .seh_save_regs  {r4, lr}
+; CHECK-NEXT:         .seh_endepilogue
+; CHECK-NEXT:         .seh_endproc
+
+define arm_aapcs_vfpcc void @clobberR4NoFrame() uwtable "frame-pointer"="none" {
+entry:
+  call arm_aapcs_vfpcc void @other()
+  call void asm sideeffect "", "~{r4}"()
+  ret void
+}
+
+; CHECK-LABEL: clobberR4Tail:
+; CHECK-NEXT: .seh_proc clobberR4Tail
+; CHECK-NEXT: @ %bb.0:                                @ %entry
+; CHECK-NEXT:         push    {r4, lr}
+; CHECK-NEXT:         .seh_save_regs  {r4, lr}
+; CHECK-NEXT:         .seh_endprologue
+
+; CHECK:              .seh_startepilogue
+; CHECK-NEXT:         pop.w   {r4, lr}
+; CHECK-NEXT:         .seh_save_regs_w        {r4, lr}
+; CHECK-NEXT:         b       other
+; CHECK-NEXT:         .seh_endepilogue_nop_w
+; CHECK-NEXT:         .seh_endproc
+
+define arm_aapcs_vfpcc void @clobberR4Tail() uwtable "frame-pointer"="none" {
+entry:
+  call void asm sideeffect "", "~{r4}"()
+  tail call arm_aapcs_vfpcc void @other()
+  ret void
+}
+
+; CHECK-LABEL: clobberD8D10:
+; CHECK-NEXT: .seh_proc clobberD8D10
+; CHECK-NEXT: @ %bb.0:                                @ %entry
+; CHECK-NEXT:         vpush   {d8, d9, d10}
+; CHECK-NEXT:         .seh_save_fregs {d8-d10}
+; CHECK-NEXT:         .seh_endprologue
+
+; CHECK:              .seh_startepilogue
+; CHECK-NEXT:         vpop    {d8, d9, d10}
+; CHECK-NEXT:         .seh_save_fregs {d8-d10}
+; CHECK-NEXT:         b       other
+; CHECK-NEXT:         .seh_endepilogue_nop_w
+; CHECK-NEXT:         .seh_endproc
+
+define arm_aapcs_vfpcc void @clobberD8D10() uwtable "frame-pointer"="none" {
+entry:
+  call void asm sideeffect "", "~{d8},~{d9},~{d10}"()
+  tail call arm_aapcs_vfpcc void @other()
+  ret void
+}
+
+declare arm_aapcs_vfpcc void @other()
+
+; CHECK-LABEL: vararg:
+; CHECK-NEXT: .seh_proc vararg
+; CHECK-NEXT: @ %bb.0:                                @ %entry
+; CHECK-NEXT:         sub     sp, #12
+; CHECK-NEXT:         .seh_stackalloc 12
+; CHECK-NEXT:         push.w  {r11, lr}
+; CHECK-NEXT:         .seh_save_regs_w        {r11, lr}
+; CHECK-NEXT:         sub     sp, #4
+; CHECK-NEXT:         .seh_stackalloc 4
+; CHECK-NEXT:         .seh_endprologue
+
+; CHECK:              .seh_startepilogue
+; CHECK-NEXT:         add     sp, #4
+; CHECK-NEXT:         .seh_stackalloc 4
+; CHECK-NEXT:         pop.w   {r11, lr}
+; CHECK-NEXT:         .seh_save_regs_w        {r11, lr}
+; CHECK-NEXT:         add     sp, #12
+; CHECK-NEXT:         .seh_stackalloc 12
+; CHECK-NEXT:         bx      lr
+; CHECK-NEXT:         .seh_endepilogue_nop
+; CHECK-NEXT:         .seh_endproc
+
+define arm_aapcs_vfpcc void @vararg(i32 noundef %a, ...) uwtable "frame-pointer"="none" {
+entry:
+  %ap = alloca ptr, align 4
+  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %ap)
+  call void @llvm.va_start(ptr nonnull %ap)
+  %0 = load ptr, ptr %ap
+  call arm_aapcs_vfpcc void @useva(ptr noundef %0)
+  call void @llvm.va_end(ptr nonnull %ap)
+  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %ap)
+  ret void
+}
+
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
+declare void @llvm.va_start(ptr)
+declare void @llvm.va_end(ptr)
+
+declare arm_aapcs_vfpcc void @useva(ptr noundef)
+
+; CHECK-LABEL: func50:
+; CHECK-NEXT: .seh_proc func50
+; CHECK-NEXT: @ %bb.0:                                @ %entry
+; CHECK-NEXT:         push.w  {r11, lr}
+; CHECK-NEXT:         .seh_save_regs_w        {r11, lr}
+; CHECK-NEXT:         sub     sp, #56
+; CHECK-NEXT:         .seh_stackalloc 56
+; CHECK-NEXT:         .seh_endprologue
+
+; CHECK:              .seh_startepilogue
+; CHECK-NEXT:         add     sp, #56
+; CHECK-NEXT:         .seh_stackalloc 56
+; CHECK-NEXT:         pop.w   {r11, pc}
+; CHECK-NEXT:         .seh_save_regs_w        {r11, lr}
+; CHECK-NEXT:         .seh_endepilogue
+; CHECK-NEXT:         .seh_endproc
+
+define arm_aapcs_vfpcc void @func50() {
+entry:
+  %buf = alloca [50 x i8], align 1
+  call void @llvm.lifetime.start.p0(i64 50, ptr nonnull %buf)
+  call arm_aapcs_vfpcc void @useptr(ptr noundef nonnull %buf)
+  call void @llvm.lifetime.end.p0(i64 50, ptr nonnull %buf)
+  ret void
+}
+
+; CHECK-LABEL: func4000:
+; CHECK-NEXT: .seh_proc func4000
+; CHECK-NEXT: @ %bb.0:                                @ %entry
+; CHECK-NEXT:         push.w  {r11, lr}
+; CHECK-NEXT:         .seh_save_regs_w        {r11, lr}
+; CHECK-NEXT:         sub.w   sp, sp, #4000
+; CHECK-NEXT:         .seh_stackalloc_w       4000
+; CHECK-NEXT:         .seh_endprologue
+
+; CHECK:              .seh_startepilogue
+; CHECK-NEXT:         add.w   sp, sp, #4000
+; CHECK-NEXT:         .seh_stackalloc_w       4000
+; CHECK-NEXT:         pop.w   {r11, pc}
+; CHECK-NEXT:         .seh_save_regs_w        {r11, lr}
+; CHECK-NEXT:         .seh_endepilogue
+; CHECK-NEXT:         .seh_endproc
+
+define arm_aapcs_vfpcc void @func4000() {
+entry:
+  %buf = alloca [4000 x i8], align 1
+  call void @llvm.lifetime.start.p0(i64 4000, ptr nonnull %buf)
+  call arm_aapcs_vfpcc void @useptr(ptr noundef nonnull %buf)
+  call void @llvm.lifetime.end.p0(i64 4000, ptr nonnull %buf)
+  ret void
+}
+
+; CHECK-LABEL: func5000:
+; CHECK-NEXT: .seh_proc func5000
+; CHECK-NEXT: @ %bb.0:                                @ %entry
+; CHECK-NEXT:         push    {r4, r5, r6, lr}
+; CHECK-NEXT:         .seh_save_regs  {r4-r6, lr}
+; CHECK-NEXT:         movw    r4, #1250
+; CHECK-NEXT:         .seh_nop_w
+; CHECK-NEXT:         bl      __chkstk
+; CHECK-NEXT:         .seh_nop_w
+; CHECK-NEXT:         sub.w   sp, sp, r4
+; CHECK-NEXT:         .seh_stackalloc_w       5000
+; CHECK-NEXT:         .seh_endprologue
+
+; CHECK:              .seh_startepilogue
+; CHECK-NEXT:         add.w   sp, sp, #4992
+; CHECK-NEXT:         .seh_stackalloc_w       4992
+; CHECK-NEXT:         add     sp, #8
+; CHECK-NEXT:         .seh_stackalloc 8
+; CHECK-NEXT:         pop     {r4, r5, r6, pc}
+; CHECK-NEXT:         .seh_save_regs  {r4-r6, lr}
+; CHECK-NEXT:         .seh_endepilogue
+; CHECK-NEXT:         .seh_endproc
+
+define arm_aapcs_vfpcc void @func5000() {
+entry:
+  %buf = alloca [5000 x i8], align 1
+  call void @llvm.lifetime.start.p0(i64 5000, ptr nonnull %buf)
+  call arm_aapcs_vfpcc void @useptr(ptr noundef nonnull %buf)
+  call void @llvm.lifetime.end.p0(i64 5000, ptr nonnull %buf)
+  ret void
+}
+
+; CHECK-LABEL: func262144:
+; CHECK-NEXT: .seh_proc func262144
+; CHECK-NEXT: @ %bb.0:                                @ %entry
+; CHECK-NEXT:         push    {r4, r5, r6, lr}
+; CHECK-NEXT:         .seh_save_regs  {r4-r6, lr}
+; CHECK-NEXT:         movs    r4, #0
+; CHECK-NEXT:         .seh_nop
+; CHECK-NEXT:         movt    r4, #1
+; CHECK-NEXT:         .seh_nop_w
+; CHECK-NEXT:         bl      __chkstk
+; CHECK-NEXT:         .seh_nop_w
+; CHECK-NEXT:         sub.w   sp, sp, r4
+; CHECK-NEXT:         .seh_stackalloc_w       262144
+; CHECK-NEXT:         .seh_endprologue
+
+; CHECK:              .seh_startepilogue
+; CHECK-NEXT:         add.w   sp, sp, #262144
+; CHECK-NEXT:         .seh_stackalloc_w       262144
+; CHECK-NEXT:         pop     {r4, r5, r6, pc}
+; CHECK-NEXT:         .seh_save_regs  {r4-r6, lr}
+; CHECK-NEXT:         .seh_endepilogue
+; CHECK-NEXT:         .seh_endfunclet
+; CHECK-NEXT:         .seh_endproc
+
+define arm_aapcs_vfpcc void @func262144() {
+entry:
+  %buf = alloca [262144 x i8], align 1
+  call void @llvm.lifetime.start.p0(i64 262144, ptr nonnull %buf)
+  call arm_aapcs_vfpcc void @useptr(ptr noundef nonnull %buf)
+  call void @llvm.lifetime.end.p0(i64 262144, ptr nonnull %buf)
+  ret void
+}
+
+; CHECK-LABEL: func270000:
+; CHECK-NEXT: .seh_proc func270000
+; CHECK-NEXT: @ %bb.0:                                @ %entry
+; CHECK-NEXT:         push    {r4, r5, r6, lr}
+; CHECK-NEXT:         .seh_save_regs  {r4-r6, lr}
+; CHECK-NEXT:         movw    r4, #1964
+; CHECK-NEXT:         .seh_nop_w
+; CHECK-NEXT:         movt    r4, #1
+; CHECK-NEXT:         .seh_nop_w
+; CHECK-NEXT:         bl      __chkstk
+; CHECK-NEXT:         .seh_nop_w
+; CHECK-NEXT:         sub.w   sp, sp, r4
+; CHECK-NEXT:         .seh_stackalloc_w       270000
+; CHECK-NEXT:         .seh_endprologue
+
+; CHECK:              .seh_startepilogue
+; CHECK-NEXT:         add.w   sp, sp, #268288
+; CHECK-NEXT:         .seh_stackalloc_w       268288
+; CHECK-NEXT:         add.w   sp, sp, #1712
+; CHECK-NEXT:         .seh_stackalloc_w       1712
+; CHECK-NEXT:         pop     {r4, r5, r6, pc}
+; CHECK-NEXT:         .seh_save_regs  {r4-r6, lr}
+; CHECK-NEXT:         .seh_endepilogue
+; CHECK-NEXT:         .seh_endproc
+
+define arm_aapcs_vfpcc void @func270000() {
+entry:
+  %buf = alloca [270000 x i8], align 1
+  call void @llvm.lifetime.start.p0(i64 270000, ptr nonnull %buf)
+  call arm_aapcs_vfpcc void @useptr(ptr noundef nonnull %buf)
+  call void @llvm.lifetime.end.p0(i64 270000, ptr nonnull %buf)
+  ret void
+}
+
+declare arm_aapcs_vfpcc void @useptr(ptr noundef)