[BOLT][NFC] Use BitVector::set_bits

[Amir]

Summary

Refactor and use set_bits BitVector interface.

[Amir]

Typo

[rafauler]

Thanks!

bolt/include/bolt/Passes/ReorderUtils.h

public:
 
   void initialize(std::vector<Cluster *> &_Clusters) { Clusters = _Clusters; }
 
   template <typename F> void forAllAdjacent(const Cluster *C, F Func) const {
     const_cast<AdjacencyMatrix *>(this)->forallAdjacent(C, Func);
   }
 
   template <typename F> void forAllAdjacent(const Cluster *C, F Func) {
-    for (int I = Bits[C->id()].find_first(); I != -1;
-         I = Bits[C->id()].find_next(I))
+    for (int I : Bits[C->id()].set_bits())
       Func(Clusters[I]);
   }
 
   /// Merge adjacency info from cluster B into cluster A.  Info for cluster B is
   /// left in an undefined state.
   void merge(const Cluster *A, const Cluster *B) {
     Bits[A->id()] |= Bits[B->id()];
     Bits[A->id()][A->id()] = false;
     Bits[A->id()][B->id()] = false;
     Bits[B->id()][A->id()] = false;
-    for (int I = Bits[B->id()].find_first(); I != -1;
-         I = Bits[B->id()].find_next(I)) {
+    for (int I : Bits[B->id()].set_bits()) {
       Bits[I][A->id()] = true;
       Bits[I][B->id()] = false;
     }
   }
 
   void set(const Cluster *A, const Cluster *B) { set(A, B, true); }
 
 private:

bolt/lib/Passes/DataflowAnalysis.cpp

 raw_ostream &operator<<(raw_ostream &OS, const BitVector &State) {
   LLVM_DEBUG({
     OS << "BitVector(";
     const char *Sep = "";
     if (State.count() > (State.size() >> 1)) {
       OS << "all, except: ";
       BitVector BV = State;
       BV.flip();
-      for (int I = BV.find_first(); I != -1; I = BV.find_next(I)) {
+      for (int I : BV.set_bits()) {
         OS << Sep << I;
         Sep = " ";
       }
       OS << ")";
       return OS;
     }
-    for (int I = State.find_first(); I != -1; I = State.find_next(I)) {
+    for (int I : State.set_bits()) {
       OS << Sep << I;
       Sep = " ";
     }
     OS << ")";
     return OS;
   });
   OS << "BitVector";
   return OS;
void RegStatePrinter::print(raw_ostream &OS, const BitVector &State) const {
   if (State.all()) {
     OS << "(all)";
     return;
   }
   if (State.count() > (State.size() >> 1)) {
     OS << "all, except: ";
     BitVector BV = State;
     BV.flip();
-    for (int I = BV.find_first(); I != -1; I = BV.find_next(I))
+    for (int I : BV.set_bits())
       OS << BC.MRI->getName(I) << " ";
     return;
   }
-  for (int I = State.find_first(); I != -1; I = State.find_next(I))
+  for (int I : State.set_bits())
     OS << BC.MRI->getName(I) << " ";
 }
 
 } // namespace bolt
 } // namespace llvm

bolt/lib/Passes/RegReAssign.cpp

 void RegReAssign::aggressivePassOverFunction(BinaryFunction &Function) {
   BinaryContext &BC = Function.getBinaryContext();
   rankRegisters(Function);
 
   // Bail early if our registers are all black listed, before running expensive
   // analysis passes
   bool Bail = true;
   int64_t LowScoreClassic = std::numeric_limits<int64_t>::max();
-  for (int J = ClassicRegs.find_first(); J != -1;
-       J = ClassicRegs.find_next(J)) {
+  for (int J : ClassicRegs.set_bits()) {
     if (RegScore[J] <= 0)
       continue;
     Bail = false;
     if (RegScore[J] < LowScoreClassic)
       LowScoreClassic = RegScore[J];
   }
   if (Bail)
     return;
   BitVector Extended = ClassicRegs;
   Extended.flip();
   Extended &= GPRegs;
   Bail = true;
   int64_t HighScoreExtended = 0;
-  for (int J = Extended.find_first(); J != -1; J = Extended.find_next(J)) {
+  for (int J : Extended.set_bits()) {
     if (RegScore[J] <= 0)
       continue;
     Bail = false;
     if (RegScore[J] > HighScoreExtended)
       HighScoreExtended = RegScore[J];
   }
   // Also bail early if there is no profitable substitution even if we assume
   // all registers can be exchanged

 
 bool RegReAssign::conservativePassOverFunction(BinaryFunction &Function) {
   BinaryContext &BC = Function.getBinaryContext();
   rankRegisters(Function);
 
   // Try swapping R12, R13, R14 or R15 with RBX (we work with all callee-saved
   // regs except RBP)
   MCPhysReg Candidate = 0;
-  for (int J = ExtendedCSR.find_first(); J != -1;
-       J = ExtendedCSR.find_next(J))
+  for (int J : ExtendedCSR.set_bits())
     if (RegScore[J] > RegScore[Candidate])
       Candidate = J;
 
   if (!Candidate || RegScore[Candidate] < 0)
     return false;
 
   // Check if our classic callee-saved reg (RBX is the only one) has lower
   // score / utilization rate
   MCPhysReg RBX = 0;
-  for (int I = ClassicCSR.find_first(); I != -1; I = ClassicCSR.find_next(I)) {
+  for (int I : ClassicCSR.set_bits()) {
     int64_t ScoreRBX = RegScore[I];
     if (ScoreRBX <= 0)
       continue;
 
     if (RegScore[Candidate] > (ScoreRBX + 10))
       RBX = I;
   }
 

bolt/lib/Passes/ShrinkWrapping.cpp

void ShrinkWrapping::classifyCSRUses() {
   const BitVector &FPAliases = BC.MIB->getAliases(BC.MIB->getFramePointer());
   for (BinaryBasicBlock &BB : BF) {
     for (MCInst &Inst : BB) {
       if (BC.MIB->isCFI(Inst))
         continue;
       BitVector BV = BitVector(BC.MRI->getNumRegs(), false);
       BC.MIB->getTouchedRegs(Inst, BV);
       BV &= CSA.CalleeSaved;
-      for (int I = BV.find_first(); I != -1; I = BV.find_next(I)) {
+      for (int I : BV.set_bits()) {
         if (I == 0)
           continue;
         if (CSA.getSavedReg(Inst) != I && CSA.getRestoredReg(Inst) != I)
           UsesByReg[I].set(DA.ExprToIdx[&Inst]);
       }
       if (!SPT.HasFramePointer || !BC.MIB->isCall(Inst))
         continue;
       BV = CSA.CalleeSaved;
       BV &= FPAliases;
-      for (int I = BV.find_first(); I > 0; I = BV.find_next(I))
+      for (int I : BV.set_bits())
         UsesByReg[I].set(DA.ExprToIdx[&Inst]);
     }
   }
 }
 
 void ShrinkWrapping::pruneUnwantedCSRs() {
   BitVector ParamRegs = BC.MIB->getRegsUsedAsParams();
   for (unsigned I = 0, E = BC.MRI->getNumRegs(); I != E; ++I) {
if ((SPFP.first == SPT.SUPERPOSITION || SPFP.first == SPT.EMPTY) &&
         (SPFP.second == SPT.SUPERPOSITION || SPFP.second == SPT.EMPTY))
       continue;
 
     for (unsigned I = 0, E = BC.MRI->getNumRegs(); I != E; ++I) {
       if (!CSA.CalleeSaved[I])
         continue;
 
       BitVector BBDominatedUses = BitVector(DA.NumInstrs, false);
-      for (int J = UsesByReg[I].find_first(); J > 0;
-           J = UsesByReg[I].find_next(J))
+      for (int J : UsesByReg[I].set_bits())
         if (DA.doesADominateB(*First, J))
           BBDominatedUses.set(J);
       LLVM_DEBUG(dbgs() << "\t\tBB " << BB.getName() << " dominates "
                         << BBDominatedUses.count() << " uses for reg " << I
                         << ". Total uses for reg is " << UsesByReg[I].count()
                         << "\n");
       BBDominatedUses &= UsesByReg[I];
       if (BBDominatedUses == UsesByReg[I]) {
         LLVM_DEBUG(dbgs() << "\t\t\tAdded " << BB.getName()
                           << " as a save pos for " << I << "\n");
         SavePos[I].insert(First);
         LLVM_DEBUG({
           dbgs() << "Dominated uses are:\n";
-          for (int J = UsesByReg[I].find_first(); J > 0;
-               J = UsesByReg[I].find_next(J)) {
+          for (int J : UsesByReg[I].set_bits()) {
             dbgs() << "Idx " << J << ": ";
             DA.Expressions[J]->dump();
           }
         });
       }
     }
   }
 

bolt/lib/Passes/StokeInfo.cpp

StokeOutputDataFilename("stoke-out",
   cl::cat(StokeOptCategory));
 }
 
 namespace llvm {
 namespace bolt {
 
 void getRegNameFromBitVec(const BinaryContext &BC, const BitVector &RegV,
                           std::set<std::string> *NameVec = nullptr) {
-  int RegIdx = RegV.find_first();
-  while (RegIdx != -1) {
+  for (int RegIdx : RegV.set_bits()) {
     LLVM_DEBUG(dbgs() << BC.MRI->getName(RegIdx) << " ");
     if (NameVec)
       NameVec->insert(std::string(BC.MRI->getName(RegIdx)));
-    RegIdx = RegV.find_next(RegIdx);
   }
   LLVM_DEBUG(dbgs() << "\n");
 }
 
 void StokeInfo::checkInstr(const BinaryFunction &BF, StokeFuncInfo &FuncInfo) {
   MCPlusBuilder *MIB = BF.getBinaryContext().MIB.get();
   BitVector RegV(NumRegs, false);
   for (BinaryBasicBlock *BB : BF.layout()) {

bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp

for (auto II = Begin; II != End; ++II) {
       LLVM_DEBUG(dbgs() << "Now updating for:\n ");
       LLVM_DEBUG(Instr.dump());
       addInstrOperands(Instr);
 
       BitVector Regs = BitVector(RegInfo->getNumRegs(), false);
       getWrittenRegs(Instr, Regs);
 
       // Update register definitions after this point
-      int Idx = Regs.find_first();
-      while (Idx != -1) {
+      for (int Idx : Regs.set_bits()) {
         RegAliasTable[Idx] = &Instr;
         LLVM_DEBUG(dbgs() << "Setting reg " << Idx
                           << " def to current instr.\n");
-        Idx = Regs.find_next(Idx);
       }
 
       TerminatorSeen = isTerminator(Instr);
     }
 
     // Process the last instruction, which is not currently added into the
     // instruction stream
     if (CurInstr)