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Differential D125173

[AMDGPU] lowerEXTRACT_VECTOR_ELT - fold from a SCALAR_TO_VECTOR source
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Authored by RKSimon on May 7 2022, 10:19 AM.

Details

Reviewers
foad
arsenm
Commits
rG7e3ef7dcd2b8: [AMDGPU] lowerEXTRACT_VECTOR_ELT - fold from a SCALAR_TO_VECTOR source
Summary

As suggested by @foad on D124839

If we're extracting a vector element that originally came from a scalar_to_vector, then avoid the bitcasting of a vector type and perform the shift masking on the (any-extended) scalar source directly, making use of the fact that the upper elements of a scalar_to_vector are all undef.

Diff Detail

Event Timeline

RKSimon created this revision.May 7 2022, 10:19 AM
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RKSimon requested review of this revision.May 7 2022, 10:19 AM
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arsenm accepted this revision.May 7 2022, 10:39 AM
This revision is now accepted and ready to land.May 7 2022, 10:39 AM
Harbormaster completed remote builds in B163330: Diff 427876.May 7 2022, 10:43 AM
This revision was landed with ongoing or failed builds.May 7 2022, 12:24 PM
Closed by commit rG7e3ef7dcd2b8: [AMDGPU] lowerEXTRACT_VECTOR_ELT - fold from a SCALAR_TO_VECTOR source (authored by RKSimon). · Explain Why
This revision was automatically updated to reflect the committed changes.
RKSimon added a commit: rG7e3ef7dcd2b8: [AMDGPU] lowerEXTRACT_VECTOR_ELT - fold from a SCALAR_TO_VECTOR source.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
11 lines
test/
CodeGen/
AMDGPU/
27 lines
55 lines

Diff 427888

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,876 Lines • ▼ Show 20 Lines if (VecSize == 128) {
SDValue IdxMask = DAG.getConstant(NElem / 2 - 1, SL, IdxVT); SDValue IdxMask = DAG.getConstant(NElem / 2 - 1, SL, IdxVT);
SDValue NewIdx = DAG.getNode(ISD::AND, SL, IdxVT, Idx, IdxMask); SDValue NewIdx = DAG.getNode(ISD::AND, SL, IdxVT, Idx, IdxMask);
SDValue Half = DAG.getSelectCC(SL, Idx, IdxMask, Hi, Lo, ISD::SETUGT); SDValue Half = DAG.getSelectCC(SL, Idx, IdxMask, Hi, Lo, ISD::SETUGT);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Half, NewIdx); return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Half, NewIdx);
} }
assert(VecSize <= 64); assert(VecSize <= 64);
MVT IntVT = MVT::getIntegerVT(VecSize);
// If Vec is just a SCALAR_TO_VECTOR, then use the scalar integer directly.
SDValue VecBC = peekThroughBitcasts(Vec);
if (VecBC.getOpcode() == ISD::SCALAR_TO_VECTOR) {
SDValue Src = VecBC.getOperand(0);
Src = DAG.getBitcast(Src.getValueType().changeTypeToInteger(), Src);
Vec = DAG.getAnyExtOrTrunc(Src, SL, IntVT);
}
unsigned EltSize = EltVT.getSizeInBits(); unsigned EltSize = EltVT.getSizeInBits();
assert(isPowerOf2_32(EltSize)); assert(isPowerOf2_32(EltSize));
MVT IntVT = MVT::getIntegerVT(VecSize);
SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32); SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32);
// Convert vector index to bit-index (* EltSize) // Convert vector index to bit-index (* EltSize)
SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor); SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
SDValue BC = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec); SDValue BC = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
SDValue Elt = DAG.getNode(ISD::SRL, SL, IntVT, BC, ScaledIdx); SDValue Elt = DAG.getNode(ISD::SRL, SL, IntVT, BC, ScaledIdx);
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llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll

Show First 20 Lines • Show All 168 Lines • ▼ Show 20 Lines
; ;
; VI-LABEL: s_insertelement_v2i16_0_reghi: ; VI-LABEL: s_insertelement_v2i16_0_reghi:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: s_load_dword s4, s[4:5], 0x30 ; VI-NEXT: s_load_dword s4, s[4:5], 0x30
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dword s2, s[2:3], 0x0 ; VI-NEXT: s_load_dword s2, s[2:3], 0x0
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_lshr_b32 s0, s4, 16
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_and_b32 s1, s2, 0xffff0000 ; VI-NEXT: s_lshr_b32 s0, s2, 16
; VI-NEXT: s_or_b32 s0, s0, s1 ; VI-NEXT: v_alignbit_b32 v2, s0, v2, 16
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: s_insertelement_v2i16_0_reghi: ; CI-LABEL: s_insertelement_v2i16_0_reghi:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: s_load_dword s4, s[4:5], 0xc ; CI-NEXT: s_load_dword s4, s[4:5], 0xc
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
Show All 34 Lines
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1: ; VI-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: s_load_dword s4, s[4:5], 0x10 ; VI-NEXT: s_load_dword s4, s[4:5], 0x10
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dword s2, s[2:3], 0x0 ; VI-NEXT: s_load_dword s2, s[2:3], 0x0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_lshr_b32 s0, s4, 16 ; VI-NEXT: s_lshr_b32 s0, s4, 16
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_and_b32 s1, s2, 0xffff0000 ; VI-NEXT: s_lshr_b32 s1, s2, 16
; VI-NEXT: s_or_b32 s1, s0, s1 ; VI-NEXT: v_alignbit_b32 v2, s1, v2, 16
; VI-NEXT: v_mov_b32_e32 v2, s1
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: ;;#ASMSTART ; VI-NEXT: ;;#ASMSTART
; VI-NEXT: ; use s0 ; VI-NEXT: ; use s0
; VI-NEXT: ;;#ASMEND ; VI-NEXT: ;;#ASMEND
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1: ; CI-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1:
; CI: ; %bb.0: ; CI: ; %bb.0:
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; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: s_insertelement_v2i16_0_reghi_both_multi_use_1: ; VI-LABEL: s_insertelement_v2i16_0_reghi_both_multi_use_1:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: s_load_dword s4, s[4:5], 0x10 ; VI-NEXT: s_load_dword s4, s[4:5], 0x10
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dword s2, s[2:3], 0x0 ; VI-NEXT: s_load_dword s2, s[2:3], 0x0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_lshr_b32 s0, s4, 16 ; VI-NEXT: s_lshr_b32 s0, s4, 16
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshr_b32 s1, s2, 16 ; VI-NEXT: s_lshr_b32 s1, s2, 16
; VI-NEXT: s_and_b32 s2, s2, 0xffff0000 ; VI-NEXT: v_alignbit_b32 v2, s1, v2, 16
; VI-NEXT: s_or_b32 s2, s0, s2
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: ;;#ASMSTART ; VI-NEXT: ;;#ASMSTART
; VI-NEXT: ; use s0 ; VI-NEXT: ; use s0
; VI-NEXT: ;;#ASMEND ; VI-NEXT: ;;#ASMEND
; VI-NEXT: ;;#ASMSTART ; VI-NEXT: ;;#ASMSTART
; VI-NEXT: ; use s1 ; VI-NEXT: ; use s1
; VI-NEXT: ;;#ASMEND ; VI-NEXT: ;;#ASMEND
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
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; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v3, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1]
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: s_lshr_b32 s0, s4, 16
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v3
; VI-NEXT: v_or_b32_e32 v2, s0, v2 ; VI-NEXT: v_alignbit_b32 v2, v2, s4, 16
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: v_insertelement_v2i16_0_reghi: ; CI-LABEL: v_insertelement_v2i16_0_reghi:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: s_load_dword s4, s[4:5], 0x4 ; CI-NEXT: s_load_dword s4, s[4:5], 0x4
; CI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
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llvm/test/CodeGen/AMDGPU/load-lo16.ll

Show First 20 Lines • Show All 278 Lines • ▼ Show 20 Lines
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_local_lo_v2i16_reghi_vreg_zexti8: ; GFX803-LABEL: load_local_lo_v2i16_reghi_vreg_zexti8:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: s_mov_b32 m0, -1 ; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u8 v0, v0 ; GFX803-NEXT: ds_read_u8 v0, v0
; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
; GFX803-NEXT: s_waitcnt lgkmcnt(0) ; GFX803-NEXT: s_waitcnt lgkmcnt(0)
; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4 ; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%load = load i8, i8 addrspace(3)* %in %load = load i8, i8 addrspace(3)* %in
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
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; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_global_lo_v2i16_reglo_vreg_zexti8: ; GFX803-LABEL: load_global_lo_v2i16_reglo_vreg_zexti8:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff001, v0 ; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff001, v0
; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc ; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
; GFX803-NEXT: flat_load_ubyte v0, v[0:1] ; GFX803-NEXT: flat_load_ubyte v0, v[0:1]
; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v2 ; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4 ; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%gep = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 -4095 %gep = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 -4095
%load = load i8, i8 addrspace(1)* %gep %load = load i8, i8 addrspace(1)* %gep
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
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; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_global_lo_v2f16_reglo_vreg_zexti8: ; GFX803-LABEL: load_global_lo_v2f16_reglo_vreg_zexti8:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff001, v0 ; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff001, v0
; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc ; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
; GFX803-NEXT: flat_load_ubyte v0, v[0:1] ; GFX803-NEXT: flat_load_ubyte v0, v[0:1]
; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v2 ; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4 ; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x half> %reg.bc = bitcast i32 %reg to <2 x half>
%gep = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 -4095 %gep = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 -4095
%load = load i8, i8 addrspace(1)* %gep %load = load i8, i8 addrspace(1)* %gep
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
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; GFX906-NEXT: global_store_dword v[0:1], v0, off ; GFX906-NEXT: global_store_dword v[0:1], v0, off
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_flat_lo_v2i16_reglo_vreg_zexti8: ; GFX803-LABEL: load_flat_lo_v2i16_reglo_vreg_zexti8:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: flat_load_ubyte v0, v[0:1] ; GFX803-NEXT: flat_load_ubyte v0, v[0:1]
; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v2 ; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4 ; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%load = load i8, i8* %in %load = load i8, i8* %in
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
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; GFX906-NEXT: global_store_dword v[0:1], v0, off ; GFX906-NEXT: global_store_dword v[0:1], v0, off
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_flat_lo_v2f16_reglo_vreg_zexti8: ; GFX803-LABEL: load_flat_lo_v2f16_reglo_vreg_zexti8:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: flat_load_ubyte v0, v[0:1] ; GFX803-NEXT: flat_load_ubyte v0, v[0:1]
; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v2 ; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4 ; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x half> %reg.bc = bitcast i32 %reg to <2 x half>
%load = load i8, i8* %in %load = load i8, i8* %in
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%bitcast = bitcast i16 %ext to half %bitcast = bitcast i16 %ext to half
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; GFX906-NEXT: global_store_dword v[0:1], v0, off ; GFX906-NEXT: global_store_dword v[0:1], v0, off
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8: ; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:4095 ; GFX803-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:4095
; GFX803-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX803-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4 ; GFX803-NEXT: v_or_b32_e32 v0, v1, v0
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8: ; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8:
; GFX900-FLATSCR: ; %bb.0: ; %entry ; GFX900-FLATSCR: ; %bb.0: ; %entry
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-FLATSCR-NEXT: scratch_load_ubyte_d16 v0, off, s32 offset:4095 ; GFX900-FLATSCR-NEXT: scratch_load_ubyte_d16 v0, off, s32 offset:4095
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; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_zexti8: ; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_zexti8:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:4094 glc ; GFX803-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:4094 glc
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00 ; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_zexti8: ; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_zexti8:
; GFX900-FLATSCR: ; %bb.0: ; %entry ; GFX900-FLATSCR: ; %bb.0: ; %entry
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-FLATSCR-NEXT: s_movk_i32 s0, 0xffe ; GFX900-FLATSCR-NEXT: s_movk_i32 s0, 0xffe
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; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_private_lo_v2f16_reglo_vreg_nooff_zexti8: ; GFX803-LABEL: load_private_lo_v2f16_reglo_vreg_nooff_zexti8:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:4094 glc ; GFX803-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:4094 glc
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00 ; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-FLATSCR-LABEL: load_private_lo_v2f16_reglo_vreg_nooff_zexti8: ; GFX900-FLATSCR-LABEL: load_private_lo_v2f16_reglo_vreg_nooff_zexti8:
; GFX900-FLATSCR: ; %bb.0: ; %entry ; GFX900-FLATSCR: ; %bb.0: ; %entry
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-FLATSCR-NEXT: s_movk_i32 s0, 0xffe ; GFX900-FLATSCR-NEXT: s_movk_i32 s0, 0xffe
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; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_constant_lo_v2f16_reglo_vreg_zexti8: ; GFX803-LABEL: load_constant_lo_v2f16_reglo_vreg_zexti8:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff001, v0 ; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff001, v0
; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc ; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
; GFX803-NEXT: flat_load_ubyte v0, v[0:1] ; GFX803-NEXT: flat_load_ubyte v0, v[0:1]
; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v2 ; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4 ; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x half> %reg.bc = bitcast i32 %reg to <2 x half>
%gep = getelementptr inbounds i8, i8 addrspace(4)* %in, i64 -4095 %gep = getelementptr inbounds i8, i8 addrspace(4)* %in, i64 -4095
%load = load i8, i8 addrspace(4)* %gep %load = load i8, i8 addrspace(4)* %gep
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
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; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_mov_b32_e32 v2, 44 ; GFX803-NEXT: v_mov_b32_e32 v2, 44
; GFX803-NEXT: buffer_load_ubyte v1, v2, s[0:3], s32 offen offset:4055 glc ; GFX803-NEXT: buffer_load_ubyte v1, v2, s[0:3], s32 offen offset:4055 glc
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX803-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00 ; GFX803-NEXT: v_or_b32_e32 v0, v1, v0
; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8_to_offset: ; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8_to_offset:
; GFX900-FLATSCR: ; %bb.0: ; %entry ; GFX900-FLATSCR: ; %bb.0: ; %entry
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-FLATSCR-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX900-FLATSCR-NEXT: v_mov_b32_e32 v1, 0x7b
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; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_mov_b32_e32 v2, 44 ; GFX803-NEXT: v_mov_b32_e32 v2, 44
; GFX803-NEXT: buffer_load_ubyte v1, v2, s[0:3], s32 offen offset:4055 glc ; GFX803-NEXT: buffer_load_ubyte v1, v2, s[0:3], s32 offen offset:4055 glc
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX803-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00 ; GFX803-NEXT: v_or_b32_e32 v0, v1, v0
; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-FLATSCR-LABEL: load_private_lo_v2f16_reglo_vreg_zexti8_to_offset: ; GFX900-FLATSCR-LABEL: load_private_lo_v2f16_reglo_vreg_zexti8_to_offset:
; GFX900-FLATSCR: ; %bb.0: ; %entry ; GFX900-FLATSCR: ; %bb.0: ; %entry
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-FLATSCR-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX900-FLATSCR-NEXT: v_mov_b32_e32 v1, 0x7b
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