Fix zero-width bitfield extracts to emit 0

[jroelofs]

Summary

Fixes #55129

[paquette]

LGTM

[jroelofs]

e1c808b36e2ec7050016c2eaafab3e17696583a0

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

                         m_OneNonDBGUse(m_GAnd(m_Reg(AndSrc), m_ICst(SMask))),
                         m_ICst(ShrAmt))))
     return false;
 
   const unsigned Size = Ty.getScalarSizeInBits();
   if (ShrAmt < 0 || ShrAmt >= Size)
     return false;
 
+  // If the shift subsumes the mask, emit the 0 directly.
+  if (0 == (SMask >> ShrAmt)) {
+    MatchInfo = [=](MachineIRBuilder &B) {
+      B.buildConstant(Dst, 0);
+    };
+    return true;
+  }
+
   // Check that ubfx can do the extraction, with no holes in the mask.
   uint64_t UMask = SMask;
   UMask |= maskTrailingOnes<uint64_t>(ShrAmt);
   UMask &= maskTrailingOnes<uint64_t>(Size);
   if (!isMask_64(UMask))
     return false;
 
   // Calculate start position and width of the extract.

llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-shr-and.mir

bb.0.entry:
     ; CHECK-NEXT: $w0 = COPY [[LSHR]](s32)
     %0:_(s32) = COPY $w0
     %1:_(s32) = G_CONSTANT i32 25
     %2:_(s32) = G_CONSTANT i32 2
     %3:_(s32) = G_AND %0, %1
     %4:_(s32) = G_LSHR %3, %2
     $w0 = COPY %4(s32)
 ...
+---
+name:          zero_from_large_shift
+legalized: true
+body:              |
+  bb.1.entry:
+    ; CHECK-LABEL: name: zero_from_large_shift
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: $x0 = COPY [[C]](s64)
+    %2:_(s32) = COPY $w0
+    %1:_(s8) = G_TRUNC %2:_(s32)
+    %3:_(s8) = G_ASSERT_ZEXT %1:_, 1
+    %5:_(s64) = G_CONSTANT i64 1
+    %7:_(s64) = G_ANYEXT %3:_(s8)
+    %4:_(s64) = G_AND %7:_, %5:_
+    %6:_(s64) = G_LSHR %4:_, %5:_(s64)
+    $x0 = COPY %6:_(s64)
+...