[HWAsan] Support 4K/8K/16K/64K page size to ring buffer

[XiaodongLoong]

Summary

The ring buffer size is a multiple of system page size, and now the page size can only be 4K.
It can not work well on other system that has different page size configure.

Depends on D123908

[eugenis]

Generally, there is no way to tell the target page size in advance. And there is no need for that, too - just untie this value from the page size instead, and fix the munmap issue in the runtime library by up/down aligning the bounds to the runtime page size. You can also increase the default / minimal ring buffer size at runtime to be a multiple of the page size.

[XiaodongLoong]

upate revision for refactor

[XiaodongLoong]

In D123910#3457079, @eugenis wrote:

Generally, there is no way to tell the target page size in advance. And there is no need for that, too - just untie this value from the page size instead, and fix the munmap issue in the runtime library by up/down aligning the bounds to the runtime page size. You can also increase the default / minimal ring buffer size at runtime to be a multiple of the page size.

Sorry, my expression may not be accurate at first. I want to support more kind of page size for HWAsan. I add a command option to custom page size in D123908.
I think the runtime can know the real page size by sysconf syscall adaptively.

Thanks!

[eugenis]

I still think that my proposal in the comment above is way better than adding an ABI-breaking compiler flag.

[XiaodongLoong]

In D123910#3462916, @eugenis wrote:

I still think that my proposal in the comment above is way better than adding an ABI-breaking compiler flag.

OK, I read the proposal https://github.com/google/sanitizers/issues/1446.

Using pagesize here would be wasteful - ex. on Android we default to a
single 4Kb page for the stack ring buffer. I'd rather replace the mmap in
SavedStackAllocations with InternalAlloc , this should solve the problem.

There is also an efficiency issue in HwasanThreadList::DontNeedThread - if
the buffer is smaller than a page, it will never be able to release
anything. That's a bit harder to fix, and I'm not sure how significant it
actually is.

I'm looking forward to your revision.

Thanks!

[eugenis]

Sorry, I did not mean that I was going to implement it.

[XiaodongLoong]

In D123910#3465774, @eugenis wrote:

Sorry, I did not mean that I was going to implement it.

OK, I'll try to implement it as you said.

llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp

 const char kHwasanModuleCtorName[] = "hwasan.module_ctor";
 const char kHwasanNoteName[] = "hwasan.note";
 const char kHwasanInitName[] = "__hwasan_init";
 const char kHwasanPersonalityThunkName[] = "__hwasan_personality_thunk";
 
 const char kHwasanShadowMemoryDynamicAddress[] =
     "__hwasan_shadow_memory_dynamic_address";
 
+#ifdef SYS_PAGE_SIZE_4K
+static const uint64_t kPageSizeBits = 12;
+#endif
+#ifdef SYS_PAGE_SIZE_8K
+static const uint64_t kPageSizeBits = 13;
+#endif
+#ifdef SYS_PAGE_SIZE_16K
+static const uint64_t kPageSizeBits = 14;
+#endif
+#ifdef SYS_PAGE_SIZE_64K
+static const uint64_t kPageSizeBits = 16;
+#endif
+
 // Accesses sizes are powers of two: 1, 2, 4, 8, 16.
 static const size_t kNumberOfAccessSizes = 5;
 
 static const size_t kDefaultShadowScale = 4;
 static const uint64_t kDynamicShadowSentinel =
     std::numeric_limits<uint64_t>::max();
 
 static const unsigned kShadowBaseAlignment = 32;
if (WithFrameRecord) {
     // Update the ring buffer. Top byte of ThreadLong defines the size of the
     // buffer in pages, it must be a power of two, and the start of the buffer
     // must be aligned by twice that much. Therefore wrap around of the ring
     // buffer is simply Addr &= ~((ThreadLong >> 56) << 12).
     // The use of AShr instead of LShr is due to
     //   https://bugs.llvm.org/show_bug.cgi?id=39030
     // Runtime library makes sure not to use the highest bit.
     Value *WrapMask = IRB.CreateXor(
-        IRB.CreateShl(IRB.CreateAShr(ThreadLong, 56), 12, "", true, true),
+        IRB.CreateShl(IRB.CreateAShr(ThreadLong, 56), kPageSizeBits, "", true, true),
         ConstantInt::get(IntptrTy, (uint64_t)-1));
     Value *ThreadLongNew = IRB.CreateAnd(
         IRB.CreateAdd(ThreadLong, ConstantInt::get(IntptrTy, 8)), WrapMask);
     IRB.CreateStore(ThreadLongNew, SlotPtr);
   }
 
   if (!ShadowBase) {
     // Get shadow base address by aligning RecordPtr up.