[BPF] Enable IAS in backend

[yonghong-song]

The UseIntegratedAssembler = false is added with the following commit,

commit d2e5157c1f0b1953c5166c1d656ac71e840615a4
Author: Fangrui Song <[e-mail]>
Date:   Sat Apr 11 10:01:36 2020 -0700

    [MC] Add UseIntegratedAssembler = false. NFC

Do you know what changed to remove UseIntegratedAssembler = false;? Does this change has any real impact on BPF backend?

[brad]

In D123845#3458214, @yonghong-song wrote:

The UseIntegratedAssembler = false is added with the following commit,

commit d2e5157c1f0b1953c5166c1d656ac71e840615a4
Author: Fangrui Song <[e-mail]>
Date:   Sat Apr 11 10:01:36 2020 -0700

    [MC] Add UseIntegratedAssembler = false. NFC

Do you know what changed to remove UseIntegratedAssembler = false;? Does this change has any real impact on BPF backend?

That commit was to offset this commit after that, since IAS was not already enabled in the backend..

commit 0a55d3f557a74cfb459b24e442072302d5444baf
Author: Fangrui Song <[e-mail]>
Date:   Sat Apr 11 10:06:18 2020 -0700

    [MC] Default MCAsmInfo::UseIntegratedAssembler to true

Well nothing changed. As far as I can see IAS for BPF has been enabled for a long time with the Clang frontend. It should be enabled in the BPF backend as well. Almost all
other backends do as well.

[yonghong-song]

The BPF doesn't really recommend to compile from the assembly code to the object code, so we should be fine here. But there is a test failure test/CodeGen/BPF/inline_asm.ll. Could you take a look?

[brad]

Fix test.

llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h

explicit BPFMCAsmInfo(const Triple &TT, const MCTargetOptions &Options) {
     MinInstAlignment = 8;
 
     // the default is 4 and it only affects dwarf elf output
     // so if not set correctly, the dwarf data will be
     // messed up in random places by 4 bytes. .debug_line
     // section will be parsable, but with odd offsets and
     // line numbers, etc.
     CodePointerSize = 8;
-
-    UseIntegratedAssembler = false;
   }
 
   void setDwarfUsesRelocationsAcrossSections(bool enable) {
     DwarfUsesRelocationsAcrossSections = enable;
   }
 };
 }
 
 #endif

llvm/test/CodeGen/BPF/inline_asm.ll

 ; CHECK: r0 = *(u16 *)skb[2]
   tail call void asm sideeffect "r0 = *(u16 *)skb[$0]", "r"(i32 4) #2
 ; CHECK: r0 = *(u16 *)skb[r1]
   %1 = tail call i32 asm sideeffect "$0 = $1", "=r,i"(i32 4) #2
 ; CHECK: r1 = 4
   %2 = tail call i32 asm sideeffect "$0 = $1 ll", "=r,i"(i64 333333333333) #2
 ; CHECK: r1 = 333333333333 ll
   %3 = call i32 asm sideeffect "$0 = *(u16 *) $1", "=r,*m"(i32* elementtype(i32) nonnull %a) #2
-; CHECK: r1 = *(u16 *) (r10 - 4)
+; CHECK: r1 = *(u16 *)(r10 - 4)
   %4 = call i32 asm sideeffect "$0 = *(u32 *) $1", "=r,*m"(i32* elementtype(i32) getelementptr inbounds ([2 x i32], [2 x i32]* @g, i64 0, i64 1)) #2
 ; CHECK: r1 = g ll
-; CHECK: r0 = *(u32 *) (r1 + 4)
+; CHECK: r0 = *(u32 *)(r1 + 4)
   call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0) #2
   ret i32 %4
 }
 
 ; Function Attrs: argmemonly nounwind
 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
 
 ; Function Attrs: argmemonly nounwind
 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
 
 attributes #0 = { nounwind }
 attributes #1 = { argmemonly nounwind }
 attributes #2 = { nounwind }