[LoongArch] Add support for selecting constant materializations.

[wangleiat]

Summary

Integer materializing can generate LU12I_W, ORI, LU32I_D, LU52I_D and
ADDI_W instructions.

According to the sign-extended behavior of these instructions
(except ORI), the generated instruction sequence can be improved.

For example, load -1 into general register:
The ADDI_W instruction performs the operation that the [31:0] bit data
in the general register rj plus the 12-bit immediate simm12 sign
extension 32-bit data; the resultant [31:0] bit is sign extension, then
written into the general register rd.

Normal sequence:

lu12i.w $a0, -1
ori $a0, $a0, 2048

Improved with sign-extended instruction:

addi.w $a0, $zero,  -1

Change-Id: Ifd72aa1cc21f4032243d7c2ba0171767b58910eb

[MaskRay]

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMatInt.cpp

24

Add const if applicable

45

The logic looks weird. What does it do?

[wangleiat]

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMatInt.cpp

24

Thanks, I will add it.

45

It is to check whether Higher20 is equal to the repetition of the 31st bit.
This judgment is made because these LU12I_W ADDI_W instructions will writes imm into the general register after sign extension.

[wangleiat]

Add const modifiers.

[SixWeining]

LGTM

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp

15

abc

foreach ($list as $item) {
  work_miracles($item);
}

[SixWeining]

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp

15

Sorry for the mess which is not my intention.

[wangleiat]

ping @MaskRay

[MaskRay]

Is it necessary to have the 4483 line test? To cover all the code paths in the function, it is possible to use significantly fewer tests.

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMatInt.h

29

Add one blank line before the header guard #endif

[wangleiat]

Reduce the test cases and simply cover all the code paths in generateInstSeq

[wangleiat]

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMatInt.h

29

Ok, thanks.

[MaskRay]

Thanks!

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp

 //=- LoongArchISelDAGToDAG.cpp - A dag to dag inst selector for LoongArch -===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines an instruction selector for the LoongArch target.
 //
 //===----------------------------------------------------------------------===//
 
 #include "LoongArchISelDAGToDAG.h"
 #include "MCTargetDesc/LoongArchMCTargetDesc.h"
+#include "MCTargetDesc/LoongArchMatInt.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "loongarch-isel"
 
 void LoongArchDAGToDAGISel::Select(SDNode *Node) {
   // If we have a custom node, we have already selected.
   if (Node->isMachineOpcode()) {
     LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");
     Node->setNodeId(-1);
     return;
   }
 
   // Instruction Selection not handled by the auto-generated tablegen selection
   // should be handled here.
   unsigned Opcode = Node->getOpcode();
+  MVT GRLenVT = Subtarget->getGRLenVT();
   SDLoc DL(Node);
 
   switch (Opcode) {
   default:
     break;
+  case ISD::Constant: {
+    int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+    SDNode *Result = nullptr;
+    SDValue SrcReg = CurDAG->getRegister(LoongArch::R0, GRLenVT);
+
+    // The instructions in the sequence are handled here.
+    for (LoongArchMatInt::Inst &Inst : LoongArchMatInt::generateInstSeq(Imm)) {
+      SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, GRLenVT);
+      if (Inst.Opc == LoongArch::LU12I_W)
+        Result = CurDAG->getMachineNode(LoongArch::LU12I_W, DL, GRLenVT, SDImm);
+      else
+        Result = CurDAG->getMachineNode(Inst.Opc, DL, GRLenVT, SrcReg, SDImm);
+      SrcReg = SDValue(Result, 0);
+    }
+
+    ReplaceNode(Node, Result);
+    return;
+  }
     // TODO: Add selection nodes needed later.
   }
 
   // Select the default instruction.
   SelectCode(Node);
 }
 // This pass converts a legalized DAG into a LoongArch-specific DAG, ready
 // for instruction scheduling.
 FunctionPass *llvm::createLoongArchISelDag(LoongArchTargetMachine &TM) {
   return new LoongArchDAGToDAGISel(TM);
 }

llvm/lib/Target/LoongArch/MCTargetDesc/CMakeLists.txt

 add_llvm_component_library(LLVMLoongArchDesc
   LoongArchAsmBackend.cpp
   LoongArchBaseInfo.cpp
   LoongArchELFObjectWriter.cpp
   LoongArchInstPrinter.cpp
   LoongArchMCAsmInfo.cpp
   LoongArchMCTargetDesc.cpp
   LoongArchMCCodeEmitter.cpp
+  LoongArchMatInt.cpp
 
   LINK_COMPONENTS
   MC
   LoongArchInfo
   Support
 
   ADD_TO_COMPONENT
   LoongArch
   )

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMatInt.h

+//===- LoongArchMatInt.h - Immediate materialisation -  --------*- C++ -*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_MATINT_H
+#define LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_MATINT_H
+
+#include "llvm/ADT/SmallVector.h"
+#include <cstdint>
+
+namespace llvm {
+namespace LoongArchMatInt {
+struct Inst {
+  unsigned Opc;
+  int64_t Imm;
+  Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {}
+};
+using InstSeq = SmallVector<Inst, 4>;
+
+// Helper to generate an instruction sequence that will materialise the given
+// immediate value into a register.
+InstSeq generateInstSeq(int64_t Val);
+} // namespace LoongArchMatInt
+} // namespace llvm
+#endif

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMatInt.cpp

+//===- LoongArchMatInt.cpp - Immediate materialisation ---------*- C++ -*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "LoongArchMatInt.h"
+#include "MCTargetDesc/LoongArchMCTargetDesc.h"
+#include "llvm/Support/MathExtras.h"
+
+using namespace llvm;
+
+LoongArchMatInt::InstSeq LoongArchMatInt::generateInstSeq(int64_t Val) {
+  // Val:
+  // |            hi32              |              lo32            |
+  // +-----------+------------------+------------------+-----------+
+  // | Highest12 |    Higher20      |       Hi20       |    Lo12   |
+  // +-----------+------------------+------------------+-----------+
+  // 63        52 51              32 31              12 11         0
+  //
+  const int64_t Highest12 = Val >> 52 & 0xFFF;
+  const int64_t Higher20 = Val >> 32 & 0xFFFFF;
+  const int64_t Hi20 = Val >> 12 & 0xFFFFF;
+  const int64_t Lo12 = Val & 0xFFF;
+  InstSeq Insts;
+
+  if (Highest12 != 0 && SignExtend64<52>(Val) == 0) {
+    Insts.push_back(Inst(LoongArch::LU52I_D, SignExtend64<12>(Highest12)));
+    return Insts;
+  }
+
+  if (Hi20 == 0)
+    Insts.push_back(Inst(LoongArch::ORI, Lo12));
+  else if (SignExtend32<1>(Lo12 >> 11) == SignExtend32<20>(Hi20))
+    Insts.push_back(Inst(LoongArch::ADDI_W, SignExtend64<12>(Lo12)));
+  else {
+    Insts.push_back(Inst(LoongArch::LU12I_W, SignExtend64<20>(Hi20)));
+    if (Lo12 != 0)
+      Insts.push_back(Inst(LoongArch::ORI, Lo12));
+  }
+
+  if (SignExtend32<1>(Hi20 >> 19) != SignExtend32<20>(Higher20))
+    Insts.push_back(Inst(LoongArch::LU32I_D, SignExtend64<20>(Higher20)));
+
+  if (SignExtend32<1>(Higher20 >> 19) != SignExtend32<12>(Highest12))
+    Insts.push_back(Inst(LoongArch::LU52I_D, SignExtend64<12>(Highest12)));
+
+  return Insts;
+}

llvm/test/CodeGen/LoongArch/imm.ll

+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefixes=ALL,CHECK-32
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefixes=ALL,CHECK-64
+
+define i32 @imm00000000() {
+; ALL-LABEL: imm00000000:
+; ALL:       # %bb.0:
+; ALL-NEXT:    ori $a0, $zero, 0
+; ALL-NEXT:    jirl $zero, $ra, 0
+  ret i32 0
+}
+
+define i32 @imm000007ff() {
+; ALL-LABEL: imm000007ff:
+; ALL:       # %bb.0:
+; ALL-NEXT:    ori $a0, $zero, 2047
+; ALL-NEXT:    jirl $zero, $ra, 0
+  ret i32 2047
+}
+
+define i32 @imm00000800() {
+; ALL-LABEL: imm00000800:
+; ALL:       # %bb.0:
+; ALL-NEXT:    ori $a0, $zero, 2048
+; ALL-NEXT:    jirl $zero, $ra, 0
+  ret i32 2048
+}
+
+define i32 @imm00000fff() {
+; ALL-LABEL: imm00000fff:
+; ALL:       # %bb.0:
+; ALL-NEXT:    ori $a0, $zero, 4095
+; ALL-NEXT:    jirl $zero, $ra, 0
+  ret i32 4095
+}
+
+define i32 @imm7ffff000() {
+; ALL-LABEL: imm7ffff000:
+; ALL:       # %bb.0:
+; ALL-NEXT:    lu12i.w $a0, 524287
+; ALL-NEXT:    jirl $zero, $ra, 0
+  ret i32 2147479552
+}
+
+define i32 @imm7ffff7ff() {
+; ALL-LABEL: imm7ffff7ff:
+; ALL:       # %bb.0:
+; ALL-NEXT:    lu12i.w $a0, 524287
+; ALL-NEXT:    ori $a0, $a0, 2047
+; ALL-NEXT:    jirl $zero, $ra, 0
+  ret i32 2147481599
+}
+
+define i32 @imm7ffff800() {
+; ALL-LABEL: imm7ffff800:
+; ALL:       # %bb.0:
+; ALL-NEXT:    lu12i.w $a0, 524287
+; ALL-NEXT:    ori $a0, $a0, 2048
+; ALL-NEXT:    jirl $zero, $ra, 0
+  ret i32 2147481600
+}
+
+define i32 @imm7fffffff() {
+; ALL-LABEL: imm7fffffff:
+; ALL:       # %bb.0:
+; ALL-NEXT:    lu12i.w $a0, 524287
+; ALL-NEXT:    ori $a0, $a0, 4095
+; ALL-NEXT:    jirl $zero, $ra, 0
+  ret i32 2147483647
+}
+
+define i32 @imm80000000() {
+; CHECK-32-LABEL: imm80000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm80000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i32 -2147483648
+}
+
+define i32 @imm800007ff() {
+; CHECK-32-LABEL: imm800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i32 -2147481601
+}
+
+define i32 @imm80000800() {
+; CHECK-32-LABEL: imm80000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm80000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i32 -2147481600
+}
+
+define i32 @imm80000fff() {
+; CHECK-32-LABEL: imm80000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm80000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i32 -2147479553
+}
+
+define i32 @immfffff000() {
+; CHECK-32-LABEL: immfffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i32 -4096
+}
+
+define i32 @immfffff7ff() {
+; CHECK-32-LABEL: immfffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i32 -2049
+}
+
+define i32 @immfffff800() {
+; CHECK-32-LABEL: immfffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i32 -2048
+}
+
+define i32 @immffffffff() {
+; CHECK-32-LABEL: immffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i32 -1
+}
+
+define i64 @imm0000000000000000() {
+; CHECK-32-LABEL: imm0000000000000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 0
+; CHECK-32-NEXT:    move $a1, $a0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0000000000000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 0
+}
+
+define i64 @imm00000000000007ff() {
+; CHECK-32-LABEL: imm00000000000007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2047
+; CHECK-32-NEXT:    ori $a1, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm00000000000007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2047
+}
+
+define i64 @imm0000000000000800() {
+; CHECK-32-LABEL: imm0000000000000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2048
+; CHECK-32-NEXT:    ori $a1, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0000000000000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2048
+}
+
+define i64 @imm0000000000000fff() {
+; CHECK-32-LABEL: imm0000000000000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 4095
+; CHECK-32-NEXT:    ori $a1, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0000000000000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 4095
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4095
+}
+
+define i64 @imm000000007ffff000() {
+; CHECK-32-LABEL: imm000000007ffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a1, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000000007ffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2147479552
+}
+
+define i64 @imm000000007ffff7ff() {
+; CHECK-32-LABEL: imm000000007ffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    ori $a1, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000000007ffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2147481599
+}
+
+define i64 @imm000000007ffff800() {
+; CHECK-32-LABEL: imm000000007ffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    ori $a1, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000000007ffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2147481600
+}
+
+define i64 @imm000000007fffffff() {
+; CHECK-32-LABEL: imm000000007fffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    ori $a1, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000000007fffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2147483647
+}
+
+define i64 @imm0000000080000000() {
+; CHECK-32-LABEL: imm0000000080000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a1, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0000000080000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2147483648
+}
+
+define i64 @imm00000000800007ff() {
+; CHECK-32-LABEL: imm00000000800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    ori $a1, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm00000000800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2147485695
+}
+
+define i64 @imm0000000080000800() {
+; CHECK-32-LABEL: imm0000000080000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    ori $a1, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0000000080000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2147485696
+}
+
+define i64 @imm0000000080000fff() {
+; CHECK-32-LABEL: imm0000000080000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    ori $a1, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0000000080000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2147487743
+}
+
+define i64 @imm00000000fffff000() {
+; CHECK-32-LABEL: imm00000000fffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a1, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm00000000fffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4294963200
+}
+
+define i64 @imm00000000fffff7ff() {
+; CHECK-32-LABEL: imm00000000fffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    ori $a1, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm00000000fffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4294965247
+}
+
+define i64 @imm00000000fffff800() {
+; CHECK-32-LABEL: imm00000000fffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    ori $a1, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm00000000fffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4294965248
+}
+
+define i64 @imm00000000ffffffff() {
+; CHECK-32-LABEL: imm00000000ffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    ori $a1, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm00000000ffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4294967295
+}
+
+define i64 @imm0007ffff00000000() {
+; CHECK-32-LABEL: imm0007ffff00000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 127
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0007ffff00000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 0
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251795518717952
+}
+
+define i64 @imm0007ffff000007ff() {
+; CHECK-32-LABEL: imm0007ffff000007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 127
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 2047
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0007ffff000007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251795518719999
+}
+
+define i64 @imm0007ffff00000800() {
+; CHECK-32-LABEL: imm0007ffff00000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 127
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0007ffff00000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251795518720000
+}
+
+define i64 @imm0007ffff00000fff() {
+; CHECK-32-LABEL: imm0007ffff00000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 127
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0007ffff00000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251795518722047
+}
+
+define i64 @imm0007ffff7ffff000() {
+; CHECK-32-LABEL: imm0007ffff7ffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 127
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0007ffff7ffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251797666197504
+}
+
+define i64 @imm0007ffff7ffff7ff() {
+; CHECK-32-LABEL: imm0007ffff7ffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 127
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0007ffff7ffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251797666199551
+}
+
+define i64 @imm0007ffff7ffff800() {
+; CHECK-32-LABEL: imm0007ffff7ffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, 127
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0007ffff7ffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251797666199552
+}
+
+define i64 @imm0007ffff7fffffff() {
+; CHECK-32-LABEL: imm0007ffff7fffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, 127
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0007ffff7fffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251797666201599
+}
+
+define i64 @imm0007ffff80000000() {
+; CHECK-32-LABEL: imm0007ffff80000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 127
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0007ffff80000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251797666201600
+}
+
+define i64 @imm0007ffff800007ff() {
+; CHECK-32-LABEL: imm0007ffff800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 127
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0007ffff800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251797666203647
+}
+
+define i64 @imm0007ffff80000800() {
+; CHECK-32-LABEL: imm0007ffff80000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, 127
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0007ffff80000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251797666203648
+}
+
+define i64 @imm0007ffff80000fff() {
+; CHECK-32-LABEL: imm0007ffff80000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, 127
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0007ffff80000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251797666205695
+}
+
+define i64 @imm0007fffffffff000() {
+; CHECK-32-LABEL: imm0007fffffffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 127
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0007fffffffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251799813681152
+}
+
+define i64 @imm0007fffffffff7ff() {
+; CHECK-32-LABEL: imm0007fffffffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 127
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0007fffffffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251799813683199
+}
+
+define i64 @imm0007fffffffff800() {
+; CHECK-32-LABEL: imm0007fffffffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 127
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0007fffffffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251799813683200
+}
+
+define i64 @imm0007ffffffffffff() {
+; CHECK-32-LABEL: imm0007ffffffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 127
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0007ffffffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251799813685247
+}
+
+define i64 @imm0008000000000000() {
+; CHECK-32-LABEL: imm0008000000000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 0
+; CHECK-32-NEXT:    lu12i.w $a1, 128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0008000000000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 0
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251799813685248
+}
+
+define i64 @imm00080000000007ff() {
+; CHECK-32-LABEL: imm00080000000007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm00080000000007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251799813687295
+}
+
+define i64 @imm0008000000000800() {
+; CHECK-32-LABEL: imm0008000000000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, 128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0008000000000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251799813687296
+}
+
+define i64 @imm0008000000000fff() {
+; CHECK-32-LABEL: imm0008000000000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, 128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0008000000000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251799813689343
+}
+
+define i64 @imm000800007ffff000() {
+; CHECK-32-LABEL: imm000800007ffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    lu12i.w $a1, 128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000800007ffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251801961164800
+}
+
+define i64 @imm000800007ffff7ff() {
+; CHECK-32-LABEL: imm000800007ffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000800007ffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251801961166847
+}
+
+define i64 @imm000800007ffff800() {
+; CHECK-32-LABEL: imm000800007ffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, 128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000800007ffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251801961166848
+}
+
+define i64 @imm000800007fffffff() {
+; CHECK-32-LABEL: imm000800007fffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, 128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000800007fffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251801961168895
+}
+
+define i64 @imm0008000080000000() {
+; CHECK-32-LABEL: imm0008000080000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    lu12i.w $a1, 128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0008000080000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251801961168896
+}
+
+define i64 @imm00080000800007ff() {
+; CHECK-32-LABEL: imm00080000800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm00080000800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251801961170943
+}
+
+define i64 @imm0008000080000800() {
+; CHECK-32-LABEL: imm0008000080000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, 128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0008000080000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251801961170944
+}
+
+define i64 @imm0008000080000fff() {
+; CHECK-32-LABEL: imm0008000080000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, 128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm0008000080000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251801961172991
+}
+
+define i64 @imm00080000fffff000() {
+; CHECK-32-LABEL: imm00080000fffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    lu12i.w $a1, 128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm00080000fffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251804108648448
+}
+
+define i64 @imm00080000fffff7ff() {
+; CHECK-32-LABEL: imm00080000fffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm00080000fffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251804108650495
+}
+
+define i64 @imm00080000fffff800() {
+; CHECK-32-LABEL: imm00080000fffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    lu12i.w $a1, 128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm00080000fffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251804108650496
+}
+
+define i64 @imm00080000ffffffff() {
+; CHECK-32-LABEL: imm00080000ffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    lu12i.w $a1, 128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm00080000ffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 2251804108652543
+}
+
+define i64 @imm000fffff00000000() {
+; CHECK-32-LABEL: imm000fffff00000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 255
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000fffff00000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 0
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4503595332403200
+}
+
+define i64 @imm000fffff000007ff() {
+; CHECK-32-LABEL: imm000fffff000007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 255
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 2047
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000fffff000007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4503595332405247
+}
+
+define i64 @imm000fffff00000800() {
+; CHECK-32-LABEL: imm000fffff00000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 255
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000fffff00000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4503595332405248
+}
+
+define i64 @imm000fffff00000fff() {
+; CHECK-32-LABEL: imm000fffff00000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 255
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000fffff00000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4503595332407295
+}
+
+define i64 @imm000fffff7ffff000() {
+; CHECK-32-LABEL: imm000fffff7ffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 255
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000fffff7ffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4503597479882752
+}
+
+define i64 @imm000fffff7ffff7ff() {
+; CHECK-32-LABEL: imm000fffff7ffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 255
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000fffff7ffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4503597479884799
+}
+
+define i64 @imm000fffff7ffff800() {
+; CHECK-32-LABEL: imm000fffff7ffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, 255
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000fffff7ffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4503597479884800
+}
+
+define i64 @imm000fffff7fffffff() {
+; CHECK-32-LABEL: imm000fffff7fffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, 255
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000fffff7fffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4503597479886847
+}
+
+define i64 @imm000fffff80000000() {
+; CHECK-32-LABEL: imm000fffff80000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 255
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000fffff80000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4503597479886848
+}
+
+define i64 @imm000fffff800007ff() {
+; CHECK-32-LABEL: imm000fffff800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 255
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000fffff800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4503597479888895
+}
+
+define i64 @imm000fffff80000800() {
+; CHECK-32-LABEL: imm000fffff80000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, 255
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000fffff80000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4503597479888896
+}
+
+define i64 @imm000fffff80000fff() {
+; CHECK-32-LABEL: imm000fffff80000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, 255
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000fffff80000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4503597479890943
+}
+
+define i64 @imm000ffffffffff000() {
+; CHECK-32-LABEL: imm000ffffffffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 255
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000ffffffffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4503599627366400
+}
+
+define i64 @imm000ffffffffff7ff() {
+; CHECK-32-LABEL: imm000ffffffffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 255
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000ffffffffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4503599627368447
+}
+
+define i64 @imm000ffffffffff800() {
+; CHECK-32-LABEL: imm000ffffffffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 255
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000ffffffffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4503599627368448
+}
+
+define i64 @imm000fffffffffffff() {
+; CHECK-32-LABEL: imm000fffffffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 255
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm000fffffffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 0
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 4503599627370495
+}
+
+define i64 @imm7ff0000000000000() {
+; CHECK-32-LABEL: imm7ff0000000000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 0
+; CHECK-32-NEXT:    lu12i.w $a1, 524032
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff0000000000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu52i.d $a0, $zero, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9218868437227405312
+}
+
+define i64 @imm7ff00000000007ff() {
+; CHECK-32-LABEL: imm7ff00000000007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 524032
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff00000000007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2047
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9218868437227407359
+}
+
+define i64 @imm7ff0000000000800() {
+; CHECK-32-LABEL: imm7ff0000000000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, 524032
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff0000000000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2048
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9218868437227407360
+}
+
+define i64 @imm7ff0000000000fff() {
+; CHECK-32-LABEL: imm7ff0000000000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, 524032
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff0000000000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 4095
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9218868437227409407
+}
+
+define i64 @imm7ff000007ffff000() {
+; CHECK-32-LABEL: imm7ff000007ffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    lu12i.w $a1, 524032
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff000007ffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9218868439374884864
+}
+
+define i64 @imm7ff000007ffff7ff() {
+; CHECK-32-LABEL: imm7ff000007ffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 524032
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff000007ffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9218868439374886911
+}
+
+define i64 @imm7ff000007ffff800() {
+; CHECK-32-LABEL: imm7ff000007ffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, 524032
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff000007ffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9218868439374886912
+}
+
+define i64 @imm7ff000007fffffff() {
+; CHECK-32-LABEL: imm7ff000007fffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, 524032
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff000007fffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9218868439374888959
+}
+
+define i64 @imm7ff0000080000000() {
+; CHECK-32-LABEL: imm7ff0000080000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    lu12i.w $a1, 524032
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff0000080000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9218868439374888960
+}
+
+define i64 @imm7ff00000800007ff() {
+; CHECK-32-LABEL: imm7ff00000800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 524032
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff00000800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9218868439374891007
+}
+
+define i64 @imm7ff0000080000800() {
+; CHECK-32-LABEL: imm7ff0000080000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, 524032
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff0000080000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9218868439374891008
+}
+
+define i64 @imm7ff0000080000fff() {
+; CHECK-32-LABEL: imm7ff0000080000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, 524032
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff0000080000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9218868439374893055
+}
+
+define i64 @imm7ff00000fffff000() {
+; CHECK-32-LABEL: imm7ff00000fffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    lu12i.w $a1, 524032
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff00000fffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9218868441522368512
+}
+
+define i64 @imm7ff00000fffff7ff() {
+; CHECK-32-LABEL: imm7ff00000fffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 524032
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff00000fffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9218868441522370559
+}
+
+define i64 @imm7ff00000fffff800() {
+; CHECK-32-LABEL: imm7ff00000fffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    lu12i.w $a1, 524032
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff00000fffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9218868441522370560
+}
+
+define i64 @imm7ff00000ffffffff() {
+; CHECK-32-LABEL: imm7ff00000ffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    lu12i.w $a1, 524032
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff00000ffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9218868441522372607
+}
+
+define i64 @imm7ff7ffff00000000() {
+; CHECK-32-LABEL: imm7ff7ffff00000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524159
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff7ffff00000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 0
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120232746123264
+}
+
+define i64 @imm7ff7ffff000007ff() {
+; CHECK-32-LABEL: imm7ff7ffff000007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524159
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 2047
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff7ffff000007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120232746125311
+}
+
+define i64 @imm7ff7ffff00000800() {
+; CHECK-32-LABEL: imm7ff7ffff00000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524159
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff7ffff00000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120232746125312
+}
+
+define i64 @imm7ff7ffff00000fff() {
+; CHECK-32-LABEL: imm7ff7ffff00000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524159
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff7ffff00000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120232746127359
+}
+
+define i64 @imm7ff7ffff7ffff000() {
+; CHECK-32-LABEL: imm7ff7ffff7ffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524159
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff7ffff7ffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120234893602816
+}
+
+define i64 @imm7ff7ffff7ffff7ff() {
+; CHECK-32-LABEL: imm7ff7ffff7ffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 524159
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff7ffff7ffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120234893604863
+}
+
+define i64 @imm7ff7ffff7ffff800() {
+; CHECK-32-LABEL: imm7ff7ffff7ffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, 524159
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff7ffff7ffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120234893604864
+}
+
+define i64 @imm7ff7ffff7fffffff() {
+; CHECK-32-LABEL: imm7ff7ffff7fffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, 524159
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff7ffff7fffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120234893606911
+}
+
+define i64 @imm7ff7ffff80000000() {
+; CHECK-32-LABEL: imm7ff7ffff80000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524159
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff7ffff80000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120234893606912
+}
+
+define i64 @imm7ff7ffff800007ff() {
+; CHECK-32-LABEL: imm7ff7ffff800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 524159
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff7ffff800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120234893608959
+}
+
+define i64 @imm7ff7ffff80000800() {
+; CHECK-32-LABEL: imm7ff7ffff80000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, 524159
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff7ffff80000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120234893608960
+}
+
+define i64 @imm7ff7ffff80000fff() {
+; CHECK-32-LABEL: imm7ff7ffff80000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, 524159
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff7ffff80000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120234893611007
+}
+
+define i64 @imm7ff7fffffffff000() {
+; CHECK-32-LABEL: imm7ff7fffffffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524159
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff7fffffffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120237041086464
+}
+
+define i64 @imm7ff7fffffffff7ff() {
+; CHECK-32-LABEL: imm7ff7fffffffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 524159
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff7fffffffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120237041088511
+}
+
+define i64 @imm7ff7fffffffff800() {
+; CHECK-32-LABEL: imm7ff7fffffffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524159
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff7fffffffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120237041088512
+}
+
+define i64 @imm7ff7ffffffffffff() {
+; CHECK-32-LABEL: imm7ff7ffffffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524159
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff7ffffffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120237041090559
+}
+
+define i64 @imm7ff8000000000000() {
+; CHECK-32-LABEL: imm7ff8000000000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 0
+; CHECK-32-NEXT:    lu12i.w $a1, 524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff8000000000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 0
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120237041090560
+}
+
+define i64 @imm7ff80000000007ff() {
+; CHECK-32-LABEL: imm7ff80000000007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff80000000007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120237041092607
+}
+
+define i64 @imm7ff8000000000800() {
+; CHECK-32-LABEL: imm7ff8000000000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, 524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff8000000000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120237041092608
+}
+
+define i64 @imm7ff8000000000fff() {
+; CHECK-32-LABEL: imm7ff8000000000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, 524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff8000000000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120237041094655
+}
+
+define i64 @imm7ff800007ffff000() {
+; CHECK-32-LABEL: imm7ff800007ffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    lu12i.w $a1, 524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff800007ffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120239188570112
+}
+
+define i64 @imm7ff800007ffff7ff() {
+; CHECK-32-LABEL: imm7ff800007ffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff800007ffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120239188572159
+}
+
+define i64 @imm7ff800007ffff800() {
+; CHECK-32-LABEL: imm7ff800007ffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, 524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff800007ffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120239188572160
+}
+
+define i64 @imm7ff800007fffffff() {
+; CHECK-32-LABEL: imm7ff800007fffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, 524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff800007fffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120239188574207
+}
+
+define i64 @imm7ff8000080000000() {
+; CHECK-32-LABEL: imm7ff8000080000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    lu12i.w $a1, 524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff8000080000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120239188574208
+}
+
+define i64 @imm7ff80000800007ff() {
+; CHECK-32-LABEL: imm7ff80000800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff80000800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120239188576255
+}
+
+define i64 @imm7ff8000080000800() {
+; CHECK-32-LABEL: imm7ff8000080000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, 524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff8000080000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120239188576256
+}
+
+define i64 @imm7ff8000080000fff() {
+; CHECK-32-LABEL: imm7ff8000080000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, 524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff8000080000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120239188578303
+}
+
+define i64 @imm7ff80000fffff000() {
+; CHECK-32-LABEL: imm7ff80000fffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    lu12i.w $a1, 524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff80000fffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120241336053760
+}
+
+define i64 @imm7ff80000fffff7ff() {
+; CHECK-32-LABEL: imm7ff80000fffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff80000fffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120241336055807
+}
+
+define i64 @imm7ff80000fffff800() {
+; CHECK-32-LABEL: imm7ff80000fffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    lu12i.w $a1, 524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff80000fffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120241336055808
+}
+
+define i64 @imm7ff80000ffffffff() {
+; CHECK-32-LABEL: imm7ff80000ffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    lu12i.w $a1, 524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ff80000ffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9221120241336057855
+}
+
+define i64 @imm7fffffff00000000() {
+; CHECK-32-LABEL: imm7fffffff00000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7fffffff00000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 0
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9223372032559808512
+}
+
+define i64 @imm7fffffff000007ff() {
+; CHECK-32-LABEL: imm7fffffff000007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 2047
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7fffffff000007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9223372032559810559
+}
+
+define i64 @imm7fffffff00000800() {
+; CHECK-32-LABEL: imm7fffffff00000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7fffffff00000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9223372032559810560
+}
+
+define i64 @imm7fffffff00000fff() {
+; CHECK-32-LABEL: imm7fffffff00000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7fffffff00000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9223372032559812607
+}
+
+define i64 @imm7fffffff7ffff000() {
+; CHECK-32-LABEL: imm7fffffff7ffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7fffffff7ffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9223372034707288064
+}
+
+define i64 @imm7fffffff7ffff7ff() {
+; CHECK-32-LABEL: imm7fffffff7ffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a1, 524287
+; CHECK-32-NEXT:    ori $a0, $a1, 2047
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7fffffff7ffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9223372034707290111
+}
+
+define i64 @imm7fffffff7ffff800() {
+; CHECK-32-LABEL: imm7fffffff7ffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a1, 524287
+; CHECK-32-NEXT:    ori $a0, $a1, 2048
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7fffffff7ffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9223372034707290112
+}
+
+define i64 @imm7fffffff7fffffff() {
+; CHECK-32-LABEL: imm7fffffff7fffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    move $a1, $a0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7fffffff7fffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9223372034707292159
+}
+
+define i64 @imm7fffffff80000000() {
+; CHECK-32-LABEL: imm7fffffff80000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7fffffff80000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9223372034707292160
+}
+
+define i64 @imm7fffffff800007ff() {
+; CHECK-32-LABEL: imm7fffffff800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 524287
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7fffffff800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9223372034707294207
+}
+
+define i64 @imm7fffffff80000800() {
+; CHECK-32-LABEL: imm7fffffff80000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, 524287
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7fffffff80000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9223372034707294208
+}
+
+define i64 @imm7fffffff80000fff() {
+; CHECK-32-LABEL: imm7fffffff80000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, 524287
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7fffffff80000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9223372034707296255
+}
+
+define i64 @imm7ffffffffffff000() {
+; CHECK-32-LABEL: imm7ffffffffffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ffffffffffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9223372036854771712
+}
+
+define i64 @imm7ffffffffffff7ff() {
+; CHECK-32-LABEL: imm7ffffffffffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, 524287
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ffffffffffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9223372036854773759
+}
+
+define i64 @imm7ffffffffffff800() {
+; CHECK-32-LABEL: imm7ffffffffffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7ffffffffffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9223372036854773760
+}
+
+define i64 @imm7fffffffffffffff() {
+; CHECK-32-LABEL: imm7fffffffffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm7fffffffffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 9223372036854775807
+}
+
+define i64 @imm8000000000000000() {
+; CHECK-32-LABEL: imm8000000000000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 0
+; CHECK-32-NEXT:    lu12i.w $a1, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8000000000000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu52i.d $a0, $zero, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9223372036854775808
+}
+
+define i64 @imm80000000000007ff() {
+; CHECK-32-LABEL: imm80000000000007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm80000000000007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2047
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9223372036854773761
+}
+
+define i64 @imm8000000000000800() {
+; CHECK-32-LABEL: imm8000000000000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8000000000000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2048
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9223372036854773760
+}
+
+define i64 @imm8000000000000fff() {
+; CHECK-32-LABEL: imm8000000000000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8000000000000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 4095
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9223372036854771713
+}
+
+define i64 @imm800000007ffff000() {
+; CHECK-32-LABEL: imm800000007ffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    lu12i.w $a1, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800000007ffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9223372034707296256
+}
+
+define i64 @imm800000007ffff7ff() {
+; CHECK-32-LABEL: imm800000007ffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800000007ffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9223372034707294209
+}
+
+define i64 @imm800000007ffff800() {
+; CHECK-32-LABEL: imm800000007ffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800000007ffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9223372034707294208
+}
+
+define i64 @imm800000007fffffff() {
+; CHECK-32-LABEL: imm800000007fffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800000007fffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9223372034707292161
+}
+
+define i64 @imm8000000080000000() {
+; CHECK-32-LABEL: imm8000000080000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    move $a1, $a0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8000000080000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9223372034707292160
+}
+
+define i64 @imm80000000800007ff() {
+; CHECK-32-LABEL: imm80000000800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a1, -524288
+; CHECK-32-NEXT:    ori $a0, $a1, 2047
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm80000000800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9223372034707290113
+}
+
+define i64 @imm8000000080000800() {
+; CHECK-32-LABEL: imm8000000080000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a1, -524288
+; CHECK-32-NEXT:    ori $a0, $a1, 2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8000000080000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9223372034707290112
+}
+
+define i64 @imm8000000080000fff() {
+; CHECK-32-LABEL: imm8000000080000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a1, -524288
+; CHECK-32-NEXT:    ori $a0, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8000000080000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9223372034707288065
+}
+
+define i64 @imm80000000fffff000() {
+; CHECK-32-LABEL: imm80000000fffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    lu12i.w $a1, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm80000000fffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9223372032559812608
+}
+
+define i64 @imm80000000fffff7ff() {
+; CHECK-32-LABEL: imm80000000fffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm80000000fffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9223372032559810561
+}
+
+define i64 @imm80000000fffff800() {
+; CHECK-32-LABEL: imm80000000fffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    lu12i.w $a1, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm80000000fffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9223372032559810560
+}
+
+define i64 @imm80000000ffffffff() {
+; CHECK-32-LABEL: imm80000000ffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    lu12i.w $a1, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm80000000ffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9223372032559808513
+}
+
+define i64 @imm8007ffff00000000() {
+; CHECK-32-LABEL: imm8007ffff00000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524161
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8007ffff00000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 0
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120241336057856
+}
+
+define i64 @imm8007ffff000007ff() {
+; CHECK-32-LABEL: imm8007ffff000007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524161
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 2047
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8007ffff000007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120241336055809
+}
+
+define i64 @imm8007ffff00000800() {
+; CHECK-32-LABEL: imm8007ffff00000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524161
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8007ffff00000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120241336055808
+}
+
+define i64 @imm8007ffff00000fff() {
+; CHECK-32-LABEL: imm8007ffff00000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524161
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8007ffff00000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120241336053761
+}
+
+define i64 @imm8007ffff7ffff000() {
+; CHECK-32-LABEL: imm8007ffff7ffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524161
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8007ffff7ffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120239188578304
+}
+
+define i64 @imm8007ffff7ffff7ff() {
+; CHECK-32-LABEL: imm8007ffff7ffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -524161
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8007ffff7ffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120239188576257
+}
+
+define i64 @imm8007ffff7ffff800() {
+; CHECK-32-LABEL: imm8007ffff7ffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -524161
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8007ffff7ffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120239188576256
+}
+
+define i64 @imm8007ffff7fffffff() {
+; CHECK-32-LABEL: imm8007ffff7fffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -524161
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8007ffff7fffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120239188574209
+}
+
+define i64 @imm8007ffff80000000() {
+; CHECK-32-LABEL: imm8007ffff80000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524161
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8007ffff80000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120239188574208
+}
+
+define i64 @imm8007ffff800007ff() {
+; CHECK-32-LABEL: imm8007ffff800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -524161
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8007ffff800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120239188572161
+}
+
+define i64 @imm8007ffff80000800() {
+; CHECK-32-LABEL: imm8007ffff80000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -524161
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8007ffff80000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120239188572160
+}
+
+define i64 @imm8007ffff80000fff() {
+; CHECK-32-LABEL: imm8007ffff80000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -524161
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8007ffff80000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120239188570113
+}
+
+define i64 @imm8007fffffffff000() {
+; CHECK-32-LABEL: imm8007fffffffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524161
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8007fffffffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120237041094656
+}
+
+define i64 @imm8007fffffffff7ff() {
+; CHECK-32-LABEL: imm8007fffffffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -524161
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8007fffffffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120237041092609
+}
+
+define i64 @imm8007fffffffff800() {
+; CHECK-32-LABEL: imm8007fffffffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524161
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8007fffffffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120237041092608
+}
+
+define i64 @imm8007ffffffffffff() {
+; CHECK-32-LABEL: imm8007ffffffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524161
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8007ffffffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120237041090561
+}
+
+define i64 @imm8008000000000000() {
+; CHECK-32-LABEL: imm8008000000000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 0
+; CHECK-32-NEXT:    lu12i.w $a1, -524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8008000000000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 0
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120237041090560
+}
+
+define i64 @imm80080000000007ff() {
+; CHECK-32-LABEL: imm80080000000007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm80080000000007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120237041088513
+}
+
+define i64 @imm8008000000000800() {
+; CHECK-32-LABEL: imm8008000000000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8008000000000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120237041088512
+}
+
+define i64 @imm8008000000000fff() {
+; CHECK-32-LABEL: imm8008000000000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8008000000000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120237041086465
+}
+
+define i64 @imm800800007ffff000() {
+; CHECK-32-LABEL: imm800800007ffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    lu12i.w $a1, -524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800800007ffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120234893611008
+}
+
+define i64 @imm800800007ffff7ff() {
+; CHECK-32-LABEL: imm800800007ffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800800007ffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120234893608961
+}
+
+define i64 @imm800800007ffff800() {
+; CHECK-32-LABEL: imm800800007ffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800800007ffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120234893608960
+}
+
+define i64 @imm800800007fffffff() {
+; CHECK-32-LABEL: imm800800007fffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800800007fffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120234893606913
+}
+
+define i64 @imm8008000080000000() {
+; CHECK-32-LABEL: imm8008000080000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    lu12i.w $a1, -524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8008000080000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120234893606912
+}
+
+define i64 @imm80080000800007ff() {
+; CHECK-32-LABEL: imm80080000800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm80080000800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120234893604865
+}
+
+define i64 @imm8008000080000800() {
+; CHECK-32-LABEL: imm8008000080000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8008000080000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120234893604864
+}
+
+define i64 @imm8008000080000fff() {
+; CHECK-32-LABEL: imm8008000080000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm8008000080000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120234893602817
+}
+
+define i64 @imm80080000fffff000() {
+; CHECK-32-LABEL: imm80080000fffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    lu12i.w $a1, -524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm80080000fffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120232746127360
+}
+
+define i64 @imm80080000fffff7ff() {
+; CHECK-32-LABEL: imm80080000fffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm80080000fffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120232746125313
+}
+
+define i64 @imm80080000fffff800() {
+; CHECK-32-LABEL: imm80080000fffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    lu12i.w $a1, -524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm80080000fffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120232746125312
+}
+
+define i64 @imm80080000ffffffff() {
+; CHECK-32-LABEL: imm80080000ffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    lu12i.w $a1, -524160
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm80080000ffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9221120232746123265
+}
+
+define i64 @imm800fffff00000000() {
+; CHECK-32-LABEL: imm800fffff00000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524033
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800fffff00000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 0
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9218868441522372608
+}
+
+define i64 @imm800fffff000007ff() {
+; CHECK-32-LABEL: imm800fffff000007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524033
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 2047
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800fffff000007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9218868441522370561
+}
+
+define i64 @imm800fffff00000800() {
+; CHECK-32-LABEL: imm800fffff00000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524033
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800fffff00000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9218868441522370560
+}
+
+define i64 @imm800fffff00000fff() {
+; CHECK-32-LABEL: imm800fffff00000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524033
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800fffff00000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9218868441522368513
+}
+
+define i64 @imm800fffff7ffff000() {
+; CHECK-32-LABEL: imm800fffff7ffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524033
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800fffff7ffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9218868439374893056
+}
+
+define i64 @imm800fffff7ffff7ff() {
+; CHECK-32-LABEL: imm800fffff7ffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -524033
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800fffff7ffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9218868439374891009
+}
+
+define i64 @imm800fffff7ffff800() {
+; CHECK-32-LABEL: imm800fffff7ffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -524033
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800fffff7ffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9218868439374891008
+}
+
+define i64 @imm800fffff7fffffff() {
+; CHECK-32-LABEL: imm800fffff7fffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -524033
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800fffff7fffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9218868439374888961
+}
+
+define i64 @imm800fffff80000000() {
+; CHECK-32-LABEL: imm800fffff80000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524033
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800fffff80000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9218868439374888960
+}
+
+define i64 @imm800fffff800007ff() {
+; CHECK-32-LABEL: imm800fffff800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -524033
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800fffff800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9218868439374886913
+}
+
+define i64 @imm800fffff80000800() {
+; CHECK-32-LABEL: imm800fffff80000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -524033
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800fffff80000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9218868439374886912
+}
+
+define i64 @imm800fffff80000fff() {
+; CHECK-32-LABEL: imm800fffff80000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -524033
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800fffff80000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9218868439374884865
+}
+
+define i64 @imm800ffffffffff000() {
+; CHECK-32-LABEL: imm800ffffffffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524033
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800ffffffffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9218868437227409408
+}
+
+define i64 @imm800ffffffffff7ff() {
+; CHECK-32-LABEL: imm800ffffffffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -524033
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800ffffffffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9218868437227407361
+}
+
+define i64 @imm800ffffffffff800() {
+; CHECK-32-LABEL: imm800ffffffffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524033
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800ffffffffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9218868437227407360
+}
+
+define i64 @imm800fffffffffffff() {
+; CHECK-32-LABEL: imm800fffffffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524033
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: imm800fffffffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -9218868437227405313
+}
+
+define i64 @immfff0000000000000() {
+; CHECK-32-LABEL: immfff0000000000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 0
+; CHECK-32-NEXT:    lu12i.w $a1, -256
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff0000000000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu52i.d $a0, $zero, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4503599627370496
+}
+
+define i64 @immfff00000000007ff() {
+; CHECK-32-LABEL: immfff00000000007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -256
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff00000000007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2047
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4503599627368449
+}
+
+define i64 @immfff0000000000800() {
+; CHECK-32-LABEL: immfff0000000000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -256
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff0000000000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2048
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4503599627368448
+}
+
+define i64 @immfff0000000000fff() {
+; CHECK-32-LABEL: immfff0000000000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -256
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff0000000000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 4095
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4503599627366401
+}
+
+define i64 @immfff000007ffff000() {
+; CHECK-32-LABEL: immfff000007ffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    lu12i.w $a1, -256
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff000007ffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4503597479890944
+}
+
+define i64 @immfff000007ffff7ff() {
+; CHECK-32-LABEL: immfff000007ffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -256
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff000007ffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4503597479888897
+}
+
+define i64 @immfff000007ffff800() {
+; CHECK-32-LABEL: immfff000007ffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -256
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff000007ffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4503597479888896
+}
+
+define i64 @immfff000007fffffff() {
+; CHECK-32-LABEL: immfff000007fffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -256
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff000007fffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4503597479886849
+}
+
+define i64 @immfff0000080000000() {
+; CHECK-32-LABEL: immfff0000080000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    lu12i.w $a1, -256
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff0000080000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4503597479886848
+}
+
+define i64 @immfff00000800007ff() {
+; CHECK-32-LABEL: immfff00000800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -256
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff00000800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4503597479884801
+}
+
+define i64 @immfff0000080000800() {
+; CHECK-32-LABEL: immfff0000080000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -256
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff0000080000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4503597479884800
+}
+
+define i64 @immfff0000080000fff() {
+; CHECK-32-LABEL: immfff0000080000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -256
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff0000080000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4503597479882753
+}
+
+define i64 @immfff00000fffff000() {
+; CHECK-32-LABEL: immfff00000fffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    lu12i.w $a1, -256
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff00000fffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4503595332407296
+}
+
+define i64 @immfff00000fffff7ff() {
+; CHECK-32-LABEL: immfff00000fffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -256
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff00000fffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4503595332405249
+}
+
+define i64 @immfff00000fffff800() {
+; CHECK-32-LABEL: immfff00000fffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    lu12i.w $a1, -256
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff00000fffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4503595332405248
+}
+
+define i64 @immfff00000ffffffff() {
+; CHECK-32-LABEL: immfff00000ffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    lu12i.w $a1, -256
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff00000ffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 0
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4503595332403201
+}
+
+define i64 @immfff7ffff00000000() {
+; CHECK-32-LABEL: immfff7ffff00000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -129
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff7ffff00000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 0
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251804108652544
+}
+
+define i64 @immfff7ffff000007ff() {
+; CHECK-32-LABEL: immfff7ffff000007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -129
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 2047
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff7ffff000007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251804108650497
+}
+
+define i64 @immfff7ffff00000800() {
+; CHECK-32-LABEL: immfff7ffff00000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -129
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff7ffff00000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251804108650496
+}
+
+define i64 @immfff7ffff00000fff() {
+; CHECK-32-LABEL: immfff7ffff00000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -129
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    ori $a0, $zero, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff7ffff00000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251804108648449
+}
+
+define i64 @immfff7ffff7ffff000() {
+; CHECK-32-LABEL: immfff7ffff7ffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -129
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff7ffff7ffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251801961172992
+}
+
+define i64 @immfff7ffff7ffff7ff() {
+; CHECK-32-LABEL: immfff7ffff7ffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -129
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff7ffff7ffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251801961170945
+}
+
+define i64 @immfff7ffff7ffff800() {
+; CHECK-32-LABEL: immfff7ffff7ffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -129
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff7ffff7ffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251801961170944
+}
+
+define i64 @immfff7ffff7fffffff() {
+; CHECK-32-LABEL: immfff7ffff7fffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -129
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff7ffff7fffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251801961168897
+}
+
+define i64 @immfff7ffff80000000() {
+; CHECK-32-LABEL: immfff7ffff80000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -129
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff7ffff80000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251801961168896
+}
+
+define i64 @immfff7ffff800007ff() {
+; CHECK-32-LABEL: immfff7ffff800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -129
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff7ffff800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251801961166849
+}
+
+define i64 @immfff7ffff80000800() {
+; CHECK-32-LABEL: immfff7ffff80000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -129
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff7ffff80000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251801961166848
+}
+
+define i64 @immfff7ffff80000fff() {
+; CHECK-32-LABEL: immfff7ffff80000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -129
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff7ffff80000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251801961164801
+}
+
+define i64 @immfff7fffffffff000() {
+; CHECK-32-LABEL: immfff7fffffffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -129
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff7fffffffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251799813689344
+}
+
+define i64 @immfff7fffffffff7ff() {
+; CHECK-32-LABEL: immfff7fffffffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -129
+; CHECK-32-NEXT:    ori $a1, $a1, 4095
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff7fffffffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251799813687297
+}
+
+define i64 @immfff7fffffffff800() {
+; CHECK-32-LABEL: immfff7fffffffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -129
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff7fffffffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251799813687296
+}
+
+define i64 @immfff7ffffffffffff() {
+; CHECK-32-LABEL: immfff7ffffffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -129
+; CHECK-32-NEXT:    ori $a1, $a0, 4095
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff7ffffffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    lu32i.d $a0, 524287
+; CHECK-64-NEXT:    lu52i.d $a0, $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251799813685249
+}
+
+define i64 @immfff8000000000000() {
+; CHECK-32-LABEL: immfff8000000000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 0
+; CHECK-32-NEXT:    lu12i.w $a1, -128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff8000000000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 0
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251799813685248
+}
+
+define i64 @immfff80000000007ff() {
+; CHECK-32-LABEL: immfff80000000007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff80000000007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251799813683201
+}
+
+define i64 @immfff8000000000800() {
+; CHECK-32-LABEL: immfff8000000000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff8000000000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251799813683200
+}
+
+define i64 @immfff8000000000fff() {
+; CHECK-32-LABEL: immfff8000000000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff8000000000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251799813681153
+}
+
+define i64 @immfff800007ffff000() {
+; CHECK-32-LABEL: immfff800007ffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    lu12i.w $a1, -128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff800007ffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251797666205696
+}
+
+define i64 @immfff800007ffff7ff() {
+; CHECK-32-LABEL: immfff800007ffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff800007ffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251797666203649
+}
+
+define i64 @immfff800007ffff800() {
+; CHECK-32-LABEL: immfff800007ffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff800007ffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251797666203648
+}
+
+define i64 @immfff800007fffffff() {
+; CHECK-32-LABEL: immfff800007fffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff800007fffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251797666201601
+}
+
+define i64 @immfff8000080000000() {
+; CHECK-32-LABEL: immfff8000080000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    lu12i.w $a1, -128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff8000080000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251797666201600
+}
+
+define i64 @immfff80000800007ff() {
+; CHECK-32-LABEL: immfff80000800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff80000800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251797666199553
+}
+
+define i64 @immfff8000080000800() {
+; CHECK-32-LABEL: immfff8000080000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    lu12i.w $a1, -128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff8000080000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251797666199552
+}
+
+define i64 @immfff8000080000fff() {
+; CHECK-32-LABEL: immfff8000080000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    lu12i.w $a1, -128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff8000080000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251797666197505
+}
+
+define i64 @immfff80000fffff000() {
+; CHECK-32-LABEL: immfff80000fffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    lu12i.w $a1, -128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff80000fffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251795518722048
+}
+
+define i64 @immfff80000fffff7ff() {
+; CHECK-32-LABEL: immfff80000fffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    lu12i.w $a1, -128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff80000fffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251795518720001
+}
+
+define i64 @immfff80000fffff800() {
+; CHECK-32-LABEL: immfff80000fffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    lu12i.w $a1, -128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff80000fffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251795518720000
+}
+
+define i64 @immfff80000ffffffff() {
+; CHECK-32-LABEL: immfff80000ffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    lu12i.w $a1, -128
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfff80000ffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    lu32i.d $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2251795518717953
+}
+
+define i64 @immffffffff00000000() {
+; CHECK-32-LABEL: immffffffff00000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 0
+; CHECK-32-NEXT:    addi.w $a1, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immffffffff00000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 0
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4294967296
+}
+
+define i64 @immffffffff000007ff() {
+; CHECK-32-LABEL: immffffffff000007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2047
+; CHECK-32-NEXT:    addi.w $a1, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immffffffff000007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4294965249
+}
+
+define i64 @immffffffff00000800() {
+; CHECK-32-LABEL: immffffffff00000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 2048
+; CHECK-32-NEXT:    addi.w $a1, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immffffffff00000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4294965248
+}
+
+define i64 @immffffffff00000fff() {
+; CHECK-32-LABEL: immffffffff00000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    ori $a0, $zero, 4095
+; CHECK-32-NEXT:    addi.w $a1, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immffffffff00000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    ori $a0, $zero, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4294963201
+}
+
+define i64 @immffffffff7ffff000() {
+; CHECK-32-LABEL: immffffffff7ffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    addi.w $a1, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immffffffff7ffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2147487744
+}
+
+define i64 @immffffffff7ffff7ff() {
+; CHECK-32-LABEL: immffffffff7ffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    addi.w $a1, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immffffffff7ffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2147485697
+}
+
+define i64 @immffffffff7ffff800() {
+; CHECK-32-LABEL: immffffffff7ffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    addi.w $a1, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immffffffff7ffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2147485696
+}
+
+define i64 @immffffffff7fffffff() {
+; CHECK-32-LABEL: immffffffff7fffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, 524287
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    addi.w $a1, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immffffffff7fffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, 524287
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    lu32i.d $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2147483649
+}
+
+define i64 @immffffffff80000000() {
+; CHECK-32-LABEL: immffffffff80000000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    addi.w $a1, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immffffffff80000000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2147483648
+}
+
+define i64 @immffffffff800007ff() {
+; CHECK-32-LABEL: immffffffff800007ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    addi.w $a1, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immffffffff800007ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2147481601
+}
+
+define i64 @immffffffff80000800() {
+; CHECK-32-LABEL: immffffffff80000800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 2048
+; CHECK-32-NEXT:    addi.w $a1, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immffffffff80000800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2147481600
+}
+
+define i64 @immffffffff80000fff() {
+; CHECK-32-LABEL: immffffffff80000fff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -524288
+; CHECK-32-NEXT:    ori $a0, $a0, 4095
+; CHECK-32-NEXT:    addi.w $a1, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immffffffff80000fff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -524288
+; CHECK-64-NEXT:    ori $a0, $a0, 4095
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2147479553
+}
+
+define i64 @immfffffffffffff000() {
+; CHECK-32-LABEL: immfffffffffffff000:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    addi.w $a1, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfffffffffffff000:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -4096
+}
+
+define i64 @immfffffffffffff7ff() {
+; CHECK-32-LABEL: immfffffffffffff7ff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    lu12i.w $a0, -1
+; CHECK-32-NEXT:    ori $a0, $a0, 2047
+; CHECK-32-NEXT:    addi.w $a1, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfffffffffffff7ff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    lu12i.w $a0, -1
+; CHECK-64-NEXT:    ori $a0, $a0, 2047
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2049
+}
+
+define i64 @immfffffffffffff800() {
+; CHECK-32-LABEL: immfffffffffffff800:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-32-NEXT:    addi.w $a1, $zero, -1
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immfffffffffffff800:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -2048
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -2048
+}
+
+define i64 @immffffffffffffffff() {
+; CHECK-32-LABEL: immffffffffffffffff:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi.w $a0, $zero, -1
+; CHECK-32-NEXT:    move $a1, $a0
+; CHECK-32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK-64-LABEL: immffffffffffffffff:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi.w $a0, $zero, -1
+; CHECK-64-NEXT:    jirl $zero, $ra, 0
+  ret i64 -1
+}