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Differential D123111

[AArch64] Make PMMIR_EL1 read-only.
ClosedPublic

Authored by simon_tatham on Apr 5 2022, 2:30 AM.

Details

Reviewers
labrinea
ostannard
vhscampos
Commits
rG82bd0bd24f61: [AArch64] Make PMMIR_EL1 read-only.
Summary

The Arm architecture reference manual (ARM DDI 0487H.a section
D13.5.12) lists every field in the register as RO, and does not list
an MSR instruction that writes it. So we should be defining it as an
ROSysReg, not an RWSysReg.

Diff Detail

Event Timeline

simon_tatham created this revision.Apr 5 2022, 2:30 AM
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simon_tatham requested review of this revision.Apr 5 2022, 2:30 AM
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vhscampos added inline comments.Apr 5 2022, 2:38 AM
llvm/lib/Target/AArch64/AArch64SystemOperands.td
980–981

There's a section further up in the file just for read-only registers. I recommend you move PMMIR_EL1 there.

simon_tatham updated this revision to Diff 420429.Apr 5 2022, 2:54 AM

Oh yes, so there is. Moved the def.

vhscampos accepted this revision.Apr 5 2022, 2:56 AM

LGTM.

This revision is now accepted and ready to land.Apr 5 2022, 2:56 AM
This revision was landed with ongoing or failed builds.Apr 5 2022, 3:10 AM
Closed by commit rG82bd0bd24f61: [AArch64] Make PMMIR_EL1 read-only. (authored by simon_tatham). · Explain Why
This revision was automatically updated to reflect the committed changes.
simon_tatham added a commit: rG82bd0bd24f61: [AArch64] Make PMMIR_EL1 read-only..
Harbormaster completed remote builds in B157918: Diff 420429.Apr 5 2022, 4:05 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
2 lines
test/
MC/
AArch64/
4 lines
2 lines
Disassembler/
AArch64/
2 lines

Diff 420433

llvm/lib/Target/AArch64/AArch64SystemOperands.td

Show First 20 Lines • Show All 625 Lines • ▼ Show 20 Lines
// Op0 Op1 CRn CRm Op2 // Op0 Op1 CRn CRm Op2
def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>; def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>;
def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>; def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;
def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>; def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>;
def : ROSysReg<"OSLSR_EL1", 0b10, 0b000, 0b0001, 0b0001, 0b100>; def : ROSysReg<"OSLSR_EL1", 0b10, 0b000, 0b0001, 0b0001, 0b100>;
def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>; def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>;
def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>; def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>; def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
def : ROSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>;
def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>; def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>;
def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>; def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>;
//v8.3 CCIDX - extending the CCsIDr number of sets //v8.3 CCIDX - extending the CCsIDr number of sets
def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> { def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> {
let Requires = [{ {AArch64::FeatureCCIDX} }]; let Requires = [{ {AArch64::FeatureCCIDX} }];
} }
def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>; def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>;
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def : RWSysReg<"PMOVSCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b011>; def : RWSysReg<"PMOVSCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b011>;
def : RWSysReg<"PMSELR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b101>; def : RWSysReg<"PMSELR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b101>;
def : RWSysReg<"PMCCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b000>; def : RWSysReg<"PMCCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b000>;
def : RWSysReg<"PMXEVTYPER_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b001>; def : RWSysReg<"PMXEVTYPER_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b001>;
def : RWSysReg<"PMXEVCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b010>; def : RWSysReg<"PMXEVCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b010>;
def : RWSysReg<"PMUSERENR_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b000>; def : RWSysReg<"PMUSERENR_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b000>;
def : RWSysReg<"PMINTENSET_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b001>; def : RWSysReg<"PMINTENSET_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b001>;
def : RWSysReg<"PMINTENCLR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b010>; def : RWSysReg<"PMINTENCLR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b010>;
def : RWSysReg<"PMOVSSET_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b011>; def : RWSysReg<"PMOVSSET_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b011>;
def : RWSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>;
def : RWSysReg<"MAIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b000>; def : RWSysReg<"MAIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b000>;
vhscamposUnsubmitted
Not Done
ReplyInline Actions

There's a section further up in the file just for read-only registers. I recommend you move PMMIR_EL1 there.

vhscampos: There's a section further up in the file just for read-only registers. I recommend you move…
def : RWSysReg<"MAIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b000>; def : RWSysReg<"MAIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b000>;
def : RWSysReg<"MAIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b000>; def : RWSysReg<"MAIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b000>;
def : RWSysReg<"AMAIR_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b000>; def : RWSysReg<"AMAIR_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b000>;
def : RWSysReg<"AMAIR_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b000>; def : RWSysReg<"AMAIR_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b000>;
def : RWSysReg<"AMAIR_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b000>; def : RWSysReg<"AMAIR_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b000>;
def : RWSysReg<"VBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b000>; def : RWSysReg<"VBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b000>;
def : RWSysReg<"VBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b000>; def : RWSysReg<"VBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b000>;
def : RWSysReg<"VBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b000>; def : RWSysReg<"VBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b000>;
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llvm/test/MC/AArch64/basic-a64-diagnostics.s

Show First 20 Lines • Show All 3,599 Lines • ▼ Show 20 Lines// write-only registers actually are.
msr ID_AA64AFR0_EL1, x12 msr ID_AA64AFR0_EL1, x12
msr ID_AA64AFR1_EL1, x12 msr ID_AA64AFR1_EL1, x12
msr ID_AA64ISAR0_EL1, x12 msr ID_AA64ISAR0_EL1, x12
msr ID_AA64ISAR1_EL1, x12 msr ID_AA64ISAR1_EL1, x12
msr ID_AA64MMFR0_EL1, x12 msr ID_AA64MMFR0_EL1, x12
msr ID_AA64MMFR1_EL1, x12 msr ID_AA64MMFR1_EL1, x12
msr PMCEID0_EL0, x12 msr PMCEID0_EL0, x12
msr PMCEID1_EL0, x12 msr PMCEID1_EL0, x12
msr PMMIR_EL1, x12
msr RVBAR_EL1, x12 msr RVBAR_EL1, x12
msr RVBAR_EL2, x12 msr RVBAR_EL2, x12
msr RVBAR_EL3, x12 msr RVBAR_EL3, x12
msr ISR_EL1, x12 msr ISR_EL1, x12
msr CNTPCT_EL0, x12 msr CNTPCT_EL0, x12
msr CNTVCT_EL0, x12 msr CNTVCT_EL0, x12
msr PMEVCNTR31_EL0, x12 msr PMEVCNTR31_EL0, x12
msr PMEVTYPER31_EL0, x12 msr PMEVTYPER31_EL0, x12
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// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr PMCEID0_EL0, x12 // CHECK-ERROR-NEXT: msr PMCEID0_EL0, x12
// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr PMCEID1_EL0, x12 // CHECK-ERROR-NEXT: msr PMCEID1_EL0, x12
// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr PMMIR_EL1, x12
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr RVBAR_EL1, x12 // CHECK-ERROR-NEXT: msr RVBAR_EL1, x12
// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr RVBAR_EL2, x12 // CHECK-ERROR-NEXT: msr RVBAR_EL2, x12
// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr RVBAR_EL3, x12 // CHECK-ERROR-NEXT: msr RVBAR_EL3, x12
// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
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llvm/test/MC/AArch64/basic-a64-instructions.s

Show First 20 Lines • Show All 3,828 Lines • ▼ Show 20 Lines// CHECK: tlbi vaale1, x25 // encoding: [0xf9,0x87,0x08,0xd5]
msr PMSELR_EL0, x12 msr PMSELR_EL0, x12
msr PMCCNTR_EL0, x12 msr PMCCNTR_EL0, x12
msr PMXEVTYPER_EL0, x12 msr PMXEVTYPER_EL0, x12
msr PMXEVCNTR_EL0, x12 msr PMXEVCNTR_EL0, x12
msr PMUSERENR_EL0, x12 msr PMUSERENR_EL0, x12
msr PMINTENSET_EL1, x12 msr PMINTENSET_EL1, x12
msr PMINTENCLR_EL1, x12 msr PMINTENCLR_EL1, x12
msr PMOVSSET_EL0, x12 msr PMOVSSET_EL0, x12
msr PMMIR_EL1, x12
msr MAIR_EL1, x12 msr MAIR_EL1, x12
msr MAIR_EL2, x12 msr MAIR_EL2, x12
msr MAIR_EL3, x12 msr MAIR_EL3, x12
msr AMAIR_EL1, x12 msr AMAIR_EL1, x12
msr AMAIR_EL2, x12 msr AMAIR_EL2, x12
msr AMAIR_EL3, x12 msr AMAIR_EL3, x12
msr VBAR_EL1, x12 msr VBAR_EL1, x12
msr VBAR_EL2, x12 msr VBAR_EL2, x12
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// CHECK: msr {{pmselr_el0|PMSELR_EL0}}, x12 // encoding: [0xac,0x9c,0x1b,0xd5] // CHECK: msr {{pmselr_el0|PMSELR_EL0}}, x12 // encoding: [0xac,0x9c,0x1b,0xd5]
// CHECK: msr {{pmccntr_el0|PMCCNTR_EL0}}, x12 // encoding: [0x0c,0x9d,0x1b,0xd5] // CHECK: msr {{pmccntr_el0|PMCCNTR_EL0}}, x12 // encoding: [0x0c,0x9d,0x1b,0xd5]
// CHECK: msr {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12 // encoding: [0x2c,0x9d,0x1b,0xd5] // CHECK: msr {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12 // encoding: [0x2c,0x9d,0x1b,0xd5]
// CHECK: msr {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12 // encoding: [0x4c,0x9d,0x1b,0xd5] // CHECK: msr {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12 // encoding: [0x4c,0x9d,0x1b,0xd5]
// CHECK: msr {{pmuserenr_el0|PMUSERENR_EL0}}, x12 // encoding: [0x0c,0x9e,0x1b,0xd5] // CHECK: msr {{pmuserenr_el0|PMUSERENR_EL0}}, x12 // encoding: [0x0c,0x9e,0x1b,0xd5]
// CHECK: msr {{pmintenset_el1|PMINTENSET_EL1}}, x12 // encoding: [0x2c,0x9e,0x18,0xd5] // CHECK: msr {{pmintenset_el1|PMINTENSET_EL1}}, x12 // encoding: [0x2c,0x9e,0x18,0xd5]
// CHECK: msr {{pmintenclr_el1|PMINTENCLR_EL1}}, x12 // encoding: [0x4c,0x9e,0x18,0xd5] // CHECK: msr {{pmintenclr_el1|PMINTENCLR_EL1}}, x12 // encoding: [0x4c,0x9e,0x18,0xd5]
// CHECK: msr {{pmovsset_el0|PMOVSSET_EL0}}, x12 // encoding: [0x6c,0x9e,0x1b,0xd5] // CHECK: msr {{pmovsset_el0|PMOVSSET_EL0}}, x12 // encoding: [0x6c,0x9e,0x1b,0xd5]
// CHECK: msr {{pmmir_el1|PMMIR_EL1}}, x12 // encoding: [0xcc,0x9e,0x18,0xd5]
// CHECK: msr {{mair_el1|MAIR_EL1}}, x12 // encoding: [0x0c,0xa2,0x18,0xd5] // CHECK: msr {{mair_el1|MAIR_EL1}}, x12 // encoding: [0x0c,0xa2,0x18,0xd5]
// CHECK: msr {{mair_el2|MAIR_EL2}}, x12 // encoding: [0x0c,0xa2,0x1c,0xd5] // CHECK: msr {{mair_el2|MAIR_EL2}}, x12 // encoding: [0x0c,0xa2,0x1c,0xd5]
// CHECK: msr {{mair_el3|MAIR_EL3}}, x12 // encoding: [0x0c,0xa2,0x1e,0xd5] // CHECK: msr {{mair_el3|MAIR_EL3}}, x12 // encoding: [0x0c,0xa2,0x1e,0xd5]
// CHECK: msr {{amair_el1|AMAIR_EL1}}, x12 // encoding: [0x0c,0xa3,0x18,0xd5] // CHECK: msr {{amair_el1|AMAIR_EL1}}, x12 // encoding: [0x0c,0xa3,0x18,0xd5]
// CHECK: msr {{amair_el2|AMAIR_EL2}}, x12 // encoding: [0x0c,0xa3,0x1c,0xd5] // CHECK: msr {{amair_el2|AMAIR_EL2}}, x12 // encoding: [0x0c,0xa3,0x1c,0xd5]
// CHECK: msr {{amair_el3|AMAIR_EL3}}, x12 // encoding: [0x0c,0xa3,0x1e,0xd5] // CHECK: msr {{amair_el3|AMAIR_EL3}}, x12 // encoding: [0x0c,0xa3,0x1e,0xd5]
// CHECK: msr {{vbar_el1|VBAR_EL1}}, x12 // encoding: [0x0c,0xc0,0x18,0xd5] // CHECK: msr {{vbar_el1|VBAR_EL1}}, x12 // encoding: [0x0c,0xc0,0x18,0xd5]
// CHECK: msr {{vbar_el2|VBAR_EL2}}, x12 // encoding: [0x0c,0xc0,0x1c,0xd5] // CHECK: msr {{vbar_el2|VBAR_EL2}}, x12 // encoding: [0x0c,0xc0,0x1c,0xd5]
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llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt

Show First 20 Lines • Show All 3,302 Lines • ▼ Show 20 Lines
# CHECK: msr {{pmselr_el0|PMSELR_EL0}}, x12 # CHECK: msr {{pmselr_el0|PMSELR_EL0}}, x12
# CHECK: msr {{pmccntr_el0|PMCCNTR_EL0}}, x12 # CHECK: msr {{pmccntr_el0|PMCCNTR_EL0}}, x12
# CHECK: msr {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12 # CHECK: msr {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12
# CHECK: msr {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12 # CHECK: msr {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12
# CHECK: msr {{pmuserenr_el0|PMUSERENR_EL0}}, x12 # CHECK: msr {{pmuserenr_el0|PMUSERENR_EL0}}, x12
# CHECK: msr {{pmintenset_el1|PMINTENSET_EL1}}, x12 # CHECK: msr {{pmintenset_el1|PMINTENSET_EL1}}, x12
# CHECK: msr {{pmintenclr_el1|PMINTENCLR_EL1}}, x12 # CHECK: msr {{pmintenclr_el1|PMINTENCLR_EL1}}, x12
# CHECK: msr {{pmovsset_el0|PMOVSSET_EL0}}, x12 # CHECK: msr {{pmovsset_el0|PMOVSSET_EL0}}, x12
# CHECK: msr {{pmmir_el1|PMMIR_EL1}}, x12
# CHECK: msr {{mair_el1|MAIR_EL1}}, x12 # CHECK: msr {{mair_el1|MAIR_EL1}}, x12
# CHECK: msr {{mair_el2|MAIR_EL2}}, x12 # CHECK: msr {{mair_el2|MAIR_EL2}}, x12
# CHECK: msr {{mair_el3|MAIR_EL3}}, x12 # CHECK: msr {{mair_el3|MAIR_EL3}}, x12
# CHECK: msr {{amair_el1|AMAIR_EL1}}, x12 # CHECK: msr {{amair_el1|AMAIR_EL1}}, x12
# CHECK: msr {{amair_el2|AMAIR_EL2}}, x12 # CHECK: msr {{amair_el2|AMAIR_EL2}}, x12
# CHECK: msr {{amair_el3|AMAIR_EL3}}, x12 # CHECK: msr {{amair_el3|AMAIR_EL3}}, x12
# CHECK: msr {{vbar_el1|VBAR_EL1}}, x12 # CHECK: msr {{vbar_el1|VBAR_EL1}}, x12
# CHECK: msr {{vbar_el2|VBAR_EL2}}, x12 # CHECK: msr {{vbar_el2|VBAR_EL2}}, x12
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# CHECK: mrs x9, {{pmceid1_el0|PMCEID1_EL0}} # CHECK: mrs x9, {{pmceid1_el0|PMCEID1_EL0}}
# CHECK: mrs x9, {{pmccntr_el0|PMCCNTR_EL0}} # CHECK: mrs x9, {{pmccntr_el0|PMCCNTR_EL0}}
# CHECK: mrs x9, {{pmxevtyper_el0|PMXEVTYPER_EL0}} # CHECK: mrs x9, {{pmxevtyper_el0|PMXEVTYPER_EL0}}
# CHECK: mrs x9, {{pmxevcntr_el0|PMXEVCNTR_EL0}} # CHECK: mrs x9, {{pmxevcntr_el0|PMXEVCNTR_EL0}}
# CHECK: mrs x9, {{pmuserenr_el0|PMUSERENR_EL0}} # CHECK: mrs x9, {{pmuserenr_el0|PMUSERENR_EL0}}
# CHECK: mrs x9, {{pmintenset_el1|PMINTENSET_EL1}} # CHECK: mrs x9, {{pmintenset_el1|PMINTENSET_EL1}}
# CHECK: mrs x9, {{pmintenclr_el1|PMINTENCLR_EL1}} # CHECK: mrs x9, {{pmintenclr_el1|PMINTENCLR_EL1}}
# CHECK: mrs x9, {{pmovsset_el0|PMOVSSET_EL0}} # CHECK: mrs x9, {{pmovsset_el0|PMOVSSET_EL0}}
# CHECK: mrs x9, {{pmmir_el1|PMMIR_EL1}}
# CHECK: mrs x9, {{mair_el1|MAIR_EL1}} # CHECK: mrs x9, {{mair_el1|MAIR_EL1}}
# CHECK: mrs x9, {{mair_el2|MAIR_EL2}} # CHECK: mrs x9, {{mair_el2|MAIR_EL2}}
# CHECK: mrs x9, {{mair_el3|MAIR_EL3}} # CHECK: mrs x9, {{mair_el3|MAIR_EL3}}
# CHECK: mrs x9, {{amair_el1|AMAIR_EL1}} # CHECK: mrs x9, {{amair_el1|AMAIR_EL1}}
# CHECK: mrs x9, {{amair_el2|AMAIR_EL2}} # CHECK: mrs x9, {{amair_el2|AMAIR_EL2}}
# CHECK: mrs x9, {{amair_el3|AMAIR_EL3}} # CHECK: mrs x9, {{amair_el3|AMAIR_EL3}}
# CHECK: mrs x9, {{vbar_el1|VBAR_EL1}} # CHECK: mrs x9, {{vbar_el1|VBAR_EL1}}
# CHECK: mrs x9, {{vbar_el2|VBAR_EL2}} # CHECK: mrs x9, {{vbar_el2|VBAR_EL2}}
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