[BOLT][NFC] Move isADD64rr and isADDri out of MCPlusBuilder class

[rafauler]

LGTM

bolt/include/bolt/Core/MCPlusBuilder.h

public:
 
   /// Return the width, in bytes, of the memory access performed by \p Inst, if
   /// this is a push instruction. Return zero otherwise.
   virtual int getPushSize(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return 0;
   }
 
-  virtual bool isADD64rr(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
-  }
-
   virtual bool isSUB(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return false;
   }
 
   virtual bool isLEA64r(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return false;

bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp

bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
     Inst.addOperand(MCOperand::createExpr(getTargetExprFor(
         Inst, MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx),
         *Ctx, 0)));
     return true;
   }
 
   bool isMoveMem2Reg(const MCInst &Inst) const override { return false; }
 
-  bool isADD64rr(const MCInst &Inst) const override { return false; }
-
   bool isLeave(const MCInst &Inst) const override { return false; }
 
   bool isPop(const MCInst &Inst) const override { return false; }
 
   bool isPrefix(const MCInst &Inst) const override { return false; }
 
   bool deleteREPPrefix(MCInst &Inst) const override { return false; }
 

bolt/lib/Target/X86/X86MCPlusBuilder.cpp

 unsigned getShortArithOpcode(unsigned Opcode) {
   return X86::getShortOpcodeArith(Opcode);
 }
 
 bool isMOVSX64rm32(const MCInst &Inst) {
   return Inst.getOpcode() == X86::MOVSX64rm32;
 }
 
+bool isADD64rr(const MCInst &Inst) { return Inst.getOpcode() == X86::ADD64rr; }
+
+bool isADDri(const MCInst &Inst) {
+  return Inst.getOpcode() == X86::ADD64ri32 ||
+         Inst.getOpcode() == X86::ADD64ri8;
+}
+
 class X86MCPlusBuilder : public MCPlusBuilder {
 public:
   X86MCPlusBuilder(const MCInstrAnalysis *Analysis, const MCInstrInfo *Info,
                    const MCRegisterInfo *RegInfo)
       : MCPlusBuilder(Analysis, Info, RegInfo) {}
 
   bool isBranch(const MCInst &Inst) const override {
     return Analysis->isBranch(Inst) && !isTailCall(Inst);
int getPushSize(const MCInst &Inst) const override {
     case X86::PUSHF64:
     case X86::PUSHFS64:
     case X86::PUSHGS64:
       return 8;
     }
     return 0;
   }
 
-  bool isADD64rr(const MCInst &Inst) const override {
-    return Inst.getOpcode() == X86::ADD64rr;
-  }
-
   bool isSUB(const MCInst &Inst) const override {
     return X86::isSUB(Inst.getOpcode());
   }
 
-  bool isADDri(const MCInst &Inst) const {
-    return Inst.getOpcode() == X86::ADD64ri32 ||
-           Inst.getOpcode() == X86::ADD64ri8;
-  }
-
   bool isLEA64r(const MCInst &Inst) const override {
     return Inst.getOpcode() == X86::LEA64r;
   }
 
   bool isLeave(const MCInst &Inst) const override {
     return Inst.getOpcode() == X86::LEAVE || Inst.getOpcode() == X86::LEAVE64;
   }