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Differential D123048

[AMDGPU] Ignore debug use during PreRARematerialize stage in scheduling pass
ClosedPublic

Authored by vangthao on Apr 4 2022, 9:53 AM.

Details

Reviewers
rampitec
kerbowa
vpykhtin
Commits
rG45c2371c0d31: [AMDGPU] Ignore debug use during PreRARematerialize stage in scheduling pass
Summary

Ignore all debug uses when collecting trivially rematerializable defs. This fixes an issue with difference in codegen when enabling debug info.

Diff Detail

Event Timeline

vangthao created this revision.Apr 4 2022, 9:53 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 4 2022, 9:53 AM
Herald added subscribers: hsmhsm, foad, kerbowa and 10 others. · View Herald Transcript
vangthao requested review of this revision.Apr 4 2022, 9:53 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 4 2022, 9:53 AM
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vangthao added reviewers: rampitec, kerbowa, vpykhtin.Apr 4 2022, 9:54 AM
Harbormaster completed remote builds in B157756: Diff 420220.Apr 4 2022, 10:37 AM
rampitec accepted this revision.Apr 4 2022, 10:40 AM

LGTM

This revision is now accepted and ready to land.Apr 4 2022, 10:40 AM
This revision was landed with ongoing or failed builds.Apr 4 2022, 11:16 AM
Closed by commit rG45c2371c0d31: [AMDGPU] Ignore debug use during PreRARematerialize stage in scheduling pass (authored by vangthao). · Explain Why
This revision was automatically updated to reflect the committed changes.
vangthao added a commit: rG45c2371c0d31: [AMDGPU] Ignore debug use during PreRARematerialize stage in scheduling pass.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
4 lines
test/
CodeGen/
AMDGPU/
110 lines

Diff 420252

llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

Show First 20 Lines • Show All 725 Lines • ▼ Show 20 Linesvoid GCNScheduleDAGMILive::collectRematerializableInstructions(
const GCNRPTracker::LiveRegSet &HighRPLiveIns = LiveIns[HighRPIdx]; const GCNRPTracker::LiveRegSet &HighRPLiveIns = LiveIns[HighRPIdx];
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) { for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
Register Reg = Register::index2VirtReg(I); Register Reg = Register::index2VirtReg(I);
if (!LIS->hasInterval(Reg)) if (!LIS->hasInterval(Reg))
continue; continue;
// TODO: Handle AGPR and SGPR rematerialization // TODO: Handle AGPR and SGPR rematerialization
if (!SRI->isVGPRClass(MRI.getRegClass(Reg)) || !MRI.hasOneDef(Reg) || if (!SRI->isVGPRClass(MRI.getRegClass(Reg)) || !MRI.hasOneDef(Reg) ||
!MRI.hasOneUse(Reg)) !MRI.hasOneNonDBGUse(Reg))
continue; continue;
// We are only collecting defs that are live-through or defined in another // We are only collecting defs that are live-through or defined in another
// block and used inside this region. This means that the register must be // block and used inside this region. This means that the register must be
// in the live-in set for this region, else skip this def. // in the live-in set for this region, else skip this def.
if (HighRPLiveIns.find(Reg) == HighRPLiveIns.end()) if (HighRPLiveIns.find(Reg) == HighRPLiveIns.end())
continue; continue;
MachineInstr *Def = MRI.getOneDef(Reg)->getParent(); MachineInstr *Def = MRI.getOneDef(Reg)->getParent();
if (!Def || Def->getOperand(0).getSubReg() != 0 || if (!Def || Def->getOperand(0).getSubReg() != 0 ||
!isTriviallyReMaterializable(*Def, AA)) !isTriviallyReMaterializable(*Def, AA))
continue; continue;
MachineInstr *UseI = &*MRI.use_instr_begin(Reg); MachineInstr *UseI = &*MRI.use_instr_nodbg_begin(Reg);
if (Def->getParent() == UseI->getParent()) if (Def->getParent() == UseI->getParent())
continue; continue;
RematerializableInsts.push_back(std::make_pair(Def, UseI)); RematerializableInsts.push_back(std::make_pair(Def, UseI));
} }
} }
bool GCNScheduleDAGMILive::sinkTriviallyRematInsts(const GCNSubtarget &ST, bool GCNScheduleDAGMILive::sinkTriviallyRematInsts(const GCNSubtarget &ST,
▲ Show 20 Lines • Show All 174 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,834 Lines • ▼ Show 20 Lines ; predcessors: %bb.1
S_NOP 0, implicit %12, implicit %13 S_NOP 0, implicit %12, implicit %13
S_NOP 0, implicit %14, implicit %15 S_NOP 0, implicit %14, implicit %15
S_NOP 0, implicit %16, implicit %17 S_NOP 0, implicit %16, implicit %17
S_NOP 0, implicit %18, implicit %19 S_NOP 0, implicit %18, implicit %19
S_NOP 0, implicit %20, implicit %21 S_NOP 0, implicit %20, implicit %21
S_NOP 0, implicit %22 S_NOP 0, implicit %22
S_ENDPGM 0 S_ENDPGM 0
... ...
---
name: test_occ_9_sink_ignore_dbg_value_use
tracksRegLiveness: true
machineFunctionInfo:
isEntryFunction: true
body: |
; GFX908-LABEL: name: test_occ_9_sink_ignore_dbg_value_use
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: %0:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %1:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %2:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %3:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %4:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %5:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %6:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %7:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %8:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %9:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %10:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %11:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %12:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 12, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %13:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 13, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %14:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 14, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %15:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 15, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %16:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %17:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 17, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %18:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 18, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %19:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %20:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %21:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: %22:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.1:
; GFX908-NEXT: successors: %bb.2(0x80000000)
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: %24:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 24, implicit $exec, implicit $mode, implicit-def $m0
; GFX908-NEXT: S_NOP 0, implicit %24
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.2:
; GFX908-NEXT: DBG_VALUE %23, 0, 0
; GFX908-NEXT: %23:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode
; GFX908-NEXT: S_NOP 0, implicit %23
; GFX908-NEXT: S_NOP 0, implicit %0, implicit %1
; GFX908-NEXT: S_NOP 0, implicit %2, implicit %3
; GFX908-NEXT: S_NOP 0, implicit %4, implicit %5
; GFX908-NEXT: S_NOP 0, implicit %6, implicit %7
; GFX908-NEXT: S_NOP 0, implicit %8, implicit %9
; GFX908-NEXT: S_NOP 0, implicit %10, implicit %11
; GFX908-NEXT: S_NOP 0, implicit %12, implicit %13
; GFX908-NEXT: S_NOP 0, implicit %14, implicit %15
; GFX908-NEXT: S_NOP 0, implicit %16, implicit %17
; GFX908-NEXT: S_NOP 0, implicit %18, implicit %19
; GFX908-NEXT: S_NOP 0, implicit %20, implicit %21
; GFX908-NEXT: S_NOP 0, implicit %22
; GFX908-NEXT: S_ENDPGM 0
bb.0:
successors: %bb.1
%0:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode, implicit-def $m0
%1:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode, implicit-def $m0
%2:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode, implicit-def $m0
%3:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode, implicit-def $m0
%4:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode, implicit-def $m0
%5:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode, implicit-def $m0
%6:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode, implicit-def $m0
%7:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0
%8:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0
%9:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode, implicit-def $m0
%10:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode, implicit-def $m0
%11:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode, implicit-def $m0
%12:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 12, implicit $exec, implicit $mode, implicit-def $m0
%13:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 13, implicit $exec, implicit $mode, implicit-def $m0
%14:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 14, implicit $exec, implicit $mode, implicit-def $m0
%15:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 15, implicit $exec, implicit $mode, implicit-def $m0
%16:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode, implicit-def $m0
%17:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 17, implicit $exec, implicit $mode, implicit-def $m0
%18:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 18, implicit $exec, implicit $mode, implicit-def $m0
%19:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode, implicit-def $m0
%20:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode, implicit-def $m0
%21:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode, implicit-def $m0
%22:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode, implicit-def $m0
%23:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode
bb.1:
; predecessors: %bb.0
successors: %bb.2
%24:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 24, implicit $exec, implicit $mode, implicit-def $m0
S_NOP 0, implicit %24
bb.2:
; predcessors: %bb.1
DBG_VALUE %23, 0, 0
S_NOP 0, implicit %23
S_NOP 0, implicit %0, implicit %1
S_NOP 0, implicit %2, implicit %3
S_NOP 0, implicit %4, implicit %5
S_NOP 0, implicit %6, implicit %7
S_NOP 0, implicit %8, implicit %9
S_NOP 0, implicit %10, implicit %11
S_NOP 0, implicit %12, implicit %13
S_NOP 0, implicit %14, implicit %15
S_NOP 0, implicit %16, implicit %17
S_NOP 0, implicit %18, implicit %19
S_NOP 0, implicit %20, implicit %21
S_NOP 0, implicit %22
S_ENDPGM 0
...