Implement ACLE 2.0 macros of chapters 6.4 and 6.5 for [ARM] and [Aarch64] targets

[labrinea]

Summary

Implementation and testing of ACLE 2.0 macros, for details see the above document:
ACLE 2.0

[rengolin]

I'm surprised you decided to rearrange the output of the macros. It makes reviewing a lot harder. Is there some special reason to have that in any specific order?

lib/Basic/Targets.cpp

4624

Is it truly impossible for CPUAttr to be empty? Or just coincidental given our tests?

[labrinea]

Reordered macro definitions to make review easier.

[labrinea]

lib/Basic/Targets.cpp

4757

According to the ACLE document, current AArch32 NEON implementations do not support double-precision floating-point even when it is present in VFP.

[olista01]

lib/Basic/Targets.cpp

4685–4686

The __fp16 type is accepted even if it is not supported by the hardware (library calls are emitted instead), so this can be defined unconditionally. I'm currently working on D12148, which also sets this and _ARM_FP16_ARGS.

[labrinea]

lib/Basic/Targets.cpp

4685–4686

Good point. As far as I know there is hardware support for having _fp16 type values as function arguments but not as return values (yet). If so, should _ARM_FP16_ARGS macro be defined or not? (ACLE 2.0: "_ARM_FP16_ARGS is defined to 1 if __fp16 can be used as an argument and result.")

[olista01]

lib/Basic/Targets.cpp

4685–4686

Support for __fp16 args/returns should be independent of hardware support (at least in clang/llvm), as we can always lower to library function calls.

For AArch32: There is currently no support for __fp16 arguments or returns, but D12148 adds both of these, and sets the predefine.

For AArch64: There has been support for __fp16 args and returns for about a year, but we only recently turned the predefine on (D12240/rL245833).

[labrinea]

lib/Basic/Targets.cpp

4685–4686

Good. I will update this patch accordingly.

[labrinea]

_ARM_FP16_FORMAT_IEEE and _ARM_FP16_ARGS should be defined unconditionally. When hardware does not support it library calls are emitted.

[labrinea]

Could I have some feedback please?

[rengolin]

Hi Alexandros,

Sorry, I was on holidays. Apart from my comment, everything else looks good.

cheers,
--renato

lib/Basic/Targets.cpp

4788

Isn't there a combination where you'll emit this macro twice?

[rengolin]

Also, the target parser code has changed, please make sure it still works with the new version.

[labrinea]

lib/Basic/Targets.cpp

4788

This could be addressed as:

bool hasDSP = false;
if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUAttr  == "7EM")) {
  Builder.defineMacro("__ARM_FEATURE_DSP", "1");
  hasDSP = true;
}

bool hasSAT = false;
if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
  Builder.defineMacro("__ARM_FEATURE_SAT", "1");
  hasSAT = true;
}

if (hasDSP || hasSAT)
  Builder.defineMacro("__ARM_FEATURE_QBIT", "1");

[rengolin]

lib/Basic/Targets.cpp

4788

Yup, that looks good.

[rengolin]

With the changes you proposed, LGTM. Thanks!

[labrinea]

This comment was removed by labrinea.

[labrinea]

committed as r246768

lib/Basic/Targets.cpp

class ARMTargetInfo : public TargetInfo {
   unsigned HWDiv : 2;
 
   // Initialized via features.
   unsigned SoftFloat : 1;
   unsigned SoftFloatABI : 1;
 
   unsigned CRC : 1;
   unsigned Crypto : 1;
+  unsigned Unaligned : 1;
+
+  enum {
+    LDREX_B = (1 << 0), /// byte (8-bit)
+    LDREX_H = (1 << 1), /// half (16-bit)
+    LDREX_W = (1 << 2), /// word (32-bit)
+    LDREX_D = (1 << 3), /// double (64-bit)
+  };
+
+  uint32_t LDREX;
 
   // ACLE 6.5.1 Hardware floating point
   enum {
     HW_FP_HP = (1 << 1), /// half (16-bit)
     HW_FP_SP = (1 << 2), /// single (32-bit)
     HW_FP_DP = (1 << 3), /// double (64-bit)
   };
   uint32_t HW_FP;
StringRef getCPUProfile() const {
     default:
       return "";
     }
   }
 
 public:
   ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
       : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
-        IsAAPCS(true), HW_FP(0) {
+        IsAAPCS(true), LDREX(0), HW_FP(0) {
     BigEndian = IsBigEndian;
 
     switch (getTriple().getOS()) {
     case llvm::Triple::NetBSD:
       PtrDiffType = SignedLong;
       break;
     default:
       PtrDiffType = SignedInt;
else if (CPU == "cortex-a5") {
       Features["crypto"] = true;
     } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || ArchVersion == 8) {
       Features["hwdiv"] = true;
       Features["hwdiv-arm"] = true;
     } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" ||
                CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") {
       Features["hwdiv"] = true;
     }
+
+    if (ArchVersion < 6  || 
+       (ArchVersion == 6 && ArchProfile == llvm::ARM::PK_M))
+      Features["strict-align"] = true;
   }
 
   bool handleTargetFeatures(std::vector<std::string> &Features,
                             DiagnosticsEngine &Diags) override {
     FPU = 0;
     CRC = 0;
     Crypto = 0;
+    Unaligned = 1;
     SoftFloat = SoftFloatABI = false;
     HWDiv = 0;
 
     // This does not diagnose illegal cases like having both
     // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
     uint32_t HW_FP_remove = 0;
     for (const auto &Feature : Features) {
       if (Feature == "+soft-float") {
for (const auto &Feature : Features) {
       } else if (Feature == "+hwdiv-arm") {
         HWDiv |= HWDivARM;
       } else if (Feature == "+crc") {
         CRC = 1;
       } else if (Feature == "+crypto") {
         Crypto = 1;
       } else if (Feature == "+fp-only-sp") {
         HW_FP_remove |= HW_FP_DP | HW_FP_HP;
+      } else if (Feature == "+strict-align") {
+        Unaligned = 0;
+      } else if (Feature == "+fp16") {
+        HW_FP |= HW_FP_HP;
       }
     }
     HW_FP &= ~HW_FP_remove;
 
+    switch (ArchVersion) {
+    case 6:
+      if (ArchProfile == llvm::ARM::PK_M)
+        LDREX = 0;
+      else if (ArchKind == llvm::ARM::AK_ARMV6K)
+        LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
+      else
+        LDREX = LDREX_W;
+      break;
+    case 7:
+      if (ArchProfile == llvm::ARM::PK_M)
+        LDREX = LDREX_W | LDREX_H | LDREX_B ;
+      else
+        LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
+      break;
+    case 8:
+      LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
+    }
+
     if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
       Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
       return false;
     }
 
     if (FPMath == FP_Neon)
       Features.push_back("+neonfp");
     else if (FPMath == FP_VFP)
void getTargetDefines(const LangOptions &Opts,
     // Target identification.
     Builder.defineMacro("__arm");
     Builder.defineMacro("__arm__");
 
     // Target properties.
     Builder.defineMacro("__REGISTER_PREFIX__", "");
     if (!CPUAttr.empty())
       Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
 
     // ACLE 6.4.1 ARM/Thumb instruction set architecture
     // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
     Builder.defineMacro("__ARM_ARCH", llvm::utostr(ArchVersion));
+
     if (ArchVersion >= 8) {
+      // ACLE 6.5.7 Crypto Extension
+      if (Crypto)
+        Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
+      // ACLE 6.5.8 CRC32 Extension
+      if (CRC)
+        Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
+      // ACLE 6.5.10 Numeric Maximum and Minimum
       Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
+      // ACLE 6.5.9 Directed Rounding
       Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
     }
 
     // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
     // is not defined for the M-profile.
     // NOTE that the deffault profile is assumed to be 'A'
     if (CPUProfile.empty() || CPUProfile != "M")
       Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
void getTargetDefines(const LangOptions &Opts,
     Builder.defineMacro("__ARM_32BIT_STATE", "1");
 
     // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
 
     // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
     if (!CPUProfile.empty())
       Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
 
+    // ACLE 6.4.3 Unaligned access supported in hardware
+    if (Unaligned) 
+      Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
+ 
+    // ACLE 6.4.4 LDREX/STREX
+    if (LDREX)
+      Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
+
+    // ACLE 6.4.5 CLZ
+    if (ArchVersion == 5 || 
+       (ArchVersion == 6 && CPUProfile != "M") || 
+        ArchVersion >  6) 
+      Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
+
     // ACLE 6.5.1 Hardware Floating Point
     if (HW_FP)
       Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
 
+    // ACLE 6.5.2 Half-precision (16-bit) floating-point format
+    if (HW_FP & HW_FP_HP)
+      Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
+
+    // ACLE 6.5.3 Fused multiply-accumulate (FMA)
+    if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM"))
+      Builder.defineMacro("__ARM_FEATURE_FMA", "1");
+
     // ACLE predefines.
     Builder.defineMacro("__ARM_ACLE", "200");
 
     // Subtarget options.
 
     // FIXME: It's more complicated than this and we don't really support
     // interworking.
     // Windows on ARM does not "support" interworking
if (CPU == "xscale")
       Builder.defineMacro("__XSCALE__");
 
     if (isThumb()) {
       Builder.defineMacro("__THUMBEL__");
       Builder.defineMacro("__thumb__");
       if (supportsThumb2())
         Builder.defineMacro("__thumb2__");
     }
-    if (((HWDiv & HWDivThumb) && isThumb()) || ((HWDiv & HWDivARM) && !isThumb()))
+
+    // ACLE 6.4.9 32-bit SIMD instructions
+    if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
+      Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
+
+    // ACLE 6.4.10 Hardware Integer Divide
+    if (((HWDiv & HWDivThumb) && isThumb()) || ((HWDiv & HWDivARM) && !isThumb())) {
+      Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 
       Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
+    }
 
     // Note, this is always on in gcc, even though it doesn't make sense.
     Builder.defineMacro("__APCS_32__");
 
     if (FPUModeIsVFP((FPUMode) FPU)) {
       Builder.defineMacro("__VFP_FP__");
       if (FPU & VFP2FPU)
         Builder.defineMacro("__ARM_VFPV2__");
       if (FPU & VFP3FPU)
         Builder.defineMacro("__ARM_VFPV3__");
       if (FPU & VFP4FPU)
         Builder.defineMacro("__ARM_VFPV4__");
     }
 
     // This only gets set when Neon instructions are actually available, unlike
     // the VFP define, hence the soft float and arch check. This is subtly
     // different from gcc, we follow the intent which was that it should be set
     // when Neon instructions are actually available.
     if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
-      Builder.defineMacro("__ARM_NEON");
+      Builder.defineMacro("__ARM_NEON", "1");
       Builder.defineMacro("__ARM_NEON__");
+      Builder.defineMacro("__ARM_NEON_FP", "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
     }
 
     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
                         Opts.ShortWChar ? "2" : "4");
 
     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
                         Opts.ShortEnums ? "1" : "4");
 
-    if (CRC)
-      Builder.defineMacro("__ARM_FEATURE_CRC32");
-
-    if (Crypto)
-      Builder.defineMacro("__ARM_FEATURE_CRYPTO");
-
     if (ArchVersion >= 6 && CPUAttr != "6M") {
       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
     }
 
+    // ACLE 6.4.6 Q (saturation) flag, 
+    // ACLE 6.4.7 DSP instructions
     bool is5EOrAbove = (ArchVersion >= 6 ||
                        (ArchVersion == 5 && CPUAttr.count('E')));
     // FIXME: We are not getting all 32-bit ARM architectures
     bool is32Bit = (!isThumb() || supportsThumb2());
-    if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUAttr  == "7EM"))
-      Builder.defineMacro("__ARM_FEATURE_DSP");
+    if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUAttr  == "7EM")) {
+      Builder.defineMacro("__ARM_FEATURE_DSP", "1");
+      Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
+    }
+
+    // ACLE 6.4.6 Q (saturation) flag, 
+    // ACLE 6.4.8 Saturation instructions
+    if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
+      Builder.defineMacro("__ARM_FEATURE_SAT", "1");
+      Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
+    }
   }
 
   void getTargetBuiltins(const Builtin::Info *&Records,
                          unsigned &NumRecords) const override {
     Records = BuiltinInfo;
     NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
   }
   bool isCLZForZeroUndef() const override { return false; }
class AArch64TargetInfo : public TargetInfo {
   enum FPUModeEnum {
     FPUMode,
     NeonMode
   };
 
   unsigned FPU;
   unsigned CRC;
   unsigned Crypto;
+  unsigned Unaligned;
 
   static const Builtin::Info BuiltinInfo[];
 
   std::string ABI;
 
 public:
   AArch64TargetInfo(const llvm::Triple &Triple)
       : TargetInfo(Triple), ABI("aapcs") {
void getTargetDefines(const LangOptions &Opts,
 
     Builder.defineMacro("__ARM_64BIT_STATE");
     Builder.defineMacro("__ARM_PCS_AAPCS64");
     Builder.defineMacro("__ARM_ARCH_ISA_A64");
 
     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
     Builder.defineMacro("__ARM_FEATURE_CLZ");
     Builder.defineMacro("__ARM_FEATURE_FMA");
-    Builder.defineMacro("__ARM_FEATURE_DIV");
+    Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
     Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
     Builder.defineMacro("__ARM_FEATURE_DIV");  // For backwards compatibility
     Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
     Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
 
     Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
 
     // 0xe implies support for half, single and double precision operations.
-    Builder.defineMacro("__ARM_FP", "0xe");
+    Builder.defineMacro("__ARM_FP", "0xE");
 
     // PCS specifies this for SysV variants, which is all we support. Other ABIs
     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
 
     if (Opts.FastMath || Opts.FiniteMathOnly)
       Builder.defineMacro("__ARM_FP_FAST");
 
     if (Opts.C99 && !Opts.Freestanding)
       Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
 
     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
 
     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
                         Opts.ShortEnums ? "1" : "4");
 
     if (FPU == NeonMode) {
       Builder.defineMacro("__ARM_NEON");
       // 64-bit NEON supports half, single and double precision operations.
-      Builder.defineMacro("__ARM_NEON_FP", "0xe");
+      Builder.defineMacro("__ARM_NEON_FP", "0xE");
     }
 
     if (CRC)
       Builder.defineMacro("__ARM_FEATURE_CRC32");
 
     if (Crypto)
       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
 
+    if (Unaligned)
+      Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
+
     // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
   }
 
   void getTargetBuiltins(const Builtin::Info *&Records,
return Feature == "aarch64" ||
       (Feature == "neon" && FPU == NeonMode);
   }
 
   bool handleTargetFeatures(std::vector<std::string> &Features,
                             DiagnosticsEngine &Diags) override {
     FPU = FPUMode;
     CRC = 0;
     Crypto = 0;
+    Unaligned = 1;
+
     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
       if (Features[i] == "+neon")
         FPU = NeonMode;
       if (Features[i] == "+crc")
         CRC = 1;
       if (Features[i] == "+crypto")
         Crypto = 1;
+      if (Features[i] == "+strict-align")
+        Unaligned = 0;
     }
 
     setDataLayoutString();
 
     return true;
   }
 
   bool isCLZForZeroUndef() const override { return false; }

test/Preprocessor/aarch64-target-features.c

 // RUN: %clang -target aarch64-none-linux-gnu -x c -E -dM %s -o - | FileCheck %s
 // RUN: %clang -target arm64-none-linux-gnu -x c -E -dM %s -o - | FileCheck %s
 
 // CHECK: __AARCH64EL__ 1
 // CHECK: __ARM_64BIT_STATE 1
+// CHECK-NOT: __ARM_32BIT_STATE
 // CHECK: __ARM_ACLE 200
 // CHECK: __ARM_ALIGN_MAX_STACK_PWR 4
 // CHECK: __ARM_ARCH 8
 // CHECK: __ARM_ARCH_ISA_A64 1
+// CHECK-NOT: __ARM_ARCH_ISA_ARM
+// CHECK-NOT: __ARM_ARCH_ISA_THUMB
+// CHECK-NOT: __ARM_FEATURE_QBIT
+// CHECK-NOT: __ARM_FEATURE_DSP
+// CHECK-NOT: __ARM_FEATURE_SAT
+// CHECK-NOT: __ARM_FEATURE_SIMD32
 // CHECK: __ARM_ARCH_PROFILE 'A'
 // CHECK-NOT: __ARM_FEATURE_BIG_ENDIAN
 // CHECK: __ARM_FEATURE_CLZ 1
 // CHECK-NOT: __ARM_FEATURE_CRC32 1
 // CHECK-NOT: __ARM_FEATURE_CRYPTO 1
 // CHECK: __ARM_FEATURE_DIRECTED_ROUNDING 1
 // CHECK: __ARM_FEATURE_DIV 1
 // CHECK: __ARM_FEATURE_FMA 1
 // CHECK: __ARM_FEATURE_IDIV 1
+// CHECK: __ARM_FEATURE_LDREX 0xF
 // CHECK: __ARM_FEATURE_NUMERIC_MAXMIN 1
 // CHECK: __ARM_FEATURE_UNALIGNED 1
-// CHECK: __ARM_FP 0xe
+// CHECK: __ARM_FP 0xE
 // CHECK: __ARM_FP16_FORMAT_IEEE 1
 // CHECK-NOT: __ARM_FP_FAST 1
 // CHECK: __ARM_FP_FENV_ROUNDING 1
 // CHECK: __ARM_NEON 1
-// CHECK: __ARM_NEON_FP 0xe
+// CHECK: __ARM_NEON_FP 0xE
 // CHECK: __ARM_PCS_AAPCS64 1
 // CHECK-NOT: __ARM_SIZEOF_MINIMAL_ENUM 1
 // CHECK-NOT: __ARM_SIZEOF_WCHAR_T 2
 
+// RUN: %clang -target aarch64_be-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-BIGENDIAN
+
+// CHECK-BIGENDIAN: __ARM_BIG_ENDIAN 1
+
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+crypto -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-CRYPTO %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+crypto -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-CRYPTO %s
 // CHECK-CRYPTO: __ARM_FEATURE_CRYPTO 1
 
 // RUN: %clang -target aarch64-none-linux-gnu -mcrc -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-CRC32 %s
 // RUN: %clang -target arm64-none-linux-gnu -mcrc -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-CRC32 %s
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+crc -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-CRC32 %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+crc -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-CRC32 %s

 
 // RUN: %clang -target aarch64-none-linux-gnu -fshort-enums -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SHORTENUMS %s
 // RUN: %clang -target arm64-none-linux-gnu -fshort-enums -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SHORTENUMS %s
 // CHECK-SHORTENUMS: __ARM_SIZEOF_MINIMAL_ENUM 1
 
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+simd -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-NEON %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+simd -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-NEON %s
 // CHECK-NEON: __ARM_NEON 1
-// CHECK-NEON: __ARM_NEON_FP 0xe
+// CHECK-NEON: __ARM_NEON_FP 0xE
 
 // RUN: %clang -target aarch64 -march=arm64 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-ARCH-NOT-ACCEPT %s
 // RUN: %clang -target aarch64 -march=aarch64 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-ARCH-NOT-ACCEPT %s
 // CHECK-ARCH-NOT-ACCEPT: error: the clang compiler does not support
 
 // RUN: %clang -target aarch64 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-GENERIC %s
 // RUN: %clang -target aarch64 -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-GENERIC %s
 // CHECK-GENERIC: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon"

test/Preprocessor/arm-acle-6.4.c

-// RUN: %clang -target arm-eabi -mcpu=cortex-m0 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-CORTEX-M0
+// RUN: %clang -target arm-eabi -x c -E -dM %s -o - | FileCheck %s
+// RUN: %clang -target thumb-eabi -x c -E -dM %s -o - | FileCheck %s
 
-// CHECK-CORTEX-M0: __ARM_32BIT_STATE 1
-// CHECK-CORTEX-M0: __ARM_ARCH 6
-// CHECK-CORTEX-M0-NOT: __ARM_ARCH_ISA_ARM
-// CHECK-CORTEX-M0: __ARM_ARCH_ISA_THUMB 1
-// CHECK-CORTEX-M0: __ARM_ARCH_PROFILE 'M'
-// CHECK-CORTEX-M0-NOT: __ARM_FEATURE_NUMERIC_MAXMIN
-// CHECK-CORTEX-M0-NOT: __ARM_FEATURE_DIRECTED_ROUNDING
-
-// RUN: %clang -target arm-eabi -mcpu=arm810 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-ARM810
-
-// CHECK-ARM810: __ARM_32BIT_STATE 1
-// CHECK-ARM810: __ARM_ARCH 4
-// CHECK-ARM810: __ARM_ARCH_ISA_ARM 1
-// CHECK-ARM810-NOT: __ARM_ARCH_ISA_THUMB
-// CHECK-ARM810-NOT: __ARM_ARCH_PROFILE
-// CHECK-ARM810-NOT: __ARM_FEATURE_NUMERIC_MAXMIN
-// CHECK-ARM810-NOT: __ARM_FEATURE_DIRECTED_ROUNDING
-
-// RUN: %clang -target arm-eabi -mcpu=arm7tdmi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-ARM7TDMI
-
-// CHECK-ARM7TDMI: __ARM_32BIT_STATE 1
-// CHECK-ARM7TDMI: __ARM_ARCH 4
-// CHECK-ARM7TDMI: __ARM_ARCH_ISA_ARM 1
-// CHECK-ARM7TDMI: __ARM_ARCH_ISA_THUMB 1
-// CHECK-ARM7TDMI-NOT: __ARM_ARCH_PROFILE
-
-// RUN: %clang -target arm-eabi -mcpu=cortex-a7 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-CORTEX-A7
-
-// CHECK-CORTEX-A7: __ARM_32BIT_STATE 1
-// CHECK-CORTEX-A7: __ARM_ARCH 7
-// CHECK-CORTEX-A7: __ARM_ARCH_ISA_ARM 1
-// CHECK-CORTEX-A7: __ARM_ARCH_ISA_THUMB 2
-// CHECK-CORTEX-A7: __ARM_ARCH_PROFILE 'A'
-// CHECK-CORTEX-A7-NOT: __ARM_FEATURE_NUMERIC_MAXMIN
-// CHECK-CORTEX-A7-NOT: __ARM_FEATURE_DIRECTED_ROUNDING
-
-// RUN: %clang -target arm-eabi -mcpu=cortex-r4 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-CORTEX-R4
-
-// CHECK-CORTEX-R4: __ARM_32BIT_STATE 1
-// CHECK-CORTEX-R4: __ARM_ARCH 7
-// CHECK-CORTEX-R4: __ARM_ARCH_ISA_ARM 1
-// CHECK-CORTEX-R4: __ARM_ARCH_ISA_THUMB 2
-// CHECK-CORTEX-R4: __ARM_ARCH_PROFILE 'R'
+// CHECK-NOT: __ARM_64BIT_STATE
+// CHECK-NOT: __ARM_ARCH_ISA_A64
+// CHECK-NOT: __ARM_BIG_ENDIAN
+// CHECK:     __ARM_32BIT_STATE 1
+// CHECK:     __ARM_ACLE 200
+
+// RUN: %clang -target armeb-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-BIGENDIAN
+// RUN: %clang -target thumbeb-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-BIGENDIAN
+
+// CHECK-BIGENDIAN: __ARM_BIG_ENDIAN 1
+
+// RUN: %clang -target armv7-none-linux-eabi -mno-unaligned-access -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-UNALIGNED
+
+// CHECK-UNALIGNED-NOT: __ARM_FEATURE_UNALIGNED
+
+// RUN: %clang -target arm-none-linux-eabi -march=armv4 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V4
+
+// CHECK-V4-NOT: __ARM_ARCH_ISA_THUMB
+// CHECK-V4-NOT: __ARM_ARCH_PROFILE
+// CHECK-V4-NOT: __ARM_FEATURE_CLZ
+// CHECK-V4-NOT: __ARM_FEATURE_LDREX
+// CHECK-V4-NOT: __ARM_FEATURE_UNALIGNED
+// CHECK-V4-NOT: __ARM_FEATURE_DSP
+// CHECK-V4-NOT: __ARM_FEATURE_SAT
+// CHECK-V4-NOT: __ARM_FEATURE_QBIT
+// CHECK-V4-NOT: __ARM_FEATURE_SIMD32
+// CHECK-V4-NOT: __ARM_FEATURE_IDIV
+// CHECK-V4:     __ARM_ARCH 4
+// CHECK-V4:     __ARM_ARCH_ISA_ARM 1
+
+// RUN: %clang -target arm-none-linux-eabi -march=armv4t -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V4T
+
+// CHECK-V4T: __ARM_ARCH_ISA_THUMB 1
+
+// RUN: %clang -target arm-none-linux-eabi -march=armv5t -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V5
+
+// CHECK-V5-NOT: __ARM_ARCH_PROFILE
+// CHECK-V5-NOT: __ARM_FEATURE_LDREX
+// CHECK-V5-NOT: __ARM_FEATURE_UNALIGNED
+// CHECK-V5-NOT: __ARM_FEATURE_DSP
+// CHECK-V5-NOT: __ARM_FEATURE_SAT
+// CHECK-V5-NOT: __ARM_FEATURE_QBIT
+// CHECK-V5-NOT: __ARM_FEATURE_SIMD32
+// CHECK-V5-NOT: __ARM_FEATURE_IDIV
+// CHECK-V5:     __ARM_ARCH 5
+// CHECK-V5:     __ARM_ARCH_ISA_ARM 1
+// CHECK-V5:     __ARM_ARCH_ISA_THUMB 1
+// CHECK-V5:     __ARM_FEATURE_CLZ 1
+
+// RUN: %clang -target arm-none-linux-eabi -march=armv5te -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V5E
+
+// CHECK-V5E: __ARM_FEATURE_DSP 1
+// CHECK-V5E: __ARM_FEATURE_QBIT 1
+
+// RUN: %clang -target armv6-none-netbsd-eabi -mcpu=arm1136jf-s -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V6
+
+// CHECK-V6-NOT: __ARM_ARCH_PROFILE
+// CHECK-V6-NOT: __ARM_FEATURE_IDIV
+// CHECK-V6:     __ARM_ARCH 6
+// CHECK-V6:     __ARM_ARCH_ISA_ARM 1
+// CHECK-V6:     __ARM_ARCH_ISA_THUMB 1
+// CHECK-V6:     __ARM_FEATURE_CLZ 1
+// CHECK-V6:     __ARM_FEATURE_DSP 1
+// CHECK-V6:     __ARM_FEATURE_LDREX 0x4
+// CHECK-V6:     __ARM_FEATURE_QBIT 1
+// CHECK-V6:     __ARM_FEATURE_SAT 1
+// CHECK-V6:     __ARM_FEATURE_SIMD32 1
+// CHECK-V6:     __ARM_FEATURE_UNALIGNED 1
+
+// RUN: %clang -target arm-none-linux-eabi -march=armv6m -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V6M
+
+// CHECK-V6M-NOT: __ARM_ARCH_ISA_ARM
+// CHECK-V6M-NOT: __ARM_FEATURE_CLZ
+// CHECK-V6M-NOT: __ARM_FEATURE_LDREX
+// CHECK-V6M-NOT: __ARM_FEATURE_UNALIGNED
+// CHECK-V6M-NOT: __ARM_FEATURE_DSP
+// CHECK-V6M-NOT: __ARM_FEATURE_QBIT
+// CHECK-V6M-NOT: __ARM_FEATURE_SAT
+// CHECK-V6M-NOT: __ARM_FEATURE_SIMD32
+// CHECK-V6M-NOT: __ARM_FEATURE_IDIV
+// CHECK-V6M:     __ARM_ARCH 6
+// CHECK-V6M:     __ARM_ARCH_ISA_THUMB 1
+// CHECK-V6M:     __ARM_ARCH_PROFILE 'M'
+
+// RUN: %clang -target arm-none-linux-eabi -march=armv6t2 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V6T2
+
+// CHECK-V6T2: __ARM_ARCH_ISA_THUMB 2
+
+// RUN: %clang -target arm-none-linux-eabi -march=armv6k -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V6K
+ 
+// CHECK-V6K: __ARM_FEATURE_LDREX 0xF
+
+// RUN: %clang -target arm-none-linux-eabi -march=armv7-a -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V7A
+
+// CHECK-V7A: __ARM_ARCH 7
+// CHECK-V7A: __ARM_ARCH_ISA_ARM 1
+// CHECK-V7A: __ARM_ARCH_ISA_THUMB 2
+// CHECK-V7A: __ARM_ARCH_PROFILE 'A'
+// CHECK-V7A: __ARM_FEATURE_CLZ 1
+// CHECK-V7A: __ARM_FEATURE_DSP 1
+// CHECK-V7A: __ARM_FEATURE_LDREX 0xF
+// CHECK-V7A: __ARM_FEATURE_QBIT 1
+// CHECK-V7A: __ARM_FEATURE_SAT 1
+// CHECK-V7A: __ARM_FEATURE_SIMD32 1
+// CHECK-V7A: __ARM_FEATURE_UNALIGNED 1
+
+// RUN: %clang -target arm-none-linux-eabi -mcpu=cortex-a7 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V7A-IDIV
+// RUN: %clang -target arm-none-linux-eabi -mcpu=cortex-a12 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V7A-IDIV
+// RUN: %clang -target arm-none-linux-eabi -mcpu=cortex-a15 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V7A-IDIV
+// RUN: %clang -target arm-none-linux-eabi -mcpu=cortex-a17 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V7A-IDIV
+
+// CHECK-V7A-IDIV: __ARM_FEATURE_IDIV 1
+
+// RUN: %clang -target arm-none-linux-eabi -mcpu=cortex-a5 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V7A-NO-IDIV
+// RUN: %clang -target arm-none-linux-eabi -mcpu=cortex-a8 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V7A-NO-IDIV
+// RUN: %clang -target arm-none-linux-eabi -mcpu=cortex-a9 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V7A-NO-IDIV
+
+// CHECK-V7A-NO-IDIV-NOT: __ARM_FEATURE_IDIV
+
+// RUN: %clang -target arm-none-linux-eabi -march=armv7-r -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V7R
+
+// CHECK-V7R:     __ARM_ARCH 7
+// CHECK-V7R:     __ARM_ARCH_ISA_ARM 1
+// CHECK-V7R:     __ARM_ARCH_ISA_THUMB 2
+// CHECK-V7R:     __ARM_ARCH_PROFILE 'R'
+// CHECK-V7R:     __ARM_FEATURE_CLZ 1
+// CHECK-V7R:     __ARM_FEATURE_DSP 1
+// CHECK-V7R:     __ARM_FEATURE_LDREX 0xF
+// CHECK-V7R:     __ARM_FEATURE_QBIT 1
+// CHECK-V7R:     __ARM_FEATURE_SAT 1
+// CHECK-V7R:     __ARM_FEATURE_SIMD32 1
+// CHECK-V7R:     __ARM_FEATURE_UNALIGNED 1
+
+// RUN: %clang -target arm-none-linux-eabi -mcpu=cortex-r4 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V7R-NO-IDIV
+
+// CHECK-V7R-NO-IDIV-NOT: __ARM_FEATURE_IDIV
+
+// RUN: %clang -target arm-none-linux-eabi -mcpu=cortex-r5 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V7R-IDIV
+// RUN: %clang -target arm-none-linux-eabi -mcpu=cortex-r7 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V7R-IDIV
+
+// CHECK-V7R-IDIV: __ARM_FEATURE_IDIV 1
+
+// RUN: %clang -target arm-none-linux-eabi -march=armv7-m -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V7M
+
+// CHECK-V7M-NOT: __ARM_ARCH_ISA_ARM
+// CHECK-V7M-NOT: __ARM_FEATURE_DSP
+// CHECK-V7M-NOT: __ARM_FEATURE_SIMD32
+// CHECK-V7M:     __ARM_ARCH 7
+// CHECK-V7M:     __ARM_ARCH_ISA_THUMB 2
+// CHECK-V7M:     __ARM_ARCH_PROFILE 'M'
+// CHECK-V7M:     __ARM_FEATURE_CLZ 1
+// CHECK-V7M:     __ARM_FEATURE_IDIV 1
+// CHECK-V7M:     __ARM_FEATURE_LDREX 0x7
+// CHECK-V7M:     __ARM_FEATURE_QBIT 1
+// CHECK-V7M:     __ARM_FEATURE_SAT 1
+// CHECK-V7M:     __ARM_FEATURE_UNALIGNED 1
+
+// RUN: %clang -target arm-none-linux-eabi -march=armv7e-m -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V7EM
+
+// CHECK-V7EM: __ARM_FEATURE_DSP 1
+// CHECK-V7EM: __ARM_FEATURE_SIMD32 1
+
+// RUN: %clang -target arm-none-linux-eabi -march=armv8-a -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V8A
+
+// CHECK-V8A: __ARM_ARCH 8
+// CHECK-V8A: __ARM_ARCH_ISA_ARM 1
+// CHECK-V8A: __ARM_ARCH_ISA_THUMB 2
+// CHECK-V8A: __ARM_ARCH_PROFILE 'A'
+// CHECK-V8A: __ARM_FEATURE_CLZ 1
+// CHECK-V8A: __ARM_FEATURE_DSP 1
+// CHECK-V8A: __ARM_FEATURE_IDIV 1
+// CHECK-V8A: __ARM_FEATURE_LDREX 0xF
+// CHECK-V8A: __ARM_FEATURE_QBIT 1
+// CHECK-V8A: __ARM_FEATURE_SAT 1
+// CHECK-V8A: __ARM_FEATURE_SIMD32 1
+// CHECK-V8A: __ARM_FEATURE_UNALIGNED 1
 

test/Preprocessor/arm-acle-6.5.c

-// RUN: %clang -target arm-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-DEFAULT
+// RUN: %clang -target arm-eabi -mfpu=none -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-FP
+// RUN: %clang -target armv4-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-FP
+// RUN: %clang -target armv5-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-FP
+// RUN: %clang -target armv6m-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-FP
+// RUN: %clang -target armv7r-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-FP
+// RUN: %clang -target armv7m-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-FP
+
+// CHECK-NO-FP-NOT: __ARM_FP 0x{{.*}}
+// CHECK-NO-FP-NOT: __ARM_FP16_FORMAT_IEEE
+
+// RUN: %clang -target arm-eabi -mfpu=vfpv3xd -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP
+// RUN: %clang -target arm-eabi -mfpu=vfpv3xd-fp16 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP
+// RUN: %clang -target arm-eabi -mfpu=fpv4-sp-d16 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP
+// RUN: %clang -target arm-eabi -mfpu=fpv5-sp-d16 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP
 
-// CHECK-DEFAULT-NOT: __ARM_FP
+// CHECK-SP:     __ARM_FP 0x4
+// CHECK-SP-NOT: __ARM_FP16_FORMAT_IEEE
 
 // RUN: %clang -target arm-eabi -mfpu=vfp -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
-// RUN: %clang -target arm-eabi -mfpu=vfp3 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
+// RUN: %clang -target arm-eabi -mfpu=vfpv2 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
+// RUN: %clang -target arm-eabi -mfpu=vfpv3 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
 // RUN: %clang -target arm-eabi -mfpu=vfp3-d16 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
 // RUN: %clang -target arm-eabi -mfpu=neon -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
-// RUN: %clang -target arm-eabi -mfpu=vfp3 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
-// RUN: %clang -target armv7-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
+// RUN: %clang -target armv6-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
+// RUN: %clang -target armv7a-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
 
-// CHECK-SP-DP: __ARM_FP 0xC
+// CHECK-SP-DP:     __ARM_FP 0xC
+// CHECK-SP-DP-NOT: __ARM_FP16_FORMAT_IEEE
 
+// RUN: %clang -target arm-eabi -mfpu=vfpv3-fp16 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP-HP
+// RUN: %clang -target arm-eabi -mfpu=vfpv3-d16-fp16 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP-HP
 // RUN: %clang -target arm-eabi -mfpu=vfpv4 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP-HP
 // RUN: %clang -target arm-eabi -mfpu=vfpv4-d16 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP-HP
+// RUN: %clang -target arm-eabi -mfpu=fpv5-d16 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP-HP
 // RUN: %clang -target arm-eabi -mfpu=fp-armv8 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP-HP
+// RUN: %clang -target arm-eabi -mfpu=neon-fp16 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP-HP
+// RUN: %clang -target arm-eabi -mfpu=neon-vfpv4 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP-HP
 // RUN: %clang -target arm-eabi -mfpu=neon-fp-armv8 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP-HP
 // RUN: %clang -target arm-eabi -mfpu=crypto-neon-fp-armv8 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP-HP
 // RUN: %clang -target armv8-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP-HP
 
 // CHECK-SP-DP-HP: __ARM_FP 0xE
+// CHECK-SP-DP-HP: __ARM_FP16_FORMAT_IEEE 1
+
+// RUN: %clang -target armv4-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-FMA
+// RUN: %clang -target armv5-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-FMA
+// RUN: %clang -target armv6-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-FMA
+// RUN: %clang -target armv6m-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-FMA
+// RUN: %clang -target armv7m-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-FMA
+
+// CHECK-NO-FMA-NOT: __ARM_FEATURE_FMA
+
+// RUN: %clang -target armv7a-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-FMA
+// RUN: %clang -target armv7r-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-FMA
+// RUN: %clang -target armv7em-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-FMA
+// RUN: %clang -target armv8-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-FMA
+
+// CHECK-FMA: __ARM_FEATURE_FMA 1
+
+// RUN: %clang -target armv4-eabi -mfpu=neon -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-NEON
+// RUN: %clang -target armv5-eabi -mfpu=neon -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-NEON
+// RUN: %clang -target armv6-eabi -mfpu=neon -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-NEON
+
+// CHECK-NO-NEON-NOT: __ARM_NEON
+// CHECK-NO-NEON-NOT: __ARM_NEON_FP 0x{{.*}}
+
+// RUN: %clang -target armv7-eabi -mfpu=neon -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NEON-SP
+
+// CHECK-NEON-SP: __ARM_NEON 1
+// CHECK-NEON-SP: __ARM_NEON_FP 0x4
+
+// RUN: %clang -target armv7-eabi -mfpu=neon-fp16 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NEON-SP-HP
+// RUN: %clang -target armv7-eabi -mfpu=neon-vfpv4 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NEON-SP-HP
+// RUN: %clang -target armv7-eabi -mfpu=neon-fp-armv8 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NEON-SP-HP
+// RUN: %clang -target armv7-eabi -mfpu=crypto-neon-fp-armv8 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NEON-SP-HP
+
+// CHECK-NEON-SP-HP: __ARM_NEON 1
+// CHECK-NEON-SP-HP: __ARM_NEON_FP 0x6
+
+// RUN: %clang -target armv4-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-EXTENSIONS
+// RUN: %clang -target armv5-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-EXTENSIONS
+// RUN: %clang -target armv6-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-EXTENSIONS
+// RUN: %clang -target armv7-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-NO-EXTENSIONS
+
+// CHECK-NO-EXTENSIONS-NOT: __ARM_FEATURE_CRC32
+// CHECK-NO-EXTENSIONS-NOT: __ARM_FEATURE_CRYPTO
+// CHECK-NO-EXTENSIONS-NOT: __ARM_FEATURE_DIRECTED_ROUNDING
+// CHECK-NO-EXTENSIONS-NOT: __ARM_FEATURE_NUMERIC_MAXMIN
+
+// RUN: %clang -target armv8-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-EXTENSIONS
+
+// CHECK-EXTENSIONS: __ARM_FEATURE_CRC32 1
+// CHECK-EXTENSIONS: __ARM_FEATURE_CRYPTO 1
+// CHECK-EXTENSIONS: __ARM_FEATURE_DIRECTED_ROUNDING 1
+// CHECK-EXTENSIONS: __ARM_FEATURE_NUMERIC_MAXMIN 1