[AMDGPU] Add symbolic names for gfx940 HWREGs

[rampitec]

Summary

The namespaces of HWREGs is now overlapping with gfx10. Thus the
patch is longer than necessary to just support new names. It also
need to handle proper error messages, i.e. to issue a "specified
hardware register is not supported on this GPU" message.

This may need a major refactoring in the future.

[foad]

Seems OK but maybe a bit over-complicated as noted inline.

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

1083

I don't understand why you need to handle this alias here and on line 1092 below, and the old code had no mention of it?

1103

We also return true for GFX10Plus above, so doesn't that mean that ID_HW_ID needs no special handling at all?

[dp]

Overall looks fine.
I've already refactored handling of hwreg and sendmsg which simplifies the code significantly. But I have to update my patch with GFX940 changes before sending it for review.

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

614–616

I'm not sure LLVM_READNONE could be used here because the function reads non-constant memory pointed to by Name. Should the attribute be replaced with LLVM_READONLY?

[rampitec]

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

1083

This is because the alias is not recognized by the code at 1087 and we exit. But the check at 1092 is not needed, removed.

1103

Yes, it is not needed anymore. Removed.

[dp]

LGTM

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

public:
   OperandMatchResultTy parseHwreg(OperandVector &Operands);
 
 private:
   struct OperandInfoTy {
     SMLoc Loc;
     int64_t Id;
     bool IsSymbolic = false;
     bool IsDefined = false;
+    StringRef Name;
 
     OperandInfoTy(int64_t Id_) : Id(Id_) {}
   };
 
   bool parseSendMsgBody(OperandInfoTy &Msg, OperandInfoTy &Op, OperandInfoTy &Stream);
   bool validateSendMsg(const OperandInfoTy &Msg,
                        const OperandInfoTy &Op,
                        const OperandInfoTy &Stream);
AMDGPUAsmParser::parseHwregBody(OperandInfoTy &HwReg,
                                 OperandInfoTy &Width) {
   using namespace llvm::AMDGPU::Hwreg;
 
   // The register may be specified by name or using a numeric code
   HwReg.Loc = getLoc();
   if (isToken(AsmToken::Identifier) &&
       (HwReg.Id = getHwregId(getTokenStr(), getSTI())) >= 0) {
     HwReg.IsSymbolic = true;
+    HwReg.Name = getTokenStr();
     lex(); // skip register name
   } else if (!parseExpr(HwReg.Id, "a register name")) {
     return false;
   }
 
   if (trySkipToken(AsmToken::RParen))
     return true;
 

 
 bool
 AMDGPUAsmParser::validateHwreg(const OperandInfoTy &HwReg,
                                const OperandInfoTy &Offset,
                                const OperandInfoTy &Width) {
 
   using namespace llvm::AMDGPU::Hwreg;
 
-  if (HwReg.IsSymbolic && !isValidHwreg(HwReg.Id, getSTI())) {
+  if (HwReg.IsSymbolic &&
+      !isValidHwreg(HwReg.Id, getSTI(), HwReg.Name)) {
     Error(HwReg.Loc,
           "specified hardware register is not supported on this GPU");
     return false;
   }
   if (!isValidHwreg(HwReg.Id)) {
     Error(HwReg.Loc,
           "invalid code of hardware register: only 6-bit values are legal");
     return false;

llvm/lib/Target/AMDGPU/SIDefines.h

enum Id { // HwRegCode, (6) [5:0]
   ID_LDS_ALLOC = 6,
   ID_IB_STS = 7,
   ID_MEM_BASES = 15,
   ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES,
   ID_TBA_LO = 16,
   ID_TBA_HI = 17,
   ID_TMA_LO = 18,
   ID_TMA_HI = 19,
+  ID_XCC_ID = 20,
+  ID_SYMBOLIC_FIRST_GFX940_ = ID_XCC_ID,
+  ID_SQ_PERF_SNAPSHOT_DATA = 21,
+  ID_SQ_PERF_SNAPSHOT_DATA1 = 22,
+  ID_SQ_PERF_SNAPSHOT_PC_LO = 23,
+  ID_SQ_PERF_SNAPSHOT_PC_HI = 24,
+  ID_SYMBOLIC_LAST_GFX940_ = ID_SQ_PERF_SNAPSHOT_PC_HI + 1,
   ID_FLAT_SCR_LO = 20,
   ID_SYMBOLIC_FIRST_GFX10_ = ID_FLAT_SCR_LO,
   ID_FLAT_SCR_HI = 21,
   ID_XNACK_MASK = 22,
   ID_HW_ID1 = 23,
   ID_HW_ID2 = 24,
   ID_POPS_PACKER = 25,
   ID_SHADER_CYCLES = 29,

llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h

 extern const char *const OpSysSymbolic[OP_SYS_LAST_];
 extern const char *const OpGsSymbolic[OP_GS_LAST_];
 
 } // namespace SendMsg
 
 namespace Hwreg { // Symbolic names for the hwreg(...) syntax.
 
 extern const char* const IdSymbolic[];
+extern const char* const IdSymbolicGFX940Specific[];
 
 } // namespace Hwreg
 
 namespace MTBUFFormat {
 
 extern StringLiteral const DfmtSymbolic[];
 extern StringLiteral const NfmtSymbolicGFX10[];
 extern StringLiteral const NfmtSymbolicSICI[];

llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp

const char* const IdSymbolic[] = {
   "HW_REG_HW_ID2",
   "HW_REG_POPS_PACKER",
   nullptr,
   nullptr,
   nullptr,
   "HW_REG_SHADER_CYCLES"
 };
 
+// This is gfx940 specific portion from ID_SYMBOLIC_FIRST_GFX940_ to
+// ID_SYMBOLIC_LAST_GFX940_
+const char* const IdSymbolicGFX940Specific[] = {
+  "HW_REG_XCC_ID",
+  "HW_REG_SQ_PERF_SNAPSHOT_DATA",
+  "HW_REG_SQ_PERF_SNAPSHOT_DATA1",
+  "HW_REG_SQ_PERF_SNAPSHOT_PC_LO",
+  "HW_REG_SQ_PERF_SNAPSHOT_PC_HI"
+};
+
 } // namespace Hwreg
 
 namespace MTBUFFormat {
 
 StringLiteral const DfmtSymbolic[] = {
   "BUF_DATA_FORMAT_INVALID",
   "BUF_DATA_FORMAT_8",
   "BUF_DATA_FORMAT_16",

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

unsigned encodeWaitcnt(const IsaVersion &Version,
                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
 
 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
 
 namespace Hwreg {
 
 LLVM_READONLY
 int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
 
-LLVM_READNONE
-bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
+LLVM_READONLY
+bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI, StringRef Name);
 
 LLVM_READNONE
 bool isValidHwreg(int64_t Id);
 
 LLVM_READNONE
 bool isValidHwregOffset(int64_t Offset);
 
 LLVM_READNONE

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 }
 
 //===----------------------------------------------------------------------===//
 // hwreg
 //===----------------------------------------------------------------------===//
 
 namespace Hwreg {
 
+static const char* getHwregName(int64_t Id, const MCSubtargetInfo &STI) {
+  if (isGFX940(STI) && Id >= ID_SYMBOLIC_FIRST_GFX940_ &&
+      Id < ID_SYMBOLIC_LAST_GFX940_)
+    return IdSymbolicGFX940Specific[Id - ID_SYMBOLIC_FIRST_GFX940_];
+  return (Id < ID_SYMBOLIC_LAST_) ? IdSymbolic[Id] : nullptr;
+}
+
 int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI) {
   if (isGFX10(STI) && Name == "HW_REG_HW_ID") // An alias
     return ID_HW_ID1;
   for (int Id = ID_SYMBOLIC_FIRST_; Id < ID_SYMBOLIC_LAST_; ++Id) {
     if (IdSymbolic[Id] && Name == IdSymbolic[Id])
       return Id;
+    // These are all defined, however may be invalid for subtarget and need
+    // further validation.
+    if (Id >= ID_SYMBOLIC_FIRST_GFX940_ && Id < ID_SYMBOLIC_LAST_GFX940_ &&
+        Name == IdSymbolicGFX940Specific[Id - ID_SYMBOLIC_FIRST_GFX940_])
+      return Id;
   }
   return ID_UNKNOWN_;
 }
 
 static unsigned getLastSymbolicHwreg(const MCSubtargetInfo &STI) {
   if (isSI(STI) || isCI(STI) || isVI(STI))
     return ID_SYMBOLIC_FIRST_GFX9_;
+  else if (isGFX940(STI))
+    return ID_SYMBOLIC_LAST_GFX940_;
   else if (isGFX9(STI))
     return ID_SYMBOLIC_FIRST_GFX10_;
   else if (isGFX10(STI) && !isGFX10_BEncoding(STI))
     return ID_SYMBOLIC_FIRST_GFX1030_;
   else
     return ID_SYMBOLIC_LAST_;
 }
 
-bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI) {
+bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI, StringRef Name) {
+  if (isGFX10(STI) && Name == "HW_REG_HW_ID") // An alias
+    return true;
+
+  const char *HWRegName = getHwregName(Id, STI);
+  if (!HWRegName || !Name.startswith(HWRegName))
+    return false;
+
+  if (isGFX10Plus(STI)) {
     switch (Id) {
-  case ID_HW_ID:
-    return isSI(STI) || isCI(STI) || isVI(STI) || isGFX9(STI);
     case ID_HW_ID1:
     case ID_HW_ID2:
-    return isGFX10Plus(STI);
+      return true;
     case ID_XNACK_MASK:
-    return isGFX10(STI) && !AMDGPU::isGFX10_BEncoding(STI);
+      return !AMDGPU::isGFX10_BEncoding(STI);
     default:
-    return ID_SYMBOLIC_FIRST_ <= Id && Id < getLastSymbolicHwreg(STI) &&
-           IdSymbolic[Id];
+      break;
+    }
   }
+
+  if (ID_SYMBOLIC_FIRST_ > Id || Id >= getLastSymbolicHwreg(STI))
+    return false;
+
+  if (isGFX940(STI) && Id >= ID_SYMBOLIC_FIRST_GFX10_ &&
+      Id < ID_SYMBOLIC_FIRST_GFX940_)
+    return false;
+
+  return true;
 }
 
 bool isValidHwreg(int64_t Id) {
   return 0 <= Id && isUInt<ID_WIDTH_>(Id);
 }
 
 bool isValidHwregOffset(int64_t Offset) {
   return 0 <= Offset && isUInt<OFFSET_WIDTH_>(Offset);
 }
 
 bool isValidHwregWidth(int64_t Width) {
   return 0 <= (Width - 1) && isUInt<WIDTH_M1_WIDTH_>(Width - 1);
 }
 
 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width) {
   return (Id << ID_SHIFT_) |
          (Offset << OFFSET_SHIFT_) |
          ((Width - 1) << WIDTH_M1_SHIFT_);
 }
 
 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI) {
-  return isValidHwreg(Id, STI) ? IdSymbolic[Id] : "";
+  const char *HWRegName = getHwregName(Id, STI);
+  return (HWRegName && isValidHwreg(Id, STI, HWRegName)) ? HWRegName : "";
 }
 
 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width) {
   Id = (Val & ID_MASK_) >> ID_SHIFT_;
   Offset = (Val & OFFSET_MASK_) >> OFFSET_SHIFT_;
   Width = ((Val & WIDTH_M1_MASK_) >> WIDTH_M1_SHIFT_) + 1;
 }
 

llvm/test/MC/AMDGPU/gfx940_asm_features.s

 // NOT-GFX940: error: instruction not supported on this GPU
 // GFX940: scratch_load_lds_ushort v2, off         ; encoding: [0x00,0x60,0xa0,0xdc,0x02,0x00,0x7f,0x00]
 scratch_load_lds_ushort v2, off
 
 // NOT-GFX940: error: instruction not supported on this GPU
 // GFX940: scratch_load_lds_sshort v2, off         ; encoding: [0x00,0x60,0xa4,0xdc,0x02,0x00,0x7f,0x00]
 scratch_load_lds_sshort v2, off
 
+// NOT-GFX940: error: specified hardware register is not supported on this GPU
+// GFX940: s_getreg_b32 s1, hwreg(HW_REG_XCC_ID)   ; encoding: [0x14,0xf8,0x81,0xb8]
+s_getreg_b32 s1, hwreg(HW_REG_XCC_ID)
+
+// NOT-GFX940: error: specified hardware register is not supported on this GPU
+// GFX940: s_getreg_b32 s1, hwreg(HW_REG_SQ_PERF_SNAPSHOT_DATA) ; encoding: [0x15,0xf8,0x81,0xb8]
+s_getreg_b32 s1, hwreg(HW_REG_SQ_PERF_SNAPSHOT_DATA)
+
+// NOT-GFX940: error: specified hardware register is not supported on this GPU
+// GFX940: s_getreg_b32 s1, hwreg(HW_REG_SQ_PERF_SNAPSHOT_DATA1) ; encoding: [0x16,0xf8,0x81,0xb8]
+s_getreg_b32 s1, hwreg(HW_REG_SQ_PERF_SNAPSHOT_DATA1)
+
+// NOT-GFX940: error: specified hardware register is not supported on this GPU
+// GFX940: s_getreg_b32 s1, hwreg(HW_REG_SQ_PERF_SNAPSHOT_PC_LO) ; encoding: [0x17,0xf8,0x81,0xb8]
+s_getreg_b32 s1, hwreg(HW_REG_SQ_PERF_SNAPSHOT_PC_LO)
+
+// NOT-GFX940: error: specified hardware register is not supported on this GPU
+// GFX940: s_getreg_b32 s1, hwreg(HW_REG_SQ_PERF_SNAPSHOT_PC_HI) ; encoding: [0x18,0xf8,0x81,0xb8]
+s_getreg_b32 s1, hwreg(HW_REG_SQ_PERF_SNAPSHOT_PC_HI)
+
+// GFX940: s_getreg_b32 s1, hwreg(HW_REG_TMA_HI)   ; encoding: [0x13,0xf8,0x81,0xb8]
+s_getreg_b32 s1, hwreg(19)
+
+// GFX940: s_getreg_b32 s1, hwreg(HW_REG_XCC_ID)   ; encoding: [0x14,0xf8,0x81,0xb8]
+s_getreg_b32 s1, hwreg(20)
+
+// GFX940: s_getreg_b32 s1, hwreg(HW_REG_SQ_PERF_SNAPSHOT_DATA) ; encoding: [0x15,0xf8,0x81,0xb8]
+s_getreg_b32 s1, hwreg(21)
+
+// GFX940: s_getreg_b32 s1, hwreg(HW_REG_SQ_PERF_SNAPSHOT_DATA1) ; encoding: [0x16,0xf8,0x81,0xb8]
+s_getreg_b32 s1, hwreg(22)
+
+// GFX940: s_getreg_b32 s1, hwreg(HW_REG_SQ_PERF_SNAPSHOT_PC_LO) ; encoding: [0x17,0xf8,0x81,0xb8]
+s_getreg_b32 s1, hwreg(23)
+
+// GFX940: s_getreg_b32 s1, hwreg(HW_REG_SQ_PERF_SNAPSHOT_PC_HI) ; encoding: [0x18,0xf8,0x81,0xb8]
+s_getreg_b32 s1, hwreg(24)
+
+// GFX940: s_getreg_b32 s1, hwreg(25)              ; encoding: [0x19,0xf8,0x81,0xb8]
+s_getreg_b32 s1, hwreg(25)
+
 // NOT-GFX940: error: instruction not supported on this GPU
 // GFX940: v_mov_b64_e32 v[2:3], v[4:5]            ; encoding: [0x04,0x71,0x04,0x7e]
 v_mov_b64 v[2:3], v[4:5]
 
 // NOT-GFX940: error: instruction not supported on this GPU
 // GFX940: v_mov_b64_dpp v[2:3], v[4:5] row_newbcast:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x70,0x04,0x7e,0x04,0x51,0x01,0xff]
 v_mov_b64 v[2:3], v[4:5]  row_newbcast:1
 

llvm/test/MC/AMDGPU/gfx940_err.s

 buffer_atomic_swap v5, off, s[8:11], s3 slc
 // GFX940: error: invalid operand for instruction
 
 buffer_wbl2 glc
 // GFX940: error: invalid operand for instruction
 
 buffer_wbl2 scc
 // GFX940: error: invalid operand for instruction
+
+s_getreg_b32 s1, hwreg(HW_REG_FLAT_SCR_LO)
+// GFX940: error: specified hardware register is not supported on this GPU
+
+s_getreg_b32 s1, hwreg(HW_REG_FLAT_SCR_HI)
+// GFX940: error: specified hardware register is not supported on this GPU
+
+s_getreg_b32 s1, hwreg(HW_REG_XNACK_MASK)
+// GFX940: error: specified hardware register is not supported on this GPU
+
+s_getreg_b32 s1, hwreg(HW_REG_HW_ID1)
+// GFX940: error: specified hardware register is not supported on this GPU
+
+s_getreg_b32 s1, hwreg(HW_REG_HW_ID2)
+// GFX940: error: specified hardware register is not supported on this GPU
+
+s_getreg_b32 s1, hwreg(HW_REG_POPS_PACKER)
+// GFX940: error: specified hardware register is not supported on this GPU

llvm/test/MC/Disassembler/AMDGPU/gfx940_dasm_features.txt

 0x00,0x60,0x9c,0xdc,0x02,0x00,0x7f,0x00
 
 # GFX940: scratch_load_lds_ushort v2, off         ; encoding: [0x00,0x60,0xa0,0xdc,0x02,0x00,0x7f,0x00]
 0x00,0x60,0xa0,0xdc,0x02,0x00,0x7f,0x00
 
 # GFX940: scratch_load_lds_sshort v2, off         ; encoding: [0x00,0x60,0xa4,0xdc,0x02,0x00,0x7f,0x00]
 0x00,0x60,0xa4,0xdc,0x02,0x00,0x7f,0x00
 
+# GFX940: s_getreg_b32 s1, hwreg(HW_REG_XCC_ID)   ; encoding: [0x14,0xf8,0x81,0xb8]
+0x14,0xf8,0x81,0xb8
+
+# GFX940: s_getreg_b32 s1, hwreg(HW_REG_SQ_PERF_SNAPSHOT_DATA) ; encoding: [0x15,0xf8,0x81,0xb8]
+0x15,0xf8,0x81,0xb8
+
+# GFX940: s_getreg_b32 s1, hwreg(HW_REG_SQ_PERF_SNAPSHOT_DATA1) ; encoding: [0x16,0xf8,0x81,0xb8]
+0x16,0xf8,0x81,0xb8
+
+# GFX940: s_getreg_b32 s1, hwreg(HW_REG_SQ_PERF_SNAPSHOT_PC_LO) ; encoding: [0x17,0xf8,0x81,0xb8]
+0x17,0xf8,0x81,0xb8
+
+# GFX940: s_getreg_b32 s1, hwreg(HW_REG_SQ_PERF_SNAPSHOT_PC_HI) ; encoding: [0x18,0xf8,0x81,0xb8]
+0x18,0xf8,0x81,0xb8
+
 # GFX940: v_mov_b64_e32 v[2:3], v[4:5]            ; encoding: [0x04,0x71,0x04,0x7e]
 0x04,0x71,0x04,0x7e
 
 # GFX940: v_mov_b64_dpp v[2:3], v[4:5] row_newbcast:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x70,0x04,0x7e,0x04,0x51,0x01,0xff]
 0xfa,0x70,0x04,0x7e,0x04,0x51,0x01,0xff
 
 # GFX940: v_mov_b64_e32 v[2:3], s[4:5]            ; encoding: [0x04,0x70,0x04,0x7e]
 0x04,0x70,0x04,0x7e