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llvm/docs/AMDGPUUsage.rst
8721	How about: Atomic read-modify-write instructions implicitly bypass the L1 cache. Therefore, they do not use the sc0 bit for coherence and instead use it to indicate if the instruction returns the original value being updated. They do use sc1 to indicate system or agent scope coherence.

rampitec updated this revision to Diff 415130.Mar 14 2022, 9:56 AM

rampitec marked an inline comment as done.

rampitec added inline comments.

llvm/docs/AMDGPUUsage.rst
8721	Thanks Tony. Updated text.

Harbormaster completed remote builds in B154127: Diff 415130.Mar 14 2022, 10:31 AM

LGTM

llvm/docs/AMDGPUUsage.rst
8721	This also applies to all other targets

This revision is now accepted and ready to land.Mar 14 2022, 4:14 PM

This revision was landed with ongoing or failed builds.Mar 16 2022, 12:02 PM

Closed by commit rG3a37d08b3521: [AMDGPU] Correct gfx940 memory model documentation. (authored by rampitec). · Explain Why

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AMDGPUUsage.rst

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llvm/docs/AMDGPUUsage.rst

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Show First 20 Lines • Show All 8,706 Lines • ▼ Show 20 Lines	* The vector memory operations access a single vector L1 cache shared by all

* No special action is required for coherence between the lanes of a single		* No special action is required for coherence between the lanes of a single
wavefront.		wavefront.

* No special action is required for coherence between wavefronts in the same		* No special action is required for coherence between wavefronts in the same
work-group since they execute on the same CU. The exception is when in		work-group since they execute on the same CU. The exception is when in
tgsplit execution mode as wavefronts of the same work-group can be in		tgsplit execution mode as wavefronts of the same work-group can be in
different CUs and so a ``buffer_inv sc0`` is required which will invalidate		different CUs and so a ``buffer_inv sc0`` is required which will invalidate
the L1 cache is in tgsplit mode.		the L1 cache.

* A ``buffer_inv sc1`` is required to invalidate the L1 cache for coherence		* A ``buffer_inv sc0`` is required to invalidate the L1 cache for coherence
between wavefronts executing in different work-groups as they may be		between wavefronts executing in different work-groups as they may be
executing on different CUs.		executing on different CUs.

		* Atomic read-modify-write instructions implicitly bypass the L1 cache.
		t-tyeUnsubmitted Done Reply Inline Actions How about: Atomic read-modify-write instructions implicitly bypass the L1 cache. Therefore, they do not use the sc0 bit for coherence and instead use it to indicate if the instruction returns the original value being updated. They do use sc1 to indicate system or agent scope coherence. t-tye: How about: Atomic read-modify-write instructions implicitly bypass the L1 cache. Therefore…
		t-tyeUnsubmitted Not Done Reply Inline Actions This also applies to all other targets t-tye: This also applies to all other targets
		rampitecAuthorUnsubmitted Done Reply Inline Actions Thanks Tony. Updated text. rampitec: Thanks Tony. Updated text.
		Therefore, they do not use the sc0 bit for coherence and instead use it to
		indicate if the instruction returns the original value being updated. They
		do use sc1 to indicate system or agent scope coherence.

* The scalar memory operations access a scalar L1 cache shared by all wavefronts		* The scalar memory operations access a scalar L1 cache shared by all wavefronts
on a group of CUs. The scalar and vector L1 caches are not coherent. However,		on a group of CUs. The scalar and vector L1 caches are not coherent. However,
scalar operations are used in a restricted way so do not impact the memory		scalar operations are used in a restricted way so do not impact the memory
model. See :ref:`amdgpu-amdhsa-memory-spaces`.		model. See :ref:`amdgpu-amdhsa-memory-spaces`.
* The vector and scalar memory operations use an L2 cache.		* The vector and scalar memory operations use an L2 cache.

* The gfx940 can be configured as a number of smaller agents with each having		* The gfx940 can be configured as a number of smaller agents with each having
a single L2 shared by all CUs on the same agent, or as fewer (possibly one)		a single L2 shared by all CUs on the same agent, or as fewer (possibly one)
▲ Show 20 Lines • Show All 157 Lines • ▼ Show 20 Lines	load atomic monotonic - singlethread - local *If TgSplit execution mode,

1. ds_load		1. ds_load
load atomic monotonic - agent - global 1. buffer/global/flat_load		load atomic monotonic - agent - global 1. buffer/global/flat_load
- generic sc1=1		- generic sc1=1
load atomic monotonic - system - global 1. buffer/global/flat_load		load atomic monotonic - system - global 1. buffer/global/flat_load
- generic sc0=1 sc1=1		- generic sc0=1 sc1=1
store atomic monotonic - singlethread - global 1. buffer/global/flat_store		store atomic monotonic - singlethread - global 1. buffer/global/flat_store
- wavefront - generic		- wavefront - generic
store atomic monotonic - singlethread - global 1. buffer/global/flat_store
- wavefront - generic
store atomic monotonic - workgroup - global 1. buffer/global/flat_store		store atomic monotonic - workgroup - global 1. buffer/global/flat_store
- generic sc0=1		- generic sc0=1
store atomic monotonic - agent - global 1. buffer/global/flat_store		store atomic monotonic - agent - global 1. buffer/global/flat_store
- generic sc1=1		- generic sc1=1
store atomic monotonic - system - global 1. buffer/global/flat_store		store atomic monotonic - system - global 1. buffer/global/flat_store
- generic sc0=1 sc1=1		- generic sc0=1 sc1=1
store atomic monotonic - singlethread - local *If TgSplit execution mode,		store atomic monotonic - singlethread - local *If TgSplit execution mode,
- wavefront local address space cannot		- wavefront local address space cannot
▲ Show 20 Lines • Show All 730 Lines • ▼ Show 20 Lines	store atomic release - agent - global 1. buffer_wbl2 sc1=1
- Ensures that all		- Ensures that all
memory operations		memory operations
to memory have		to memory have
completed before		completed before
performing the		performing the
store that is being		store that is being
released.		released.

3. buffer/global/flat_store sc1=1		3. buffer/global/flat_store sc1=1
store atomic release - system - global 1. buffer_wbl2 sc0=1 sc1=1		store atomic release - system - global 1. buffer_wbl2 sc0=1 sc1=1
- generic		- generic
- Must happen before		- Must happen before
following s_waitcnt.		following s_waitcnt.
- Performs L2 writeback to		- Performs L2 writeback to
ensure previous		ensure previous
global/generic		global/generic
store/atomicrmw are		store/atomicrmw are
Show All 38 Lines	store atomic release - system - global 1. buffer_wbl2 sc0=1 sc1=1
memory operations		memory operations
to memory and the L2		to memory and the L2
writeback have		writeback have
completed before		completed before
performing the		performing the
store that is being		store that is being
released.		released.

2. buffer/global/flat_store		3. buffer/global/flat_store
sc0=1 sc1=1		sc0=1 sc1=1
atomicrmw release - singlethread - global 1. buffer/global/flat_atomic		atomicrmw release - singlethread - global 1. buffer/global/flat_atomic
- wavefront - generic		- wavefront - generic
atomicrmw release - singlethread - local *If TgSplit execution mode,		atomicrmw release - singlethread - local *If TgSplit execution mode,
- wavefront local address space cannot		- wavefront local address space cannot
be used.*		be used.*

1. ds_atomic		1. ds_atomic
▲ Show 20 Lines • Show All 1,167 Lines • ▼ Show 20 Lines	fence acq_rel - system none 1. buffer_wbl2 sc0=1 sc1=1
MTYPE RW and CC memory will		MTYPE RW and CC memory will
never be stale due to the		never be stale due to the
memory probes.		memory probes.

Sequential Consistent Atomic		Sequential Consistent Atomic
------------------------------------------------------------------------------------		------------------------------------------------------------------------------------
load atomic seq_cst - singlethread - global *Same as corresponding		load atomic seq_cst - singlethread - global *Same as corresponding
- wavefront - local load atomic acquire,		- wavefront - local load atomic acquire,
- generic except must generated		- generic except must generate
all instructions even		all instructions even
for OpenCL.*		for OpenCL.*
load atomic seq_cst - workgroup - global 1. s_waitcnt lgkm/vmcnt(0)		load atomic seq_cst - workgroup - global 1. s_waitcnt lgkm/vmcnt(0)
- generic		- generic
- Use lgkmcnt(0) if not		- Use lgkmcnt(0) if not
TgSplit execution mode		TgSplit execution mode
and vmcnt(0) if TgSplit		and vmcnt(0) if TgSplit
execution mode.		execution mode.
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines	load atomic seq_cst - workgroup - global 1. s_waitcnt lgkm/vmcnt(0)
so that the store		so that the store
may have already		may have already
completed.)		completed.)

2. *Following		2. *Following
instructions same as		instructions same as
corresponding load		corresponding load
atomic acquire,		atomic acquire,
except must generated		except must generate
all instructions even		all instructions even
for OpenCL.*		for OpenCL.*
load atomic seq_cst - workgroup - local *If TgSplit execution mode,		load atomic seq_cst - workgroup - local *If TgSplit execution mode,
local address space cannot		local address space cannot
be used.*		be used.*

*Same as corresponding		*Same as corresponding
load atomic acquire,		load atomic acquire,
except must generated		except must generate
all instructions even		all instructions even
for OpenCL.*		for OpenCL.*

load atomic seq_cst - agent - global 1. s_waitcnt lgkmcnt(0) &		load atomic seq_cst - agent - global 1. s_waitcnt lgkmcnt(0) &
- system - generic vmcnt(0)		- system - generic vmcnt(0)

- If TgSplit execution mode,		- If TgSplit execution mode,
omit lgkmcnt(0).		omit lgkmcnt(0).
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines	load atomic seq_cst - agent - global 1. s_waitcnt lgkmcnt(0) &
so that the store		so that the store
may have already		may have already
completed.)		completed.)

2. *Following		2. *Following
instructions same as		instructions same as
corresponding load		corresponding load
atomic acquire,		atomic acquire,
except must generated		except must generate
all instructions even		all instructions even
for OpenCL.*		for OpenCL.*
store atomic seq_cst - singlethread - global *Same as corresponding		store atomic seq_cst - singlethread - global *Same as corresponding
- wavefront - local store atomic release,		- wavefront - local store atomic release,
- workgroup - generic except must generated		- workgroup - generic except must generate
- agent all instructions even		- agent all instructions even
- system for OpenCL.*		- system for OpenCL.*
atomicrmw seq_cst - singlethread - global *Same as corresponding		atomicrmw seq_cst - singlethread - global *Same as corresponding
- wavefront - local atomicrmw acq_rel,		- wavefront - local atomicrmw acq_rel,
- workgroup - generic except must generated		- workgroup - generic except must generate
- agent all instructions even		- agent all instructions even
- system for OpenCL.*		- system for OpenCL.*
fence seq_cst - singlethread none *Same as corresponding		fence seq_cst - singlethread none *Same as corresponding
- wavefront fence acq_rel,		- wavefront fence acq_rel,
- workgroup except must generated		- workgroup except must generate
- agent all instructions even		- agent all instructions even
- system for OpenCL.*		- system for OpenCL.*
============ ============ ============== ========== ================================		============ ============ ============== ========== ================================

.. _amdgpu-amdhsa-memory-model-gfx10:		.. _amdgpu-amdhsa-memory-model-gfx10:

Memory Model GFX10		Memory Model GFX10
++++++++++++++++++		++++++++++++++++++
▲ Show 20 Lines • Show All 3,903 Lines • Show Last 20 Lines

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