This is an archive of the discontinued LLVM Phabricator instance.

Differential D121353

[SLP][NFC] This adds a test for a follow-up patch that fixes a look-ahead operand reordering issue
ClosedPublic

Authored by vporpo on Mar 9 2022, 9:43 PM.

Details

Reviewers
ABataev
RKSimon
fhahn
Commits
rGb051c836c0c8: [SLP][NFC] This adds a test for a follow-up patch that fixes a look-ahead…

Diff Detail

Event Timeline

vporpo created this revision.Mar 9 2022, 9:43 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 9 2022, 9:43 PM
vporpo requested review of this revision.Mar 9 2022, 9:43 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 9 2022, 9:43 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
vporpo added a child revision: D121354: [SLP] Fix lookahead operand reordering for splat loads..Mar 9 2022, 9:46 PM
Harbormaster completed remote builds in B153484: Diff 414274.Mar 9 2022, 10:30 PM
RKSimon accepted this revision.Mar 9 2022, 11:33 PM

LGTM with one minor comment/question

llvm/test/Transforms/SLPVectorizer/X86/lookahead.ll
648

do we need the weak_odr attribute?

This revision is now accepted and ready to land.Mar 9 2022, 11:33 PM
vporpo updated this revision to Diff 414285.Mar 10 2022, 12:17 AM

Removed the weak_odr attribute.

RKSimon accepted this revision.Mar 10 2022, 12:42 AM
Harbormaster completed remote builds in B153492: Diff 414285.Mar 10 2022, 1:04 AM
vporpo updated this revision to Diff 415943.Mar 16 2022, 12:51 PM

Added a new RUN for SSE2 checks.

Harbormaster completed remote builds in B154675: Diff 415943.Mar 16 2022, 1:42 PM
This revision was landed with ongoing or failed builds.Mar 17 2022, 6:06 PM
Closed by commit rGb051c836c0c8: [SLP][NFC] This adds a test for a follow-up patch that fixes a look-ahead… (authored by vporpo). · Explain Why
This revision was automatically updated to reflect the committed changes.
vporpo added a commit: rGb051c836c0c8: [SLP][NFC] This adds a test for a follow-up patch that fixes a look-ahead….

Revision Contents

PathSize
llvm/
test/
Transforms/
SLPVectorizer/
X86/
50 lines
177 lines

Diff 416367

llvm/test/Transforms/SLPVectorizer/X86/lookahead.ll

Show First 20 Lines • Show All 636 Lines • ▼ Show 20 Lines;
%add1 = fadd double %mul1, %mul4 %add1 = fadd double %mul1, %mul4
%sidx0 = getelementptr inbounds double, double* %storeArray, i64 0 %sidx0 = getelementptr inbounds double, double* %storeArray, i64 0
%sidx1 = getelementptr inbounds double, double* %storeArray, i64 1 %sidx1 = getelementptr inbounds double, double* %storeArray, i64 1
store double %add0, double *%sidx0, align 8 store double %add0, double *%sidx0, align 8
store double %add1, double *%sidx1, align 8 store double %add1, double *%sidx1, align 8
ret void ret void
} }
; This checks that we we prefer splats rather than reverse load vectors + shuffles.
; 2-wide splat loads in x86 use a single instruction so they are quite cheap.
define double @splat_loads(double *%array1, double *%array2, double *%ptrA, double *%ptrB) {
RKSimonUnsubmitted
Not Done
ReplyInline Actions

do we need the weak_odr attribute?

RKSimon: do we need the weak_odr attribute?
; CHECK-LABEL: @splat_loads(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[GEP_1_0:%.*]] = getelementptr inbounds double, double* [[ARRAY1:%.*]], i64 0
; CHECK-NEXT: [[GEP_1_1:%.*]] = getelementptr inbounds double, double* [[ARRAY1]], i64 1
; CHECK-NEXT: [[TMP0:%.*]] = bitcast double* [[GEP_1_0]] to <2 x double>*
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[TMP0]], align 8
; CHECK-NEXT: [[GEP_2_0:%.*]] = getelementptr inbounds double, double* [[ARRAY2:%.*]], i64 0
; CHECK-NEXT: [[GEP_2_1:%.*]] = getelementptr inbounds double, double* [[ARRAY2]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = bitcast double* [[GEP_2_0]] to <2 x double>*
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, <2 x double>* [[TMP2]], align 8
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP1]], [[SHUFFLE]]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[SHUFFLE]], i32 1
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> poison, double [[TMP5]], i32 0
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[SHUFFLE]], i32 0
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x double> [[TMP6]], double [[TMP7]], i32 1
; CHECK-NEXT: [[TMP9:%.*]] = fmul <2 x double> [[TMP1]], [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = fadd <2 x double> [[TMP4]], [[TMP9]]
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x double> [[TMP10]], i32 0
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x double> [[TMP10]], i32 1
; CHECK-NEXT: [[ADD3:%.*]] = fadd double [[TMP11]], [[TMP12]]
; CHECK-NEXT: ret double [[ADD3]]
;
entry:
%gep_1_0 = getelementptr inbounds double, double* %array1, i64 0
%gep_1_1 = getelementptr inbounds double, double* %array1, i64 1
%ld_1_0 = load double, double* %gep_1_0, align 8
%ld_1_1 = load double, double* %gep_1_1, align 8
%gep_2_0 = getelementptr inbounds double, double* %array2, i64 0
%gep_2_1 = getelementptr inbounds double, double* %array2, i64 1
%ld_2_0 = load double, double* %gep_2_0, align 8
%ld_2_1 = load double, double* %gep_2_1, align 8
%mul1 = fmul double %ld_1_0, %ld_2_0
%mul2 = fmul double %ld_1_1, %ld_2_0
%mul3 = fmul double %ld_1_0, %ld_2_1
%mul4 = fmul double %ld_1_1, %ld_2_1
%add1 = fadd double %mul1, %mul3
%add2 = fadd double %mul2, %mul4
%add3 = fadd double %add1, %add2
ret double %add3
}

llvm/test/Transforms/SLPVectorizer/X86/operandorder.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -basic-aa -slp-vectorizer -slp-threshold=-100 -instcombine -dce -S -mtriple=i386-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s ; RUN: opt < %s -basic-aa -slp-vectorizer -slp-threshold=-100 -instcombine -dce -S -mtriple=i386-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
; RUN: opt < %s -basic-aa -slp-vectorizer -slp-threshold=-100 -instcombine -dce -S -mtriple=i386-apple-macosx10.8.0 -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128"
; Make sure we order the operands of commutative operations so that we get ; Make sure we order the operands of commutative operations so that we get
; bigger vectorizable trees. ; bigger vectorizable trees.
define void @shuffle_operands1(double * noalias %from, double * noalias %to, double %v1, double %v2) { define void @shuffle_operands1(double * noalias %from, double * noalias %to, double %v1, double %v2) {
; CHECK-LABEL: @shuffle_operands1( ; CHECK-LABEL: @shuffle_operands1(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast double* [[FROM:%.*]] to <2 x double>* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast double* [[FROM:%.*]] to <2 x double>*
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, <2 x double>* [[TMP1]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, <2 x double>* [[TMP1]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[V1:%.*]], i64 0 ; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[V1:%.*]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[V2:%.*]], i64 1 ; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[V2:%.*]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = fadd <2 x double> [[TMP2]], [[TMP4]] ; CHECK-NEXT: [[TMP5:%.*]] = fadd <2 x double> [[TMP2]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>* ; CHECK-NEXT: [[TMP6:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>*
; CHECK-NEXT: store <2 x double> [[TMP5]], <2 x double>* [[TMP6]], align 4 ; CHECK-NEXT: store <2 x double> [[TMP5]], <2 x double>* [[TMP6]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; SSE2-LABEL: @shuffle_operands1(
; SSE2-NEXT: [[TMP1:%.*]] = bitcast double* [[FROM:%.*]] to <2 x double>*
; SSE2-NEXT: [[TMP2:%.*]] = load <2 x double>, <2 x double>* [[TMP1]], align 4
; SSE2-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[V1:%.*]], i64 0
; SSE2-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[V2:%.*]], i64 1
; SSE2-NEXT: [[TMP5:%.*]] = fadd <2 x double> [[TMP2]], [[TMP4]]
; SSE2-NEXT: [[TMP6:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>*
; SSE2-NEXT: store <2 x double> [[TMP5]], <2 x double>* [[TMP6]], align 4
; SSE2-NEXT: ret void
;
%from_1 = getelementptr double, double *%from, i64 1 %from_1 = getelementptr double, double *%from, i64 1
%v0_1 = load double , double * %from %v0_1 = load double , double * %from
%v0_2 = load double , double * %from_1 %v0_2 = load double , double * %from_1
%v1_1 = fadd double %v0_1, %v1 %v1_1 = fadd double %v0_1, %v1
%v1_2 = fadd double %v2, %v0_2 %v1_2 = fadd double %v2, %v0_2
%to_2 = getelementptr double, double * %to, i64 1 %to_2 = getelementptr double, double * %to, i64 1
store double %v1_1, double *%to store double %v1_1, double *%to
store double %v1_2, double *%to_2 store double %v1_2, double *%to_2
Show All 12 Lines
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP1]], <2 x i32> <i32 0, i32 2> ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP1]], <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP1]], [[TMP3]] ; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP1]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>* ; CHECK-NEXT: [[TMP5:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>*
; CHECK-NEXT: store <2 x double> [[TMP4]], <2 x double>* [[TMP5]], align 4 ; CHECK-NEXT: store <2 x double> [[TMP4]], <2 x double>* [[TMP5]], align 4
; CHECK-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]] ; CHECK-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]]
; CHECK: ext: ; CHECK: ext:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; SSE2-LABEL: @vecload_vs_broadcast(
; SSE2-NEXT: entry:
; SSE2-NEXT: br label [[LP:%.*]]
; SSE2: lp:
; SSE2-NEXT: [[P:%.*]] = phi double [ 1.000000e+00, [[LP]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; SSE2-NEXT: [[TMP0:%.*]] = bitcast double* [[FROM:%.*]] to <2 x double>*
; SSE2-NEXT: [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[TMP0]], align 4
; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[P]], i64 0
; SSE2-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP1]], <2 x i32> <i32 0, i32 2>
; SSE2-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP1]], [[TMP3]]
; SSE2-NEXT: [[TMP5:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>*
; SSE2-NEXT: store <2 x double> [[TMP4]], <2 x double>* [[TMP5]], align 4
; SSE2-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]]
; SSE2: ext:
; SSE2-NEXT: ret void
;
entry: entry:
br label %lp br label %lp
lp: lp:
%p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ] %p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ]
%from_1 = getelementptr double, double *%from, i64 1 %from_1 = getelementptr double, double *%from, i64 1
%v0_1 = load double , double * %from %v0_1 = load double , double * %from
%v0_2 = load double , double * %from_1 %v0_2 = load double , double * %from_1
Show All 20 Lines
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP1]], <2 x i32> <i32 0, i32 2> ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP1]], <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP3]], [[TMP1]] ; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP3]], [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>* ; CHECK-NEXT: [[TMP5:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>*
; CHECK-NEXT: store <2 x double> [[TMP4]], <2 x double>* [[TMP5]], align 4 ; CHECK-NEXT: store <2 x double> [[TMP4]], <2 x double>* [[TMP5]], align 4
; CHECK-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]] ; CHECK-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]]
; CHECK: ext: ; CHECK: ext:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; SSE2-LABEL: @vecload_vs_broadcast2(
; SSE2-NEXT: entry:
; SSE2-NEXT: br label [[LP:%.*]]
; SSE2: lp:
; SSE2-NEXT: [[P:%.*]] = phi double [ 1.000000e+00, [[LP]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; SSE2-NEXT: [[TMP0:%.*]] = bitcast double* [[FROM:%.*]] to <2 x double>*
; SSE2-NEXT: [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[TMP0]], align 4
; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[P]], i64 0
; SSE2-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP1]], <2 x i32> <i32 0, i32 2>
; SSE2-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP3]], [[TMP1]]
; SSE2-NEXT: [[TMP5:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>*
; SSE2-NEXT: store <2 x double> [[TMP4]], <2 x double>* [[TMP5]], align 4
; SSE2-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]]
; SSE2: ext:
; SSE2-NEXT: ret void
;
entry: entry:
br label %lp br label %lp
lp: lp:
%p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ] %p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ]
%from_1 = getelementptr double, double *%from, i64 1 %from_1 = getelementptr double, double *%from, i64 1
%v0_1 = load double , double * %from %v0_1 = load double , double * %from
%v0_2 = load double , double * %from_1 %v0_2 = load double , double * %from_1
Show All 20 Lines
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP1]], <2 x i32> <i32 0, i32 2> ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP1]], <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP3]], [[TMP1]] ; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP3]], [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>* ; CHECK-NEXT: [[TMP5:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>*
; CHECK-NEXT: store <2 x double> [[TMP4]], <2 x double>* [[TMP5]], align 4 ; CHECK-NEXT: store <2 x double> [[TMP4]], <2 x double>* [[TMP5]], align 4
; CHECK-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]] ; CHECK-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]]
; CHECK: ext: ; CHECK: ext:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; SSE2-LABEL: @vecload_vs_broadcast3(
; SSE2-NEXT: entry:
; SSE2-NEXT: br label [[LP:%.*]]
; SSE2: lp:
; SSE2-NEXT: [[P:%.*]] = phi double [ 1.000000e+00, [[LP]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; SSE2-NEXT: [[TMP0:%.*]] = bitcast double* [[FROM:%.*]] to <2 x double>*
; SSE2-NEXT: [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[TMP0]], align 4
; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[P]], i64 0
; SSE2-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP1]], <2 x i32> <i32 0, i32 2>
; SSE2-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP3]], [[TMP1]]
; SSE2-NEXT: [[TMP5:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>*
; SSE2-NEXT: store <2 x double> [[TMP4]], <2 x double>* [[TMP5]], align 4
; SSE2-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]]
; SSE2: ext:
; SSE2-NEXT: ret void
;
entry: entry:
br label %lp br label %lp
lp: lp:
%p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ] %p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ]
%from_1 = getelementptr double, double *%from, i64 1 %from_1 = getelementptr double, double *%from, i64 1
%v0_1 = load double , double * %from %v0_1 = load double , double * %from
%v0_2 = load double , double * %from_1 %v0_2 = load double , double * %from_1
Show All 20 Lines
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i64 1 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP2]], [[SHUFFLE]] ; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP2]], [[SHUFFLE]]
; CHECK-NEXT: [[TMP4:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>* ; CHECK-NEXT: [[TMP4:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>*
; CHECK-NEXT: store <2 x double> [[TMP3]], <2 x double>* [[TMP4]], align 4 ; CHECK-NEXT: store <2 x double> [[TMP3]], <2 x double>* [[TMP4]], align 4
; CHECK-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]] ; CHECK-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]]
; CHECK: ext: ; CHECK: ext:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; SSE2-LABEL: @shuffle_nodes_match1(
; SSE2-NEXT: entry:
; SSE2-NEXT: br label [[LP:%.*]]
; SSE2: lp:
; SSE2-NEXT: [[P:%.*]] = phi double [ 1.000000e+00, [[LP]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; SSE2-NEXT: [[TMP0:%.*]] = bitcast double* [[FROM:%.*]] to <2 x double>*
; SSE2-NEXT: [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[TMP0]], align 4
; SSE2-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i64 1
; SSE2-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP2]], [[SHUFFLE]]
; SSE2-NEXT: [[TMP4:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>*
; SSE2-NEXT: store <2 x double> [[TMP3]], <2 x double>* [[TMP4]], align 4
; SSE2-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]]
; SSE2: ext:
; SSE2-NEXT: ret void
;
entry: entry:
br label %lp br label %lp
lp: lp:
%p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ] %p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ]
%from_1 = getelementptr double, double *%from, i64 1 %from_1 = getelementptr double, double *%from, i64 1
%v0_1 = load double , double * %from %v0_1 = load double , double * %from
%v0_2 = load double , double * %from_1 %v0_2 = load double , double * %from_1
Show All 20 Lines
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i64 1 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP2]], [[SHUFFLE]] ; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP2]], [[SHUFFLE]]
; CHECK-NEXT: [[TMP4:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>* ; CHECK-NEXT: [[TMP4:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>*
; CHECK-NEXT: store <2 x double> [[TMP3]], <2 x double>* [[TMP4]], align 4 ; CHECK-NEXT: store <2 x double> [[TMP3]], <2 x double>* [[TMP4]], align 4
; CHECK-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]] ; CHECK-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]]
; CHECK: ext: ; CHECK: ext:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; SSE2-LABEL: @vecload_vs_broadcast4(
; SSE2-NEXT: entry:
; SSE2-NEXT: br label [[LP:%.*]]
; SSE2: lp:
; SSE2-NEXT: [[P:%.*]] = phi double [ 1.000000e+00, [[LP]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; SSE2-NEXT: [[TMP0:%.*]] = bitcast double* [[FROM:%.*]] to <2 x double>*
; SSE2-NEXT: [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[TMP0]], align 4
; SSE2-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i64 1
; SSE2-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP2]], [[SHUFFLE]]
; SSE2-NEXT: [[TMP4:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>*
; SSE2-NEXT: store <2 x double> [[TMP3]], <2 x double>* [[TMP4]], align 4
; SSE2-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]]
; SSE2: ext:
; SSE2-NEXT: ret void
;
entry: entry:
br label %lp br label %lp
lp: lp:
%p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ] %p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ]
%from_1 = getelementptr double, double *%from, i64 1 %from_1 = getelementptr double, double *%from, i64 1
%v0_1 = load double , double * %from %v0_1 = load double , double * %from
%v0_2 = load double , double * %from_1 %v0_2 = load double , double * %from_1
Show All 21 Lines
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i64 1 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[SHUFFLE]], [[TMP2]] ; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[SHUFFLE]], [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>* ; CHECK-NEXT: [[TMP4:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>*
; CHECK-NEXT: store <2 x double> [[TMP3]], <2 x double>* [[TMP4]], align 4 ; CHECK-NEXT: store <2 x double> [[TMP3]], <2 x double>* [[TMP4]], align 4
; CHECK-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]] ; CHECK-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]]
; CHECK: ext: ; CHECK: ext:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; SSE2-LABEL: @shuffle_nodes_match2(
; SSE2-NEXT: entry:
; SSE2-NEXT: br label [[LP:%.*]]
; SSE2: lp:
; SSE2-NEXT: [[P:%.*]] = phi double [ 1.000000e+00, [[LP]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; SSE2-NEXT: [[TMP0:%.*]] = bitcast double* [[FROM:%.*]] to <2 x double>*
; SSE2-NEXT: [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[TMP0]], align 4
; SSE2-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i64 1
; SSE2-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[SHUFFLE]], [[TMP2]]
; SSE2-NEXT: [[TMP4:%.*]] = bitcast double* [[TO:%.*]] to <2 x double>*
; SSE2-NEXT: store <2 x double> [[TMP3]], <2 x double>* [[TMP4]], align 4
; SSE2-NEXT: br i1 undef, label [[LP]], label [[EXT:%.*]]
; SSE2: ext:
; SSE2-NEXT: ret void
;
entry: entry:
br label %lp br label %lp
lp: lp:
%p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ] %p = phi double [ 1.000000e+00, %lp ], [ 0.000000e+00, %entry ]
%from_1 = getelementptr double, double *%from, i64 1 %from_1 = getelementptr double, double *%from, i64 1
%v0_1 = load double , double * %from %v0_1 = load double , double * %from
%v0_2 = load double , double * %from_1 %v0_2 = load double , double * %from_1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[MUL45:%.*]] = fmul float [[TMP14]], [[TMP15]] ; CHECK-NEXT: [[MUL45:%.*]] = fmul float [[TMP14]], [[TMP15]]
; CHECK-NEXT: store float [[MUL45]], float* [[ARRAYIDX31]], align 4 ; CHECK-NEXT: store float [[MUL45]], float* [[ARRAYIDX31]], align 4
; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32 ; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP16]], 31995 ; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP16]], 31995
; CHECK-NEXT: br i1 [[CMP2]], label [[FOR_BODY3]], label [[FOR_END:%.*]] ; CHECK-NEXT: br i1 [[CMP2]], label [[FOR_BODY3]], label [[FOR_END:%.*]]
; CHECK: for.end: ; CHECK: for.end:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; SSE2-LABEL: @good_load_order(
; SSE2-NEXT: entry:
; SSE2-NEXT: br label [[FOR_COND1_PREHEADER:%.*]]
; SSE2: for.cond1.preheader:
; SSE2-NEXT: [[TMP0:%.*]] = load float, float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i32 0, i32 0), align 16
; SSE2-NEXT: br label [[FOR_BODY3:%.*]]
; SSE2: for.body3:
; SSE2-NEXT: [[TMP1:%.*]] = phi float [ [[TMP0]], [[FOR_COND1_PREHEADER]] ], [ [[TMP14:%.*]], [[FOR_BODY3]] ]
; SSE2-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_COND1_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY3]] ]
; SSE2-NEXT: [[TMP2:%.*]] = trunc i64 [[INDVARS_IV]] to i32
; SSE2-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], 1
; SSE2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [32000 x float], [32000 x float]* @a, i32 0, i32 [[TMP3]]
; SSE2-NEXT: [[TMP4:%.*]] = trunc i64 [[INDVARS_IV]] to i32
; SSE2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [32000 x float], [32000 x float]* @a, i32 0, i32 [[TMP4]]
; SSE2-NEXT: [[TMP5:%.*]] = trunc i64 [[INDVARS_IV]] to i32
; SSE2-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 4
; SSE2-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds [32000 x float], [32000 x float]* @a, i32 0, i32 [[TMP6]]
; SSE2-NEXT: [[TMP7:%.*]] = bitcast float* [[ARRAYIDX]] to <4 x float>*
; SSE2-NEXT: [[TMP8:%.*]] = load <4 x float>, <4 x float>* [[TMP7]], align 4
; SSE2-NEXT: [[TMP9:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i64 0
; SSE2-NEXT: [[TMP10:%.*]] = shufflevector <4 x float> [[TMP9]], <4 x float> [[TMP8]], <4 x i32> <i32 0, i32 4, i32 5, i32 6>
; SSE2-NEXT: [[TMP11:%.*]] = fmul <4 x float> [[TMP8]], [[TMP10]]
; SSE2-NEXT: [[TMP12:%.*]] = bitcast float* [[ARRAYIDX5]] to <4 x float>*
; SSE2-NEXT: store <4 x float> [[TMP11]], <4 x float>* [[TMP12]], align 4
; SSE2-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 5
; SSE2-NEXT: [[TMP13:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
; SSE2-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds [32000 x float], [32000 x float]* @a, i32 0, i32 [[TMP13]]
; SSE2-NEXT: [[TMP14]] = load float, float* [[ARRAYIDX41]], align 4
; SSE2-NEXT: [[TMP15:%.*]] = extractelement <4 x float> [[TMP8]], i64 3
; SSE2-NEXT: [[MUL45:%.*]] = fmul float [[TMP14]], [[TMP15]]
; SSE2-NEXT: store float [[MUL45]], float* [[ARRAYIDX31]], align 4
; SSE2-NEXT: [[TMP16:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
; SSE2-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP16]], 31995
; SSE2-NEXT: br i1 [[CMP2]], label [[FOR_BODY3]], label [[FOR_END:%.*]]
; SSE2: for.end:
; SSE2-NEXT: ret void
;
entry: entry:
br label %for.cond1.preheader br label %for.cond1.preheader
for.cond1.preheader: for.cond1.preheader:
%0 = load float, float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), align 16 %0 = load float, float* getelementptr inbounds ([32000 x float], [32000 x float]* @a, i64 0, i64 0), align 16
br label %for.body3 br label %for.body3
for.body3: for.body3:
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, <2 x double>* [[TMP1]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, <2 x double>* [[TMP1]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = bitcast double* [[A:%.*]] to <2 x double>* ; CHECK-NEXT: [[TMP3:%.*]] = bitcast double* [[A:%.*]] to <2 x double>*
; CHECK-NEXT: [[TMP4:%.*]] = load <2 x double>, <2 x double>* [[TMP3]], align 4 ; CHECK-NEXT: [[TMP4:%.*]] = load <2 x double>, <2 x double>* [[TMP3]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = fadd <2 x double> [[TMP2]], [[TMP4]] ; CHECK-NEXT: [[TMP5:%.*]] = fadd <2 x double> [[TMP2]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = bitcast double* [[C:%.*]] to <2 x double>* ; CHECK-NEXT: [[TMP6:%.*]] = bitcast double* [[C:%.*]] to <2 x double>*
; CHECK-NEXT: store <2 x double> [[TMP5]], <2 x double>* [[TMP6]], align 4 ; CHECK-NEXT: store <2 x double> [[TMP5]], <2 x double>* [[TMP6]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; SSE2-LABEL: @load_reorder_double(
; SSE2-NEXT: [[TMP1:%.*]] = bitcast double* [[B:%.*]] to <2 x double>*
; SSE2-NEXT: [[TMP2:%.*]] = load <2 x double>, <2 x double>* [[TMP1]], align 4
; SSE2-NEXT: [[TMP3:%.*]] = bitcast double* [[A:%.*]] to <2 x double>*
; SSE2-NEXT: [[TMP4:%.*]] = load <2 x double>, <2 x double>* [[TMP3]], align 4
; SSE2-NEXT: [[TMP5:%.*]] = fadd <2 x double> [[TMP2]], [[TMP4]]
; SSE2-NEXT: [[TMP6:%.*]] = bitcast double* [[C:%.*]] to <2 x double>*
; SSE2-NEXT: store <2 x double> [[TMP5]], <2 x double>* [[TMP6]], align 4
; SSE2-NEXT: ret void
;
%1 = load double, double* %a %1 = load double, double* %a
%2 = load double, double* %b %2 = load double, double* %b
%3 = fadd double %1, %2 %3 = fadd double %1, %2
store double %3, double* %c store double %3, double* %c
%4 = getelementptr inbounds double, double* %b, i64 1 %4 = getelementptr inbounds double, double* %b, i64 1
%5 = load double, double* %4 %5 = load double, double* %4
%6 = getelementptr inbounds double, double* %a, i64 1 %6 = getelementptr inbounds double, double* %a, i64 1
%7 = load double, double* %6 %7 = load double, double* %6
Show All 15 Lines
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[B:%.*]] to <4 x float>* ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[B:%.*]] to <4 x float>*
; CHECK-NEXT: [[TMP4:%.*]] = load <4 x float>, <4 x float>* [[TMP3]], align 4 ; CHECK-NEXT: [[TMP4:%.*]] = load <4 x float>, <4 x float>* [[TMP3]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = fadd <4 x float> [[TMP2]], [[TMP4]] ; CHECK-NEXT: [[TMP5:%.*]] = fadd <4 x float> [[TMP2]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = bitcast float* [[C:%.*]] to <4 x float>* ; CHECK-NEXT: [[TMP6:%.*]] = bitcast float* [[C:%.*]] to <4 x float>*
; CHECK-NEXT: store <4 x float> [[TMP5]], <4 x float>* [[TMP6]], align 4 ; CHECK-NEXT: store <4 x float> [[TMP5]], <4 x float>* [[TMP6]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; SSE2-LABEL: @load_reorder_float(
; SSE2-NEXT: [[TMP1:%.*]] = bitcast float* [[A:%.*]] to <4 x float>*
; SSE2-NEXT: [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
; SSE2-NEXT: [[TMP3:%.*]] = bitcast float* [[B:%.*]] to <4 x float>*
; SSE2-NEXT: [[TMP4:%.*]] = load <4 x float>, <4 x float>* [[TMP3]], align 4
; SSE2-NEXT: [[TMP5:%.*]] = fadd <4 x float> [[TMP2]], [[TMP4]]
; SSE2-NEXT: [[TMP6:%.*]] = bitcast float* [[C:%.*]] to <4 x float>*
; SSE2-NEXT: store <4 x float> [[TMP5]], <4 x float>* [[TMP6]], align 4
; SSE2-NEXT: ret void
;
%1 = load float, float* %a %1 = load float, float* %a
%2 = load float, float* %b %2 = load float, float* %b
%3 = fadd float %1, %2 %3 = fadd float %1, %2
store float %3, float* %c store float %3, float* %c
%4 = getelementptr inbounds float, float* %b, i64 1 %4 = getelementptr inbounds float, float* %b, i64 1
%5 = load float, float* %4 %5 = load float, float* %4
%6 = getelementptr inbounds float, float* %a, i64 1 %6 = getelementptr inbounds float, float* %a, i64 1
%7 = load float, float* %6 %7 = load float, float* %6
Show All 32 Lines
; CHECK-NEXT: [[TMP5:%.*]] = fadd <4 x float> [[TMP2]], [[TMP4]] ; CHECK-NEXT: [[TMP5:%.*]] = fadd <4 x float> [[TMP2]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = bitcast float* [[D:%.*]] to <4 x float>* ; CHECK-NEXT: [[TMP6:%.*]] = bitcast float* [[D:%.*]] to <4 x float>*
; CHECK-NEXT: [[TMP7:%.*]] = load <4 x float>, <4 x float>* [[TMP6]], align 4 ; CHECK-NEXT: [[TMP7:%.*]] = load <4 x float>, <4 x float>* [[TMP6]], align 4
; CHECK-NEXT: [[TMP8:%.*]] = fadd <4 x float> [[TMP7]], [[TMP5]] ; CHECK-NEXT: [[TMP8:%.*]] = fadd <4 x float> [[TMP7]], [[TMP5]]
; CHECK-NEXT: [[TMP9:%.*]] = bitcast float* [[A:%.*]] to <4 x float>* ; CHECK-NEXT: [[TMP9:%.*]] = bitcast float* [[A:%.*]] to <4 x float>*
; CHECK-NEXT: store <4 x float> [[TMP8]], <4 x float>* [[TMP9]], align 4 ; CHECK-NEXT: store <4 x float> [[TMP8]], <4 x float>* [[TMP9]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; SSE2-LABEL: @opcode_reorder(
; SSE2-NEXT: [[TMP1:%.*]] = bitcast float* [[B:%.*]] to <4 x float>*
; SSE2-NEXT: [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
; SSE2-NEXT: [[TMP3:%.*]] = bitcast float* [[C:%.*]] to <4 x float>*
; SSE2-NEXT: [[TMP4:%.*]] = load <4 x float>, <4 x float>* [[TMP3]], align 4
; SSE2-NEXT: [[TMP5:%.*]] = fadd <4 x float> [[TMP2]], [[TMP4]]
; SSE2-NEXT: [[TMP6:%.*]] = bitcast float* [[D:%.*]] to <4 x float>*
; SSE2-NEXT: [[TMP7:%.*]] = load <4 x float>, <4 x float>* [[TMP6]], align 4
; SSE2-NEXT: [[TMP8:%.*]] = fadd <4 x float> [[TMP7]], [[TMP5]]
; SSE2-NEXT: [[TMP9:%.*]] = bitcast float* [[A:%.*]] to <4 x float>*
; SSE2-NEXT: store <4 x float> [[TMP8]], <4 x float>* [[TMP9]], align 4
; SSE2-NEXT: ret void
;
%1 = load float, float* %b %1 = load float, float* %b
%2 = load float, float* %c %2 = load float, float* %c
%3 = fadd float %1, %2 %3 = fadd float %1, %2
%4 = load float, float* %d %4 = load float, float* %d
%5 = fadd float %3, %4 %5 = fadd float %3, %4
store float %5, float* %a store float %5, float* %a
%6 = getelementptr inbounds float, float* %d, i64 1 %6 = getelementptr inbounds float, float* %d, i64 1
%7 = load float, float* %6 %7 = load float, float* %6
Show All 30 Lines