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[OpenMP][FIX] Ensure custom state machine works
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Authored by jdoerfert on Mar 4 2022, 10:05 AM.

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jhuber6
jdenny

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rGf9c2d6005ef0: [OpenMP][FIX] Ensure custom state machine works

Summary

The custom state machine had a check for surplus threads that filtered
the main thread if the kernel was executed by a single warp only. We
now first check for the main thread, then for surplus threads, avoiding
to filter the former out.

Fixes #54214.

Diff Detail

Repository: rG LLVM Github Monorepo

Event Timeline

jdoerfert created this revision.Mar 4 2022, 10:05 AM

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jdoerfert requested review of this revision.Mar 4 2022, 10:05 AM

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Fix comment

LGTM, fixes the issue and passed tests.

This revision is now accepted and ready to land.Mar 4 2022, 10:12 AM

Harbormaster completed remote builds in B152624: Diff 413056.Mar 4 2022, 10:32 AM

This revision was landed with ongoing or failed builds.Mar 4 2022, 10:51 AM

Closed by commit rGf9c2d6005ef0: [OpenMP][FIX] Ensure custom state machine works (authored by jdoerfert, committed by jhuber6). · Explain Why

This revision was automatically updated to reflect the committed changes.

jhuber6 added a commit: rGf9c2d6005ef0: [OpenMP][FIX] Ensure custom state machine works.

Revision Contents

Path

Size

llvm/

lib/

Transforms/

IPO/

OpenMPOpt.cpp

38 lines

test/

Transforms/

OpenMP/

custom_state_machines.ll

112 lines

spmdization.ll

128 lines

spmdization_guarding.ll

8 lines

spmdization_guarding_two_reaching_kernels.ll

8 lines

Diff 413073

llvm/lib/Transforms/IPO/OpenMPOpt.cpp

Show First 20 Lines • Show All 3,727 Lines • ▼ Show 20 Lines	ChangeStatus buildCustomStateMachine(Attributor &A) {

// Create all the blocks:		// Create all the blocks:
//		//
// InitCB = __kmpc_target_init(...)		// InitCB = __kmpc_target_init(...)
// BlockHwSize =		// BlockHwSize =
// __kmpc_get_hardware_num_threads_in_block();		// __kmpc_get_hardware_num_threads_in_block();
// WarpSize = __kmpc_get_warp_size();		// WarpSize = __kmpc_get_warp_size();
// BlockSize = BlockHwSize - WarpSize;		// BlockSize = BlockHwSize - WarpSize;
// if (InitCB >= BlockSize) return;		// IsWorkerCheckBB: bool IsWorker = InitCB != -1;
// IsWorkerCheckBB: bool IsWorker = InitCB >= 0;
// if (IsWorker) {		// if (IsWorker) {
		// if (InitCB >= BlockSize) return;
// SMBeginBB: __kmpc_barrier_simple_generic(...);		// SMBeginBB: __kmpc_barrier_simple_generic(...);
// void *WorkFn;		// void *WorkFn;
// bool Active = __kmpc_kernel_parallel(&WorkFn);		// bool Active = __kmpc_kernel_parallel(&WorkFn);
// if (!WorkFn) return;		// if (!WorkFn) return;
// SMIsActiveCheckBB: if (Active) {		// SMIsActiveCheckBB: if (Active) {
// SMIfCascadeCurrentBB: if (WorkFn == <ParFn0>)		// SMIfCascadeCurrentBB: if (WorkFn == <ParFn0>)
// ParFn0(...);		// ParFn0(...);
// SMIfCascadeCurrentBB: else if (WorkFn == <ParFn1>)		// SMIfCascadeCurrentBB: else if (WorkFn == <ParFn1>)
Show All 40 Lines	ChangeStatus buildCustomStateMachine(Attributor &A) {
A.registerManifestAddedBasicBlock(*StateMachineIfCascadeCurrentBB);		A.registerManifestAddedBasicBlock(*StateMachineIfCascadeCurrentBB);
A.registerManifestAddedBasicBlock(*StateMachineEndParallelBB);		A.registerManifestAddedBasicBlock(*StateMachineEndParallelBB);
A.registerManifestAddedBasicBlock(*StateMachineDoneBarrierBB);		A.registerManifestAddedBasicBlock(*StateMachineDoneBarrierBB);

const DebugLoc &DLoc = KernelInitCB->getDebugLoc();		const DebugLoc &DLoc = KernelInitCB->getDebugLoc();
ReturnInst::Create(Ctx, StateMachineFinishedBB)->setDebugLoc(DLoc);		ReturnInst::Create(Ctx, StateMachineFinishedBB)->setDebugLoc(DLoc);
InitBB->getTerminator()->eraseFromParent();		InitBB->getTerminator()->eraseFromParent();

		Instruction *IsWorker =
		ICmpInst::Create(ICmpInst::ICmp, llvm::CmpInst::ICMP_NE, KernelInitCB,
		ConstantInt::get(KernelInitCB->getType(), -1),
		"thread.is_worker", InitBB);
		IsWorker->setDebugLoc(DLoc);
		BranchInst::Create(IsWorkerCheckBB, UserCodeEntryBB, IsWorker, InitBB);

Module &M = *Kernel->getParent();		Module &M = *Kernel->getParent();
auto &OMPInfoCache = static_cast<OMPInformationCache &>(A.getInfoCache());		auto &OMPInfoCache = static_cast<OMPInformationCache &>(A.getInfoCache());
FunctionCallee BlockHwSizeFn =		FunctionCallee BlockHwSizeFn =
OMPInfoCache.OMPBuilder.getOrCreateRuntimeFunction(		OMPInfoCache.OMPBuilder.getOrCreateRuntimeFunction(
M, OMPRTL___kmpc_get_hardware_num_threads_in_block);		M, OMPRTL___kmpc_get_hardware_num_threads_in_block);
FunctionCallee WarpSizeFn =		FunctionCallee WarpSizeFn =
OMPInfoCache.OMPBuilder.getOrCreateRuntimeFunction(		OMPInfoCache.OMPBuilder.getOrCreateRuntimeFunction(
M, OMPRTL___kmpc_get_warp_size);		M, OMPRTL___kmpc_get_warp_size);
CallInst *BlockHwSize =		CallInst *BlockHwSize =
CallInst::Create(BlockHwSizeFn, "block.hw_size", InitBB);		CallInst::Create(BlockHwSizeFn, "block.hw_size", IsWorkerCheckBB);
OMPInfoCache.setCallingConvention(BlockHwSizeFn, BlockHwSize);		OMPInfoCache.setCallingConvention(BlockHwSizeFn, BlockHwSize);
BlockHwSize->setDebugLoc(DLoc);		BlockHwSize->setDebugLoc(DLoc);
CallInst *WarpSize = CallInst::Create(WarpSizeFn, "warp.size", InitBB);		CallInst *WarpSize =
		CallInst::Create(WarpSizeFn, "warp.size", IsWorkerCheckBB);
OMPInfoCache.setCallingConvention(WarpSizeFn, WarpSize);		OMPInfoCache.setCallingConvention(WarpSizeFn, WarpSize);
WarpSize->setDebugLoc(DLoc);		WarpSize->setDebugLoc(DLoc);
Instruction *BlockSize =		Instruction *BlockSize = BinaryOperator::CreateSub(
BinaryOperator::CreateSub(BlockHwSize, WarpSize, "block.size", InitBB);		BlockHwSize, WarpSize, "block.size", IsWorkerCheckBB);
BlockSize->setDebugLoc(DLoc);		BlockSize->setDebugLoc(DLoc);
Instruction *IsMainOrWorker =		Instruction *IsMainOrWorker = ICmpInst::Create(
ICmpInst::Create(ICmpInst::ICmp, llvm::CmpInst::ICMP_SLT, KernelInitCB,		ICmpInst::ICmp, llvm::CmpInst::ICMP_SLT, KernelInitCB, BlockSize,
BlockSize, "thread.is_main_or_worker", InitBB);		"thread.is_main_or_worker", IsWorkerCheckBB);
IsMainOrWorker->setDebugLoc(DLoc);		IsMainOrWorker->setDebugLoc(DLoc);
BranchInst::Create(IsWorkerCheckBB, StateMachineFinishedBB, IsMainOrWorker,		BranchInst::Create(StateMachineBeginBB, StateMachineFinishedBB,
InitBB);		IsMainOrWorker, IsWorkerCheckBB);

Instruction *IsWorker =
ICmpInst::Create(ICmpInst::ICmp, llvm::CmpInst::ICMP_NE, KernelInitCB,
ConstantInt::get(KernelInitCB->getType(), -1),
"thread.is_worker", IsWorkerCheckBB);
IsWorker->setDebugLoc(DLoc);
BranchInst::Create(StateMachineBeginBB, UserCodeEntryBB, IsWorker,
IsWorkerCheckBB);

// Create local storage for the work function pointer.		// Create local storage for the work function pointer.
const DataLayout &DL = M.getDataLayout();		const DataLayout &DL = M.getDataLayout();
Type *VoidPtrTy = Type::getInt8PtrTy(Ctx);		Type *VoidPtrTy = Type::getInt8PtrTy(Ctx);
Instruction *WorkFnAI =		Instruction *WorkFnAI =
new AllocaInst(VoidPtrTy, DL.getAllocaAddrSpace(), nullptr,		new AllocaInst(VoidPtrTy, DL.getAllocaAddrSpace(), nullptr,
"worker.work_fn.addr", &Kernel->getEntryBlock().front());		"worker.work_fn.addr", &Kernel->getEntryBlock().front());
WorkFnAI->setDebugLoc(DLoc);		WorkFnAI->setDebugLoc(DLoc);
▲ Show 20 Lines • Show All 1,361 Lines • Show Last 20 Lines

llvm/test/Transforms/OpenMP/custom_state_machines.ll

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 906 Lines • ▼ Show 20 Lines
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22			; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22
	; AMDGPU-SAME: () #[[ATTR0]] {			; AMDGPU-SAME: () #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; AMDGPU: worker_state_machine.begin:			; AMDGPU: worker_state_machine.begin:
	; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**
	; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])			; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8			; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39			; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39
	; AMDGPU-SAME: () #[[ATTR0]] {			; AMDGPU-SAME: () #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; AMDGPU: worker_state_machine.begin:			; AMDGPU: worker_state_machine.begin:
	; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**
	; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])			; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8			; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
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	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55			; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55
	; AMDGPU-SAME: () #[[ATTR0]] {			; AMDGPU-SAME: () #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; AMDGPU: worker_state_machine.begin:			; AMDGPU: worker_state_machine.begin:
	; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**
	; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])			; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8			; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
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	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66			; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
	; AMDGPU-SAME: () #[[ATTR0]] {			; AMDGPU-SAME: () #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; AMDGPU: worker_state_machine.begin:			; AMDGPU: worker_state_machine.begin:
	; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**
	; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])			; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8			; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
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	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77			; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
	; AMDGPU-SAME: () #[[ATTR0]] {			; AMDGPU-SAME: () #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; AMDGPU: worker_state_machine.begin:			; AMDGPU: worker_state_machine.begin:
	; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**
	; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])			; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8			; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
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	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92			; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92
	; AMDGPU-SAME: () #[[ATTR0]] {			; AMDGPU-SAME: () #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; AMDGPU: worker_state_machine.begin:			; AMDGPU: worker_state_machine.begin:
	; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**
	; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])			; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8			; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
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	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112			; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112
	; AMDGPU-SAME: () #[[ATTR0]] {			; AMDGPU-SAME: () #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; AMDGPU: worker_state_machine.begin:			; AMDGPU: worker_state_machine.begin:
	; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**
	; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])			; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8			; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
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	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22			; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22
	; NVPTX-SAME: () #[[ATTR0]] {			; NVPTX-SAME: () #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; NVPTX: worker_state_machine.begin:			; NVPTX: worker_state_machine.begin:
	; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; NVPTX: worker_state_machine.finished:			; NVPTX: worker_state_machine.finished:
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	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39			; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39
	; NVPTX-SAME: () #[[ATTR0]] {			; NVPTX-SAME: () #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; NVPTX: worker_state_machine.begin:			; NVPTX: worker_state_machine.begin:
	; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; NVPTX: worker_state_machine.finished:			; NVPTX: worker_state_machine.finished:
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	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55			; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55
	; NVPTX-SAME: () #[[ATTR0]] {			; NVPTX-SAME: () #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; NVPTX: worker_state_machine.begin:			; NVPTX: worker_state_machine.begin:
	; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; NVPTX: worker_state_machine.finished:			; NVPTX: worker_state_machine.finished:
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	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66			; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
	; NVPTX-SAME: () #[[ATTR0]] {			; NVPTX-SAME: () #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; NVPTX: worker_state_machine.begin:			; NVPTX: worker_state_machine.begin:
	; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; NVPTX: worker_state_machine.finished:			; NVPTX: worker_state_machine.finished:
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	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77			; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
	; NVPTX-SAME: () #[[ATTR0]] {			; NVPTX-SAME: () #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; NVPTX: worker_state_machine.begin:			; NVPTX: worker_state_machine.begin:
	; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; NVPTX: worker_state_machine.finished:			; NVPTX: worker_state_machine.finished:
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	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92			; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92
	; NVPTX-SAME: () #[[ATTR0]] {			; NVPTX-SAME: () #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; NVPTX: worker_state_machine.begin:			; NVPTX: worker_state_machine.begin:
	; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; NVPTX: worker_state_machine.finished:			; NVPTX: worker_state_machine.finished:
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	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112			; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112
	; NVPTX-SAME: () #[[ATTR0]] {			; NVPTX-SAME: () #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; NVPTX: worker_state_machine.begin:			; NVPTX: worker_state_machine.begin:
	; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; NVPTX: worker_state_machine.finished:			; NVPTX: worker_state_machine.finished:
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llvm/test/Transforms/OpenMP/spmdization.ll

	Show First 20 Lines • Show All 202 Lines • ▼ Show 20 Lines
	;			;
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_l5			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_l5
	; AMDGPU-DISABLED-SAME: () #[[ATTR0:[0-9]+]] {			; AMDGPU-DISABLED-SAME: () #[[ATTR0:[0-9]+]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; AMDGPU-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; AMDGPU-DISABLED: is_worker_check:
	; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; AMDGPU-DISABLED: is_worker_check:
	; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; AMDGPU-DISABLED: worker_state_machine.begin:			; AMDGPU-DISABLED: worker_state_machine.begin:
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**
	; AMDGPU-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])			; AMDGPU-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; AMDGPU-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; AMDGPU-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; AMDGPU-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; AMDGPU-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	Show All 30 Lines
	;			;
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_l5			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_l5
	; NVPTX-DISABLED-SAME: () #[[ATTR0:[0-9]+]] {			; NVPTX-DISABLED-SAME: () #[[ATTR0:[0-9]+]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; NVPTX-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; NVPTX-DISABLED: is_worker_check:
	; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; NVPTX-DISABLED: is_worker_check:
	; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; NVPTX-DISABLED: worker_state_machine.begin:			; NVPTX-DISABLED: worker_state_machine.begin:
	; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; NVPTX-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; NVPTX-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; NVPTX-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; NVPTX-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; NVPTX-DISABLED: worker_state_machine.finished:			; NVPTX-DISABLED: worker_state_machine.finished:
	▲ Show 20 Lines • Show All 267 Lines • ▼ Show 20 Lines
	;			;
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20
	; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; AMDGPU-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; AMDGPU-DISABLED: is_worker_check:
	; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; AMDGPU-DISABLED: is_worker_check:
	; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; AMDGPU-DISABLED: worker_state_machine.begin:			; AMDGPU-DISABLED: worker_state_machine.begin:
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**
	; AMDGPU-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])			; AMDGPU-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; AMDGPU-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; AMDGPU-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; AMDGPU-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; AMDGPU-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	Show All 30 Lines
	;			;
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20
	; NVPTX-DISABLED-SAME: () #[[ATTR0]] {			; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; NVPTX-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; NVPTX-DISABLED: is_worker_check:
	; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; NVPTX-DISABLED: is_worker_check:
	; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; NVPTX-DISABLED: worker_state_machine.begin:			; NVPTX-DISABLED: worker_state_machine.begin:
	; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; NVPTX-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; NVPTX-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; NVPTX-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; NVPTX-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; NVPTX-DISABLED: worker_state_machine.finished:			; NVPTX-DISABLED: worker_state_machine.finished:
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	;			;
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35
	; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; AMDGPU-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; AMDGPU-DISABLED: is_worker_check:
	; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; AMDGPU-DISABLED: is_worker_check:
	; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; AMDGPU-DISABLED: worker_state_machine.begin:			; AMDGPU-DISABLED: worker_state_machine.begin:
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**
	; AMDGPU-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])			; AMDGPU-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; AMDGPU-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; AMDGPU-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; AMDGPU-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; AMDGPU-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	Show All 30 Lines
	;			;
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35
	; NVPTX-DISABLED-SAME: () #[[ATTR0]] {			; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; NVPTX-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; NVPTX-DISABLED: is_worker_check:
	; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; NVPTX-DISABLED: is_worker_check:
	; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; NVPTX-DISABLED: worker_state_machine.begin:			; NVPTX-DISABLED: worker_state_machine.begin:
	; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; NVPTX-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; NVPTX-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; NVPTX-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; NVPTX-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; NVPTX-DISABLED: worker_state_machine.finished:			; NVPTX-DISABLED: worker_state_machine.finished:
	▲ Show 20 Lines • Show All 310 Lines • ▼ Show 20 Lines
	;			;
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50
	; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; AMDGPU-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; AMDGPU-DISABLED: is_worker_check:
	; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; AMDGPU-DISABLED: is_worker_check:
	; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; AMDGPU-DISABLED: worker_state_machine.begin:			; AMDGPU-DISABLED: worker_state_machine.begin:
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**
	; AMDGPU-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])			; AMDGPU-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; AMDGPU-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; AMDGPU-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; AMDGPU-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; AMDGPU-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	Show All 30 Lines
	;			;
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50
	; NVPTX-DISABLED-SAME: () #[[ATTR0]] {			; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; NVPTX-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; NVPTX-DISABLED: is_worker_check:
	; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; NVPTX-DISABLED: is_worker_check:
	; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; NVPTX-DISABLED: worker_state_machine.begin:			; NVPTX-DISABLED: worker_state_machine.begin:
	; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; NVPTX-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; NVPTX-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; NVPTX-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; NVPTX-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; NVPTX-DISABLED: worker_state_machine.finished:			; NVPTX-DISABLED: worker_state_machine.finished:
	▲ Show 20 Lines • Show All 311 Lines • ▼ Show 20 Lines
	define weak void @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65() #0 {			define weak void @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65() #0 {
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65			; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65
	; AMDGPU-SAME: () #[[ATTR0]] {			; AMDGPU-SAME: () #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; AMDGPU: worker_state_machine.begin:			; AMDGPU: worker_state_machine.begin:
	; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**
	; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])			; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8			; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	Show All 23 Lines
	;			;
	; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65			; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65
	; NVPTX-SAME: () #[[ATTR0]] {			; NVPTX-SAME: () #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; NVPTX: worker_state_machine.begin:			; NVPTX: worker_state_machine.begin:
	; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; NVPTX: worker_state_machine.finished:			; NVPTX: worker_state_machine.finished:
	Show All 22 Lines
	;			;
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65
	; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; AMDGPU-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; AMDGPU-DISABLED: is_worker_check:
	; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; AMDGPU-DISABLED: is_worker_check:
	; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; AMDGPU-DISABLED: worker_state_machine.begin:			; AMDGPU-DISABLED: worker_state_machine.begin:
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**
	; AMDGPU-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])			; AMDGPU-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; AMDGPU-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; AMDGPU-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; AMDGPU-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; AMDGPU-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	Show All 23 Lines
	;			;
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65
	; NVPTX-DISABLED-SAME: () #[[ATTR0]] {			; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; NVPTX-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; NVPTX-DISABLED: is_worker_check:
	; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; NVPTX-DISABLED: is_worker_check:
	; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; NVPTX-DISABLED: worker_state_machine.begin:			; NVPTX-DISABLED: worker_state_machine.begin:
	; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; NVPTX-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; NVPTX-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; NVPTX-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; NVPTX-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; NVPTX-DISABLED: worker_state_machine.finished:			; NVPTX-DISABLED: worker_state_machine.finished:
	▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
	; Function Attrs: alwaysinline convergent norecurse nounwind			; Function Attrs: alwaysinline convergent norecurse nounwind
	define weak void @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74() #0 {			define weak void @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74() #0 {
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74			; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74
	; AMDGPU-SAME: () #[[ATTR0]] {			; AMDGPU-SAME: () #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)
	; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 8			; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 8
	; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; AMDGPU-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; AMDGPU: is_worker_check:
	; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; AMDGPU: worker_state_machine.begin:			; AMDGPU: worker_state_machine.begin:
	; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**
	; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])			; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])
	; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8			; AMDGPU-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
	; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; AMDGPU-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	Show All 32 Lines
	; AMDGPU-NEXT: br label [[COMMON_RET]]			; AMDGPU-NEXT: br label [[COMMON_RET]]
	;			;
	; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74			; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74
	; NVPTX-SAME: () #[[ATTR0]] {			; NVPTX-SAME: () #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 8			; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 8
	; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; NVPTX-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; NVPTX: is_worker_check:
	; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; NVPTX: worker_state_machine.begin:			; NVPTX: worker_state_machine.begin:
	; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; NVPTX-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; NVPTX-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; NVPTX-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; NVPTX: worker_state_machine.finished:			; NVPTX: worker_state_machine.finished:
	Show All 31 Lines
	; NVPTX-NEXT: br label [[COMMON_RET]]			; NVPTX-NEXT: br label [[COMMON_RET]]
	;			;
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74
	; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8, addrspace(5)
	; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 8			; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 8
	; AMDGPU-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; AMDGPU-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; AMDGPU-DISABLED: is_worker_check:
	; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; AMDGPU-DISABLED: is_worker_check:
	; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; AMDGPU-DISABLED: worker_state_machine.begin:			; AMDGPU-DISABLED: worker_state_machine.begin:
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.]] = addrspacecast i8 addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8**
	; AMDGPU-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])			; AMDGPU-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR_GENERIC]])
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
	; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; AMDGPU-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; AMDGPU-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; AMDGPU-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; AMDGPU-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	Show All 32 Lines
	; AMDGPU-DISABLED-NEXT: br label [[COMMON_RET]]			; AMDGPU-DISABLED-NEXT: br label [[COMMON_RET]]
	;			;
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74
	; NVPTX-DISABLED-SAME: () #[[ATTR0]] {			; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 8			; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [0 x i8], align 8
	; NVPTX-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; NVPTX-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; NVPTX-DISABLED: is_worker_check:
	; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; NVPTX-DISABLED: is_worker_check:
	; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; NVPTX-DISABLED: worker_state_machine.begin:			; NVPTX-DISABLED: worker_state_machine.begin:
	; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; NVPTX-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; NVPTX-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; NVPTX-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; NVPTX-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; NVPTX-DISABLED: worker_state_machine.finished:			; NVPTX-DISABLED: worker_state_machine.finished:
	▲ Show 20 Lines • Show All 455 Lines • Show Last 20 Lines

llvm/test/Transforms/OpenMP/spmdization_guarding.ll

	Show First 20 Lines • Show All 172 Lines • ▼ Show 20 Lines
	; CHECK-NEXT: ret void			; CHECK-NEXT: ret void
	;			;
	; CHECK-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_2a_fbfa7a_sequential_loop_l6			; CHECK-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_2a_fbfa7a_sequential_loop_l6
	; CHECK-DISABLED-SAME: (i32* [[X:%.]], i64 [[N:%.]]) #[[ATTR0:[0-9]+]] {			; CHECK-DISABLED-SAME: (i32* [[X:%.]], i64 [[N:%.]]) #[[ATTR0:[0-9]+]] {
	; CHECK-DISABLED-NEXT: entry:			; CHECK-DISABLED-NEXT: entry:
	; CHECK-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; CHECK-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; CHECK-DISABLED-NEXT: [[N_ADDR_SROA_0_0_EXTRACT_TRUNC:%.*]] = trunc i64 [[N]] to i32			; CHECK-DISABLED-NEXT: [[N_ADDR_SROA_0_0_EXTRACT_TRUNC:%.*]] = trunc i64 [[N]] to i32
	; CHECK-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t nonnull @[[GLOB1]], i8 1, i1 false, i1 true) #[[ATTR4:[0-9]+]]			; CHECK-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t nonnull @[[GLOB1]], i8 1, i1 false, i1 true) #[[ATTR4:[0-9]+]]
				; CHECK-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; CHECK-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; CHECK-DISABLED: is_worker_check:
	; CHECK-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; CHECK-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; CHECK-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; CHECK-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; CHECK-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; CHECK-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; CHECK-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; CHECK-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; CHECK-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; CHECK-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; CHECK-DISABLED: is_worker_check:
	; CHECK-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; CHECK-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; CHECK-DISABLED: worker_state_machine.begin:			; CHECK-DISABLED: worker_state_machine.begin:
	; CHECK-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; CHECK-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; CHECK-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; CHECK-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; CHECK-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; CHECK-DISABLED-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; CHECK-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; CHECK-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; CHECK-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; CHECK-DISABLED-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; CHECK-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; CHECK-DISABLED-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; CHECK-DISABLED: worker_state_machine.finished:			; CHECK-DISABLED: worker_state_machine.finished:
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llvm/test/Transforms/OpenMP/spmdization_guarding_two_reaching_kernels.ll

	Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
	; CHECK: @[[__OMP_OUTLINED___WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef			; CHECK: @[[__OMP_OUTLINED___WRAPPER_ID:[a-zA-Z0-9_$"\\.-]+]] = private constant i8 undef
	;.			;.
	define weak void @__omp_offloading_2b_10393b5_spmd_l12() #0 {			define weak void @__omp_offloading_2b_10393b5_spmd_l12() #0 {
	; CHECK-LABEL: define {{[^@]+}}@__omp_offloading_2b_10393b5_spmd_l12			; CHECK-LABEL: define {{[^@]+}}@__omp_offloading_2b_10393b5_spmd_l12
	; CHECK-SAME: () #[[ATTR0:[0-9]+]] {			; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
	; CHECK-NEXT: entry:			; CHECK-NEXT: entry:
	; CHECK-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; CHECK-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; CHECK-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; CHECK-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
				; CHECK-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
				; CHECK-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
				; CHECK: is_worker_check:
	; CHECK-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; CHECK-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; CHECK-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; CHECK-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; CHECK-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; CHECK-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; CHECK-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; CHECK-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; CHECK-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; CHECK-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; CHECK: is_worker_check:
	; CHECK-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; CHECK-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
	; CHECK: worker_state_machine.begin:			; CHECK: worker_state_machine.begin:
	; CHECK-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			; CHECK-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
	; CHECK-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])			; CHECK-NEXT: [[WORKER_IS_ACTIVE:%.]] = call i1 @__kmpc_kernel_parallel(i8* [[WORKER_WORK_FN_ADDR]])
	; CHECK-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8			; CHECK-NEXT: [[WORKER_WORK_FN:%.]] = load i8, i8** [[WORKER_WORK_FN_ADDR]], align 8
	; CHECK-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*			; CHECK-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.]] = bitcast i8 [[WORKER_WORK_FN]] to void (i16, i32)*
	; CHECK-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null			; CHECK-NEXT: [[WORKER_IS_DONE:%.]] = icmp eq i8 [[WORKER_WORK_FN]], null
	; CHECK-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]			; CHECK-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER_STATE_MACHINE_IS_ACTIVE_CHECK:%.*]]
	; CHECK: worker_state_machine.finished:			; CHECK: worker_state_machine.finished:
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