[PowerPC] make splat struct like an array for function arguments

[shchenz]

Summary

Splat struct should be the same with an array. With this, we can get a more accurate alignment in CalculateStackSlotAlignment instead of conservative pointer size alignment.

In some cases, with accurate alignment, we can save parameter save areas like the test case change shows.

[amyk]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

16789

Could we maybe add a comment that describes that we do this for the more accurate alignment?

I am not sure if it is directly obvious in that this is the case.

[shchenz]

address @amyk comments

[shchenz]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

16789

Updated, thanks.

[shchenz]

gentle ping

[shchenz]

gentle ping.

[shchenz]

gentle ping

[shchenz]

gentle ping

[shchenz]

gentle ping

[shchenz]

gentle ping

[shchenz]

gentle ping

[shchenz]

gentle ping

[shchenz]

gentle ping

[shchenz]

Gentle ping

[shchenz]

Gentle ping

llvm/lib/Target/PowerPC/PPCISelLowering.h

public:
     /// or null if the target does not support "fast" instruction selection.
     FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
                              const TargetLibraryInfo *LibInfo) const override;
 
     /// Returns true if an argument of type Ty needs to be passed in a
     /// contiguous block of registers in calling convention CallConv.
     bool functionArgumentNeedsConsecutiveRegisters(
         Type *Ty, CallingConv::ID CallConv, bool isVarArg,
-        const DataLayout &DL) const override {
-      // We support any array type as "consecutive" block in the parameter
-      // save area.  The element type defines the alignment requirement and
-      // whether the argument should go in GPRs, FPRs, or VRs if available.
-      //
-      // Note that clang uses this capability both to implement the ELFv2
-      // homogeneous float/vector aggregate ABI, and to avoid having to use
-      // "byval" when passing aggregates that might fully fit in registers.
-      return Ty->isArrayTy();
-    }
+        const DataLayout &DL) const override;
 
     /// If a physical register, this returns the register that receives the
     /// exception address on entry to an EH pad.
     Register
     getExceptionPointerRegister(const Constant *PersonalityFn) const override;
 
     /// If a physical register, this returns the register that receives the
     /// exception typeid on entry to a landing pad.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

 #include "llvm/ADT/None.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/StringSwitch.h"
+#include "llvm/CodeGen/Analysis.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/ISDOpcodes.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineJumpTableInfo.h"

 
 // Create a fast isel object.
 FastISel *
 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
                                   const TargetLibraryInfo *LibInfo) const {
   return PPC::createFastISel(FuncInfo, LibInfo);
 }
 
+bool PPCTargetLowering::functionArgumentNeedsConsecutiveRegisters(
+    Type *Ty, CallingConv::ID CallConv, bool isVarArg,
+    const DataLayout &DL) const {
+  // We support any array type and splat struct type as "consecutive" block in
+  // the parameter save area. The element type defines the alignment requirement
+  // and whether the argument should go in GPRs, FPRs, or VRs if available.
+  //
+  // Note that clang uses this capability both to implement the ELFv2
+  // homogeneous float/vector aggregate ABI, and to avoid having to use
+  // "byval" when passing aggregates that might fully fit in registers.
+  if (Ty->isArrayTy())
+    return true;
+
+  if (!Ty->isStructTy())
+    return false;
+
+  SmallVector<EVT> ValueVTs;
+  ComputeValueVTs(*this, DL, Ty, ValueVTs);
+  return is_splat(ValueVTs);
+}
+
 // 'Inverted' means the FMA opcode after negating one multiplicand.
 // For example, (fma -a b c) = (fnmsub a b c)
 static unsigned invertFMAOpcode(unsigned Opc) {
   switch (Opc) {
   default:
     llvm_unreachable("Invalid FMA opcode for PowerPC!");
   case ISD::FMA:
     return PPCISD::FNMSUB;

llvm/test/CodeGen/PowerPC/splat-struct.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s \
 ; RUN:   -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
 
 %struct.A = type <{ float, float, float, float, float, float, float, float }>
 
 define signext i32 @foo() nounwind {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    std r0, 16(r1)
-; CHECK-NEXT:    stdu r1, -144(r1)
-; CHECK-NEXT:    lfs f8, 140(r1)
-; CHECK-NEXT:    lfs f7, 136(r1)
-; CHECK-NEXT:    li r3, 10
-; CHECK-NEXT:    lfs f6, 132(r1)
-; CHECK-NEXT:    lfs f5, 128(r1)
-; CHECK-NEXT:    std r3, 96(r1)
-; CHECK-NEXT:    lfs f4, 124(r1)
-; CHECK-NEXT:    lfs f3, 120(r1)
-; CHECK-NEXT:    lfs f2, 116(r1)
-; CHECK-NEXT:    lfs f1, 112(r1)
+; CHECK-NEXT:    stdu r1, -64(r1)
+; CHECK-NEXT:    lfs f8, 60(r1)
+; CHECK-NEXT:    lfs f7, 56(r1)
+; CHECK-NEXT:    li r7, 10
+; CHECK-NEXT:    lfs f6, 52(r1)
+; CHECK-NEXT:    lfs f5, 48(r1)
+; CHECK-NEXT:    lfs f4, 44(r1)
+; CHECK-NEXT:    lfs f3, 40(r1)
+; CHECK-NEXT:    lfs f2, 36(r1)
+; CHECK-NEXT:    lfs f1, 32(r1)
 ; CHECK-NEXT:    bl bar
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    addi r1, r1, 144
+; CHECK-NEXT:    addi r1, r1, 64
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    blr
 entry:
   %a = alloca %struct.A, align 4
   %0 = load %struct.A, %struct.A* %a, align 4
   %call = call signext i32 @bar(%struct.A %0, i32 signext 10)
   ret i32 %call
 }
 
 declare signext i32 @bar(%struct.A, i32 signext)