[IROutliner] Adding support to properly handle musttail, swifttailcc and tailcc

[AndrewLitteken]

Summary

musttail functions and those with swifttailcc and tailcc calling conventions have to be handled specially when being outlined. This adds support of musttail function in the cases of these two calling conventions in particular.

[paquette]

Do you think you could add a statistic which counts the number of tail calls emitted? And maybe some debug output that says that something will be handled as a tail call?

[paquette]

I'm not sure how often musttail/tailcc appears in the LLVM test suite, but this didn't introduce any asserts there, and all of the tests pass.

@aschwaighofer Can you think of any (open source) Swift programs we can test this on? :)

[tschuett]

In D120867#3360859, @paquette wrote:

I'm not sure how often musttail/tailcc appears in the LLVM test suite, but this didn't introduce any asserts there, and all of the tests pass.

@aschwaighofer Can you think of any (open source) Swift programs we can test this on? :)

Is there a clang attribute?

[paquette]

Yeah, it looks like there's a clang attribute, but it isn't used anywhere in the LLVM test suite.

https://clang.llvm.org/docs/AttributeReference.html#musttail

llvm/lib/Transforms/IPO/IROutliner.cpp

2438

2729

Nit: You could just return this rather than explicitly returning true/false

2738

• Can you add a comment explaining why we need to check the caller's CC as well?
• Would it be faster to check this first, and then do the any_of?
• What if every candidate except for the first is in a function with swifttailcc or tailcc? What happens then? Can you add a testcase for that?

2744

Could pull CandidateVec[0] out into a variable?

2749

Nit

2809

I think this needs a testcase?

llvm/lib/Analysis/IRSimilarityIdentifier.cpp

 cl::opt<bool>
     MatchCallsByName("ir-sim-calls-by-name", cl::init(false), cl::ReallyHidden,
                      cl::desc("only allow matching call instructions if the "
                               "name and type signature match."));
 
 cl::opt<bool>
     DisableIntrinsics("no-ir-sim-intrinsics", cl::init(false), cl::ReallyHidden,
                       cl::desc("Don't match or outline intrinsics"));
+
+cl::opt<bool> DisableMustTailCalls(
+    "no-ir-musttail", cl::init(false), cl::ReallyHidden,
+    cl::desc("Don't match or outline any musttail functions"));
+
 } // namespace llvm
 
 IRInstructionData::IRInstructionData(Instruction &I, bool Legality,
                                      IRInstructionDataList &IDList)
     : Inst(&I), Legal(Legality), IDL(&IDList) {
   initializeInstruction();
 }
 
IRSimilarityIdentifierWrapperPass::IRSimilarityIdentifierWrapperPass()
     : ModulePass(ID) {
   initializeIRSimilarityIdentifierWrapperPassPass(
       *PassRegistry::getPassRegistry());
 }
 
 bool IRSimilarityIdentifierWrapperPass::doInitialization(Module &M) {
   IRSI.reset(new IRSimilarityIdentifier(!DisableBranches, !DisableIndirectCalls,
                                         MatchCallsByName, !DisableIntrinsics,
-                                        false));
+                                        !DisableMustTailCalls));
   return false;
 }
 
 bool IRSimilarityIdentifierWrapperPass::doFinalization(Module &M) {
   IRSI.reset();
   return false;
 }
 
 bool IRSimilarityIdentifierWrapperPass::runOnModule(Module &M) {
   IRSI->findSimilarity(M);
   return false;
 }
 
 AnalysisKey IRSimilarityAnalysis::Key;
 IRSimilarityIdentifier IRSimilarityAnalysis::run(Module &M,
                                                  ModuleAnalysisManager &) {
   auto IRSI = IRSimilarityIdentifier(!DisableBranches, !DisableIndirectCalls,
                                      MatchCallsByName, !DisableIntrinsics,
-                                     false);
+                                     !DisableMustTailCalls);
   IRSI.findSimilarity(M);
   return IRSI;
 }
 
 PreservedAnalyses
 IRSimilarityAnalysisPrinterPass::run(Module &M, ModuleAnalysisManager &AM) {
   IRSimilarityIdentifier &IRSI = AM.getResult<IRSimilarityAnalysis>(M);
   Optional<SimilarityGroupList> &SimilarityCandidatesOpt = IRSI.getSimilarity();

llvm/lib/Transforms/IPO/IROutliner.cpp

 #include "llvm/Transforms/IPO.h"
 #include <map>
 #include <set>
 #include <vector>
 
 #define DEBUG_TYPE "iroutliner"
 
 using namespace llvm;
+using namespace CallingConv;
 using namespace IRSimilarity;
 
 // A command flag to be used for debugging to exclude branches from similarity
 // matching and outlining.
 namespace llvm {
 extern cl::opt<bool> DisableBranches;
 
 // A command flag to be used for debugging to indirect calls from similarity
 // matching and outlining.
 extern cl::opt<bool> DisableIndirectCalls;
 
 // A command flag to be used for debugging to exclude intrinsics from similarity
 // matching and outlining.
 extern cl::opt<bool> DisableIntrinsics;
 
+// A command flag to be used for debugging to exclude intrinsics from similarity
+// matching and outlining.
+extern cl::opt<bool> DisableMustTailCalls;
+
 } // namespace llvm
 
 // Set to true if the user wants the ir outliner to run on linkonceodr linkage
 // functions. This is false by default because the linker can dedupe linkonceodr
 // functions. Since the outliner is confined to a single module (modulo LTO),
 // this is off by default. It should, however, be the default behavior in
 // LTO.
 static cl::opt<bool> EnableLinkOnceODRIROutlining(
struct OutlinableGroup {
   /// The number of added instructions needed for the outlining of the \ref
   /// Regions.
   InstructionCost Cost = 0;
 
   /// The argument that needs to be marked with the swifterr attribute.  If not
   /// needed, there is no value.
   Optional<unsigned> SwiftErrorArgument;
 
+  /// The boolean to track whether the group is outlining a SwiftTail calling
+  /// convention function.
+  Optional<CallingConv::ID> HasTailCC;
+
+  /// The boolean to track whether the group is outlining a musttail marked
+  /// function.
+  bool ContainsMustTailCall = false;
+
   /// For the \ref Regions, we look at every Value.  If it is a constant,
   /// we check whether it is the same in Region.
   ///
   /// \param [in,out] NotSame contains the global value numbers where the
   /// constant is not always the same, and must be passed in as an argument.
   void findSameConstants(DenseSet<unsigned> &NotSame);
 
   /// For the regions, look at each set of GVN stores needed and account for
Group.OutlinedFunction = Function::Create(
       Group.OutlinedFunctionType, GlobalValue::InternalLinkage,
       "outlined_ir_func_" + std::to_string(FunctionNameSuffix), M);
 
   // Transfer the swifterr attribute to the correct function parameter.
   if (Group.SwiftErrorArgument.hasValue())
     Group.OutlinedFunction->addParamAttr(Group.SwiftErrorArgument.getValue(),
                                          Attribute::SwiftError);
 
+  // Transfer the SwiftTail calling convention if relevant for the outlined
+  // code.
+  if (Group.HasTailCC.hasValue())
+    Group.OutlinedFunction->setCallingConv(*Group.HasTailCC);
+
   Group.OutlinedFunction->addFnAttr(Attribute::OptimizeForSize);
   Group.OutlinedFunction->addFnAttr(Attribute::MinSize);
 
   // If there's a DISubprogram associated with this outlined function, then
   // emit debug info for the outlined function.
   if (DISubprogram *SP = getSubprogramOrNull(Group)) {
     Function *F = Group.OutlinedFunction;
     // We have a DISubprogram. Get its DICompileUnit.
void createSwitchStatement(
   // corresponding ending block.  We do not check that the OutputGVNCombinations
   // is equal to 1 here since that could just been the case where there are 0
   // outputs. Instead, we check whether there is more than one set of output
   // blocks since this is the only case where we would have to move the
   // stores, and erase the extraneous blocks.
   if (OutputStoreBBs.size() == 1) {
     LLVM_DEBUG(dbgs() << "Move store instructions to the end block in "
                       << *OG.OutlinedFunction << "\n");
-    DenseMap<Value *, BasicBlock *> OutputBlocks = OutputStoreBBs[0];
+    DenseMap<Value *, BasicBlock *> &OutputBlocks = OutputStoreBBs[0];
     for (std::pair<Value *, BasicBlock *> &VBPair : OutputBlocks) {
       DenseMap<Value *, BasicBlock *>::iterator EndBBIt =
           EndBBs.find(VBPair.first);
       assert(EndBBIt != EndBBs.end() && "Could not find end block");
       BasicBlock *EndBB = EndBBIt->second;
       BasicBlock *OutputBB = VBPair.second;
       Instruction *Term = OutputBB->getTerminator();
       Term->eraseFromParent();
       Term = EndBB->getTerminator();
       moveBBContents(*OutputBB, *EndBB);
       Term->moveBefore(*EndBB, EndBB->end());
       OutputBB->eraseFromParent();
     }
+    return;
+  }
+
+  // If there are no End Blocks, then we have no return instructions to compress
+  // and no other exits.  We can simply return without having done anything.
+  if (EndBBs.size() == 0)
+    return;
+
+  // At this point, we have no outputs to handle, and only one exit but we still
+  // branch unnecessarily to a different block.  So we eliminate this branch to
+  // the final block and move it into it's predecessors.
+
+  // This is not only an optimization, but necessary in the case where we are
+  // outlining a tail called function, as it still must remain the final
+  // operation, excluding the return in the function.
+  DenseMap<Value *, BasicBlock *>::iterator EndBBIt = EndBBs.begin();
+  BasicBlock *EndBB = EndBBIt->second;
+  Instruction *RI = EndBB->getTerminator();
+  Instruction *RIDup;
+  Instruction *Term;
+  SmallVector<Instruction *, 2> TermsToErase;
+  bool AllWereCompressed = true;
+  for (BasicBlock *Pred : predecessors(EndBB)) {
+    if (!Pred->getUniqueSuccessor()) {
+      AllWereCompressed = false;
+      continue;
+    }
+    Term = Pred->getTerminator();
+    TermsToErase.push_back(Term);
+    RIDup = RI->clone();
+    RIDup->insertAfter(&Pred->back());
   }
+  for (Instruction *Term : TermsToErase)
+    Term->eraseFromParent();
+  if (AllWereCompressed)
+    EndBB->eraseFromParent();
 }
 
 /// Fill the new function that will serve as the replacement function for all of
 /// the extracted regions of a certain structure from the first region in the
 /// list of regions.  Replace this first region's extracted function with the
 /// new overall function.
 ///
 /// \param [in] M - The module we are outlining from.
for (unsigned Idx = 1; Idx < CurrentGroup.Regions.size(); Idx++) {
     alignOutputBlockWithAggFunc(CurrentGroup, *CurrentOS, NewBBs,
                                 CurrentGroup.EndBBs, OutputMappings,
                                 OutputStoreBBs);
 
     CurrentOS->Call = replaceCalledFunction(M, *CurrentOS);
     FuncsToRemove.push_back(CurrentOS->ExtractedFunction);
   }
 
+  for (OutlinableRegion *Region : CurrentGroup.Regions) {
+    // Make sure that the calling convention for SwiftTail is set.
+    if (CurrentGroup.HasTailCC.hasValue())
+      Region->Call->setCallingConv(*CurrentGroup.HasTailCC);
+
+    // Make sure that the calling convention for SwiftTail is set.
+    if (CurrentGroup.ContainsMustTailCall)
+      Region->Call->setTailCallKind(CallInst::TailCallKind::TCK_MustTail);
+  }
+
   // Create a switch statement to handle the different output schemes.
   createSwitchStatement(M, CurrentGroup, CurrentGroup.EndBBs, OutputStoreBBs);
 
   OutlinedFunctionNum++;
 }
 
 /// Checks that the next instruction in the InstructionDataList matches the
 /// next instruction in the module.  If they do not, there could be the
for (unsigned OutputCanon : Region->GVNStores) {
                         << *V->getType() << "\n");
       OverallCost += LoadCost;
     }
   }
 
   return OverallCost;
 }
 
-/// Find the extra instructions needed to handle any output values for the
-/// region.
+/// Determine how many different exit paths exists for a region in the \ref
+/// OutlinableGroup \param CurrentGroup.  This is done by chekcing how many
+/// branches target BasicBlocks outside of the region.
 ///
-/// \param [in] M - The Module to outline from.
-/// \param [in] CurrentGroup - The collection of OutlinableRegions to analyze.
-/// \param [in] TTI - The TargetTransformInfo used to collect information for
-/// new instruction costs.
-/// \returns the additional cost to handle the outputs.
-static InstructionCost findCostForOutputBlocks(Module &M,
-                                               OutlinableGroup &CurrentGroup,
-                                               TargetTransformInfo &TTI) {
-  InstructionCost OutputCost = 0;
-  unsigned NumOutputBranches = 0;
-
-  OutlinableRegion &FirstRegion = *CurrentGroup.Regions[0];
-  IRSimilarityCandidate &Candidate = *CurrentGroup.Regions[0]->Candidate;
+///
+/// \param CurrentGroup - The region whose blocks to analyze.
+/// \returns the number of exit paths from the region.
+static unsigned findNumberOutputBranches(OutlinableRegion &Region) {
+  IRSimilarityCandidate &Candidate = *Region.Candidate;
   DenseSet<BasicBlock *> CandidateBlocks;
   Candidate.getBasicBlocks(CandidateBlocks);
+  unsigned NumOutputBranches = 0;
 
   // Count the number of different output branches that point to blocks outside
   // of the region.
   DenseSet<BasicBlock *> FoundBlocks;
   for (IRInstructionData &ID : Candidate) {
     if (!isa<BranchInst>(ID.Inst))
       continue;
 
     for (Value *V : ID.OperVals) {
       BasicBlock *BB = static_cast<BasicBlock *>(V);
       DenseSet<BasicBlock *>::iterator CBIt = CandidateBlocks.find(BB);
       if (CBIt != CandidateBlocks.end() || FoundBlocks.contains(BB))
         continue;
       FoundBlocks.insert(BB);
       NumOutputBranches++;
     }
   }
 
-  CurrentGroup.BranchesToOutside = NumOutputBranches;
+  return NumOutputBranches;
+}
+
+/// Find the extra instructions needed to handle any output values for the
+/// region.
+///
+/// \param [in] M - The Module to outline from.
+/// \param [in] CurrentGroup - The collection of OutlinableRegions to analyze.
+/// \param [in] TTI - The TargetTransformInfo used to collect information for
+/// new instruction costs.
+/// \returns the additional cost to handle the outputs.
+static InstructionCost findCostForOutputBlocks(Module &M,
+                                               OutlinableGroup &CurrentGroup,
+                                               TargetTransformInfo &TTI) {
+  InstructionCost OutputCost = 0;
+  unsigned NumOutputBranches = CurrentGroup.BranchesToOutside;
+
+  OutlinableRegion &FirstRegion = *CurrentGroup.Regions[0];
 
   for (const ArrayRef<unsigned> &OutputUse :
        CurrentGroup.OutputGVNCombinations) {
     for (unsigned OutputCanon : OutputUse) {
       Value *V = findOutputValueInRegion(FirstRegion, OutputCanon);
       InstructionCost StoreCost =
           TTI.getMemoryOpCost(Instruction::Load, V->getType(), Align(1), 0,
                               TargetTransformInfo::TCK_CodeSize);
bool IROutliner::extractSection(OutlinableRegion &Region) {
   return true;
 }
 
 unsigned IROutliner::doOutline(Module &M) {
   // Find the possible similarity sections.
   InstructionClassifier.EnableBranches = !DisableBranches;
   InstructionClassifier.EnableIndirectCalls = !DisableIndirectCalls;
   InstructionClassifier.EnableIntrinsics = !DisableIntrinsics;
+  InstructionClassifier.EnableMustTailCalls = !DisableMustTailCalls;
 
   IRSimilarityIdentifier &Identifier = getIRSI(M);
   SimilarityGroupList &SimilarityCandidates = *Identifier.getSimilarity();
 
   // Sort them by size of extracted sections
   unsigned OutlinedFunctionNum = 0;
   // If we only have one SimilarityGroup in SimilarityCandidates, we do not have
   // to sort them by the potential number of instructions to be outlined
unsigned IROutliner::doOutline(Module &M) {
   DenseSet<unsigned> NotSame;
   std::vector<OutlinableGroup *> NegativeCostGroups;
   std::vector<OutlinableRegion *> OutlinedRegions;
   // Iterate over the possible sets of similarity.
   unsigned PotentialGroupIdx = 0;
   for (SimilarityGroup &CandidateVec : SimilarityCandidates) {
     OutlinableGroup &CurrentGroup = PotentialGroups[PotentialGroupIdx++];
 
+    // We check if any call instruction in the set contains a swifttailcc
+    // or tailcc calling convention function.  If it does, we indicate it in the
+    // OutlinableGroup.
+    bool HasATailCC =
+        any_of(CandidateVec[0], [](IRInstructionData &ID) {
+          CallInst *CI = dyn_cast<CallInst>(ID.Inst);
+          if (!CI)
+            return false;
+          
+          if(CI->getCallingConv() == CallingConv::SwiftTail ||
+             CI->getCallingConv() == CallingConv::Tail)
+            return true;
+          
+          return false;
+        });
+
+    if (HasATailCC)
+      CurrentGroup.HasTailCC =
+          CandidateVec[0].frontInstruction()->getFunction()->getCallingConv();
+
+    // We check if any call instruction in the set contains a musttail
+    // function attribute. If it does, we inidicate it in the group, as any
+    // outlined function must also be marked with this attribute.
+    CurrentGroup.ContainsMustTailCall =
+        any_of(CandidateVec[0], [](IRInstructionData &ID) {
+          CallInst *CI = dyn_cast<CallInst>(ID.Inst);
+          if (!CI)
+            return false;
+
+          return CI->isMustTailCall();
+        });
+
     // Remove entries that were previously outlined
     pruneIncompatibleRegions(CandidateVec, CurrentGroup);
 
     // We pruned the number of regions to 0 to 1, meaning that it's not worth
     // trying to outlined since there is no compatible similar instance of this
     // code.
     if (CurrentGroup.Regions.size() < 2)
       continue;
for (SimilarityGroup &CandidateVec : SimilarityCandidates) {
 
     CurrentGroup.Regions = std::move(OutlinedRegions);
 
     if (CurrentGroup.Regions.empty())
       continue;
 
     CurrentGroup.collectGVNStoreSets(M);
 
+    // If we are outlining a function that contains a tail call, we must
+    // ensure that there is only one exit from the outlined region.  If there is
+    // not, this means that there will be instructions that need to be executed
+    // after the outlined function resolves to handle the different exit paths.
+
+    // As a result, we disregard groups containing a tail call, but contain
+    // multiple exits.
+    CurrentGroup.BranchesToOutside =
+        findNumberOutputBranches(*CurrentGroup.Regions[0]);
+    if (CurrentGroup.BranchesToOutside > 1 &&
+        (CurrentGroup.HasTailCC.hasValue() ||
+         CurrentGroup.ContainsMustTailCall))
+      continue;
+
     if (CostModel)
       findCostBenefit(M, CurrentGroup);
 
     // If we are adhering to the cost model, skip those groups where the cost
     // outweighs the benefits.
     if (CurrentGroup.Cost >= CurrentGroup.Benefit && CostModel) {
       OptimizationRemarkEmitter &ORE =
           getORE(*CurrentGroup.Regions[0]->Candidate->getFunction());

llvm/test/Transforms/IROutliner/included-phi-nodes-begin.ll

 ; CHECK-NEXT:    ret void
 ; CHECK:       test1:
 ; CHECK-NEXT:    call void @outlined_ir_func_0(i32 [[Y]], i32* [[TMP0]], i32 [[C]])
 ; CHECK-NEXT:    br label [[FIRST:%.*]]
 ; CHECK:       first:
 ; CHECK-NEXT:    ret void
 ;
 ;
-; CHECK: define internal void @outlined_ir_func_0(
+; CHECK-LABEL: define internal void @outlined_ir_func_0(
 ; CHECK-NEXT:  newFuncRoot:
 ; CHECK-NEXT:    br label [[TEST1_TO_OUTLINE:%.*]]
 ; CHECK:       test1_to_outline:
 ; CHECK-NEXT:    [[TMP3:%.*]] = phi i32 [ [[E:%.*]], [[TEST1_TO_OUTLINE]] ], [ [[TMP0:%.*]], [[NEWFUNCROOT:%.*]] ]
 ; CHECK-NEXT:    [[TMP4:%.*]] = phi i32 [ [[E]], [[TEST1_TO_OUTLINE]] ], [ [[TMP0]], [[NEWFUNCROOT]] ]
 ; CHECK-NEXT:    [[E]] = load i32, i32* [[TMP1:%.*]], align 4
 ; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[TMP2:%.*]], [[TMP2]]
 ; CHECK-NEXT:    br i1 true, label [[TEST:%.*]], label [[TEST1_TO_OUTLINE]]
 ; CHECK:       test:
 ; CHECK-NEXT:    [[D:%.*]] = load i32, i32* [[TMP1]], align 4
-; CHECK-NEXT:    br label [[FIRST_EXITSTUB:%.*]]
-; CHECK:       first.exitStub:
 ; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/IROutliner/included-phi-nodes-end.ll

 ; CHECK-NEXT:    [[TARGETBLOCK:%.*]] = call i1 @outlined_ir_func_0(i32* [[TMP0]], i32 [[C]])
 ; CHECK-NEXT:    br i1 [[TARGETBLOCK]], label [[NEXT:%.*]], label [[ENTRY_AFTER_OUTLINE:%.*]]
 ; CHECK:       entry_after_outline:
 ; CHECK-NEXT:    ret void
 ; CHECK:       next:
 ; CHECK-NEXT:    ret void
 ;
 ;
-; CHECK: define internal i1 @outlined_ir_func_0(
+; CHECK-LABEL: define internal i1 @outlined_ir_func_0(
 ; CHECK-NEXT:  newFuncRoot:
 ; CHECK-NEXT:    br label [[ENTRY_TO_OUTLINE:%.*]]
 ; CHECK:       entry_to_outline:
 ; CHECK-NEXT:    br i1 true, label [[TEST1:%.*]], label [[FIRST:%.*]]
 ; CHECK:       test1:
 ; CHECK-NEXT:    [[E:%.*]] = load i32, i32* [[TMP0:%.*]], align 4
 ; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[TMP1:%.*]], [[TMP1]]
 ; CHECK-NEXT:    br i1 true, label [[FIRST]], label [[TEST:%.*]]

llvm/test/Transforms/IROutliner/legal-debug.ll

 ; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4, !dbg [[DBG31:![0-9]+]]
 ; CHECK-NEXT:    call void @llvm.dbg.value(metadata i32* [[B]], metadata [[META25:![0-9]+]], metadata !DIExpression()), !dbg [[DBG31]]
 ; CHECK-NEXT:    [[C:%.*]] = alloca i32, align 4, !dbg [[DBG32:![0-9]+]]
 ; CHECK-NEXT:    call void @llvm.dbg.value(metadata i32* [[C]], metadata [[META26:![0-9]+]], metadata !DIExpression()), !dbg [[DBG32]]
 ; CHECK-NEXT:    call void @outlined_ir_func_0(i32* [[A]], i32* [[B]], i32* [[C]]), !dbg [[DBG33:![0-9]+]]
 ; CHECK-NEXT:    ret void, !dbg [[DBG34:![0-9]+]]
 ;
 ;
-; CHECK: @outlined_ir_func_0(i32* [[TMP0:%.*]], i32* [[TMP1:%.*]], i32*  [[TMP2:%.*]])
+; CHECK-LABEL: define internal void @outlined_ir_func_0(
+; CHECK-NEXT:  newFuncRoot:
+; CHECK-NEXT:    br label [[ENTRY_TO_OUTLINE:%.*]]
 ; CHECK:       entry_to_outline:
-; CHECK-NEXT:    store i32 2, i32* [[TMP0]], align 4
-; CHECK-NEXT:    store i32 3, i32* [[TMP1]], align 4
-; CHECK-NEXT:    store i32 4, i32* [[TMP2]], align 4
+; CHECK-NEXT:    store i32 2, i32* [[TMP0:%.*]], align 4
+; CHECK-NEXT:    store i32 3, i32* [[TMP1:%.*]], align 4
+; CHECK-NEXT:    store i32 4, i32* [[TMP2:%.*]], align 4
 ; CHECK-NEXT:    [[AL:%.*]] = load i32, i32* [[TMP0]], align 4
 ; CHECK-NEXT:    [[BL:%.*]] = load i32, i32* [[TMP1]], align 4
 ; CHECK-NEXT:    [[CL:%.*]] = load i32, i32* [[TMP2]], align 4
-; CHECK-NEXT:    br label [[ENTRY_AFTER_OUTLINE_EXITSTUB:%.*]]
+; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/IROutliner/legal-indirect-calls.ll

 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    [[C:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    call void @outlined_ir_func_0(i32* [[A]], i32* [[B]], i32* [[C]], void ()* [[FUNC:%.*]])
 ; CHECK-NEXT:    ret void
 ;
 ;
-; CHECK-LABEL: define internal void  @outlined_ir_func_0(
+; CHECK-LABEL: define internal void @outlined_ir_func_0(
 ; CHECK-NEXT:  newFuncRoot:
 ; CHECK-NEXT:    br label [[ENTRY_TO_OUTLINE:%.*]]
 ; CHECK:       entry_to_outline:
 ; CHECK-NEXT:    store i32 2, i32* [[TMP0:%.*]], align 4
 ; CHECK-NEXT:    store i32 3, i32* [[TMP1:%.*]], align 4
 ; CHECK-NEXT:    store i32 4, i32* [[TMP2:%.*]], align 4
 ; CHECK-NEXT:    call void [[TMP3:%.*]]()
 ; CHECK-NEXT:    [[AL:%.*]] = load i32, i32* [[TMP0]], align 4
 ; CHECK-NEXT:    [[BL:%.*]] = load i32, i32* [[TMP1]], align 4
 ; CHECK-NEXT:    [[CL:%.*]] = load i32, i32* [[TMP2]], align 4
-; CHECK-NEXT:    br label [[ENTRY_AFTER_OUTLINE_EXITSTUB:%.*]]
-; CHECK:       entry_after_outline.exitStub:
 ; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/IROutliner/mismatched-phi-outputs-ordering.ll

 ; CHECK-NEXT:    store i32 [[E]], i32* [[TMP1]], align 4
 ; CHECK-NEXT:    br label [[FINAL_BLOCK_1]]
 ; CHECK:       final_block_0:
 ; CHECK-NEXT:    ret i1 false
 ; CHECK:       final_block_1:
 ; CHECK-NEXT:    ret i1 true
 ;
 ;
-; CHECK-LABEL: @outlined_ir_func_1(
+; CHECK-LABEL: define internal void @outlined_ir_func_1(
 ; CHECK-NEXT:  newFuncRoot:
 ; CHECK-NEXT:    br label [[NEXT_TO_OUTLINE:%.*]]
 ; CHECK:       next_to_outline:
 ; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[TMP0:%.*]], 1
 ; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[TMP1:%.*]], 1
-; CHECK-NEXT:    br label [[NEXT_AFTER_OUTLINE_EXITSTUB:%.*]]
-; CHECK:       next_after_outline.exitStub:
 ; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/IROutliner/no-outlining-swifttailcc.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --include-generated-funcs
+; RUN: opt -S -verify -iroutliner -ir-outlining-no-cost -no-ir-musttail < %s | FileCheck %s
+
+; Check that we do not outline musttail calls when swifttailcc is present
+; if specified on the command line.
+
+declare swifttailcc void @musttail()
+
+define swifttailcc void @f1() {
+  %a = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  musttail call swifttailcc void @musttail()
+  ret void
+}
+
+define swifttailcc void @f2() {
+  %a = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  musttail call swifttailcc void @musttail()
+  ret void
+}
+; CHECK-LABEL: @f1(
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    store i32 2, i32* [[A]], align 4
+; CHECK-NEXT:    musttail call swifttailcc void @musttail()
+; CHECK-NEXT:    ret void
+;
+;
+; CHECK-LABEL: @f2(
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    store i32 2, i32* [[A]], align 4
+; CHECK-NEXT:    musttail call swifttailcc void @musttail()
+; CHECK-NEXT:    ret void
+;

llvm/test/Transforms/IROutliner/outline-memset.ll

 ;
 ; CHECK-LABEL: @function2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[POOL:%.*]] = alloca [59 x i64], align 4
 ; CHECK-NEXT:    call void @outlined_ir_func_0([59 x i64]* [[POOL]], i64 [[N:%.*]], i64 [[X:%.*]], i64 [[Z:%.*]])
 ; CHECK-NEXT:    ret i64 0
 ;
 ;
-; CHECK: define internal void @outlined_ir_func_0(
+; CHECK-LABEL: define internal void @outlined_ir_func_0(
 ; CHECK-NEXT:  newFuncRoot:
 ; CHECK-NEXT:    br label [[ENTRY_TO_OUTLINE:%.*]]
 ; CHECK:       entry_to_outline:
 ; CHECK-NEXT:    [[TMP:%.*]] = bitcast [59 x i64]* [[TMP0:%.*]] to i8*
 ; CHECK-NEXT:    call void @llvm.memset.p0i8.i64(i8* align 4 [[TMP]], i8 0, i64 236, i1 false)
 ; CHECK-NEXT:    [[CMP3:%.*]] = icmp eq i64 [[TMP1:%.*]], 0
 ; CHECK-NEXT:    [[A:%.*]] = add i64 [[TMP2:%.*]], [[TMP3:%.*]]
 ; CHECK-NEXT:    [[C:%.*]] = add i64 [[TMP2]], [[TMP3]]
-; CHECK-NEXT:    br label [[ENTRY_AFTER_OUTLINE_EXITSTUB:%.*]]
-; CHECK:       entry_after_outline.exitStub:
 ; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/IROutliner/outline-vaarg-intrinsic.ll

 ; CHECK-NEXT:    call void @llvm.va_start(i8* [[AP1]])
 ; CHECK-NEXT:    [[TMP0:%.*]] = va_arg i8** [[AP]], i32
 ; CHECK-NEXT:    call void @outlined_ir_func_0(i8* [[V:%.*]], i8* [[AP1]], i32 [[TMP0]], i32* [[C]])
 ; CHECK-NEXT:    [[AP2:%.*]] = bitcast i8** [[AP]] to i8*
 ; CHECK-NEXT:    [[TMP:%.*]] = load i32, i32* [[C]], align 4
 ; CHECK-NEXT:    ret i32 [[TMP]]
 ;
 ;
-; CHECK: define internal void @outlined_ir_func_0(
+; CHECK-LABEL: define internal void @outlined_ir_func_0(
 ; CHECK-NEXT:  newFuncRoot:
 ; CHECK-NEXT:    br label [[ENTRY_TO_OUTLINE:%.*]]
 ; CHECK:       entry_to_outline:
 ; CHECK-NEXT:    call void @llvm.va_copy(i8* [[TMP0:%.*]], i8* [[TMP1:%.*]])
 ; CHECK-NEXT:    call void @llvm.va_end(i8* [[TMP1]])
 ; CHECK-NEXT:    store i32 [[TMP2:%.*]], i32* [[TMP3:%.*]], align 4
-; CHECK-NEXT:    br label [[ENTRY_AFTER_OUTLINE_EXITSTUB:%.*]]
-; CHECK:       entry_after_outline.exitStub:
 ; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/IROutliner/outlining-across-branch.ll

 ; CHECK-NEXT:    [[OUTPUT:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    [[RESULT:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    [[OUTPUT2:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    [[RESULT2:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    call void @outlined_ir_func_0(i32* [[A]], i32* [[B]], i32* [[OUTPUT]], i32* [[RESULT]])
 ; CHECK-NEXT:    ret void
 ;
 ;
-; CHECK: define internal void @outlined_ir_func_0(
-; CHECK:  newFuncRoot:
+; CHECK-LABEL: define internal void @outlined_ir_func_0(
+; CHECK-NEXT:  newFuncRoot:
 ; CHECK-NEXT:    br label [[ENTRY_TO_OUTLINE:%.*]]
 ; CHECK:       entry_to_outline:
 ; CHECK-NEXT:    store i32 2, i32* [[TMP0:%.*]], align 4
 ; CHECK-NEXT:    store i32 3, i32* [[TMP1:%.*]], align 4
 ; CHECK-NEXT:    br label [[NEXT:%.*]]
 ; CHECK:       next:
 ; CHECK-NEXT:    store i32 2, i32* [[TMP2:%.*]], align 4
 ; CHECK-NEXT:    store i32 3, i32* [[TMP3:%.*]], align 4
-; CHECK-NEXT:    br label [[ENTRY_AFTER_OUTLINE_EXITSTUB:%.*]]
-; CHECK:       entry_after_outline.exitStub:
 ; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/IROutliner/outlining-basic-branches.ll

 ; CHECK-NEXT:    br label [[NEXT3:%.*]]
 ; CHECK:       next5:
 ; CHECK-NEXT:    br label [[NEXT6:%.*]]
 ; CHECK:       next6:
 ; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    ret void
 ;
 ;
-; CHECK: define internal void @outlined_ir_func_0(
-; CHECK:  newFuncRoot:
+; CHECK-LABEL: define internal void @outlined_ir_func_0(
+; CHECK-NEXT:  newFuncRoot:
 ; CHECK-NEXT:    br label [[NEXT_TO_OUTLINE:%.*]]
 ; CHECK:       next_to_outline:
 ; CHECK-NEXT:    br label [[NEXT2:%.*]]
 ; CHECK:       next2:
-; CHECK-NEXT:    br label [[NEXT_EXITSTUB:%.*]]
-; CHECK:       next.exitStub:
 ; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/IROutliner/outlining-bitcasts.ll

 ; CHECK-NEXT:    [[CM:%.*]] = add i32 [[B]], [[C]]
 ; CHECK-NEXT:    [[LT_CAST1:%.*]] = bitcast i32* [[D]] to i8*
 ; CHECK-NEXT:    call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST1]])
 ; CHECK-NEXT:    [[LT_CAST:%.*]] = bitcast i32* [[D]] to i8*
 ; CHECK-NEXT:    call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
 ; CHECK-NEXT:    ret void
 ;
 ;
-; CHECK-LABEL: @outlined_ir_func_0(
+; CHECK-LABEL: define internal void @outlined_ir_func_0(
 ; CHECK-NEXT:  newFuncRoot:
 ; CHECK-NEXT:    br label [[ENTRY_TO_OUTLINE:%.*]]
 ; CHECK:       entry_to_outline:
 ; CHECK-NEXT:    store i32 2, i32* [[TMP0:%.*]], align 4
 ; CHECK-NEXT:    store i32 3, i32* [[TMP1:%.*]], align 4
 ; CHECK-NEXT:    store i32 4, i32* [[TMP2:%.*]], align 4
 ; CHECK-NEXT:    [[X:%.*]] = bitcast i32* [[TMP3:%.*]] to i8*
 ; CHECK-NEXT:    [[AL:%.*]] = load i32, i32* [[TMP0]], align 4
 ; CHECK-NEXT:    [[BL:%.*]] = load i32, i32* [[TMP1]], align 4
 ; CHECK-NEXT:    [[CL:%.*]] = load i32, i32* [[TMP2]], align 4
-; CHECK-NEXT:    br label [[ENTRY_AFTER_OUTLINE_EXITSTUB:%.*]]
-; CHECK:       entry_after_outline.exitStub:
 ; CHECK-NEXT:    ret void
+;

llvm/test/Transforms/IROutliner/outlining-call-and-indirect.ll

 ; CHECK:       entry_to_outline:
 ; CHECK-NEXT:    store i32 2, i32* [[TMP0:%.*]], align 4
 ; CHECK-NEXT:    store i32 3, i32* [[TMP1:%.*]], align 4
 ; CHECK-NEXT:    store i32 4, i32* [[TMP2:%.*]], align 4
 ; CHECK-NEXT:    call void [[TMP3:%.*]]()
 ; CHECK-NEXT:    [[AL:%.*]] = load i32, i32* [[TMP0]], align 4
 ; CHECK-NEXT:    [[BL:%.*]] = load i32, i32* [[TMP1]], align 4
 ; CHECK-NEXT:    [[CL:%.*]] = load i32, i32* [[TMP2]], align 4
-; CHECK-NEXT:    br label [[ENTRY_AFTER_OUTLINE_EXITSTUB:%.*]]
-; CHECK:       entry_after_outline.exitStub:
 ; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/IROutliner/outlining-calls.ll

 ; CHECK:       entry_to_outline:
 ; CHECK-NEXT:    store i32 2, i32* [[TMP0:%.*]], align 4
 ; CHECK-NEXT:    store i32 3, i32* [[TMP1:%.*]], align 4
 ; CHECK-NEXT:    store i32 4, i32* [[TMP2:%.*]], align 4
 ; CHECK-NEXT:    call void [[TMP3:%.*]](i32* [[TMP0]], i32* [[TMP1]])
 ; CHECK-NEXT:    [[AL:%.*]] = load i32, i32* [[TMP0]], align 4
 ; CHECK-NEXT:    [[BL:%.*]] = load i32, i32* [[TMP1]], align 4
 ; CHECK-NEXT:    [[CL:%.*]] = load i32, i32* [[TMP2]], align 4
-; CHECK-NEXT:    br label [[ENTRY_AFTER_OUTLINE_EXITSTUB:%.*]]
-; CHECK:       entry_after_outline.exitStub:
 ; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/IROutliner/outlining-commutative-operands-opposite-order.ll

 ; CHECK-NEXT:    ret void
 ;
 ;
 ; CHECK-LABEL: @turtle(
 ; CHECK-NEXT:    call void @outlined_ir_func_0(i32 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]])
 ; CHECK-NEXT:    ret void
 ;
 ;
-; CHECK: @outlined_ir_func_0(i32 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]])
+; CHECK-LABEL: define internal void @outlined_ir_func_0(
+; CHECK-NEXT:  newFuncRoot:
+; CHECK-NEXT:    br label [[ENTRY_TO_OUTLINE:%.*]]
 ; CHECK:       entry_to_outline:
-; CHECK-NEXT:    [[TMP3:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
-; CHECK-NEXT:    [[TMP4:%.*]] = sub nsw i32 [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP3:%.*]] = add nsw i32 [[TMP0:%.*]], [[TMP1:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = sub nsw i32 [[TMP1]], [[TMP2:%.*]]
 ; CHECK-NEXT:    [[TMP5:%.*]] = sub nsw i32 [[TMP0]], [[TMP2]]
-; CHECK-NEXT:    br label [[ENTRY_AFTER_OUTLINE_EXITSTUB:%.*]]
+; CHECK-NEXT:    ret void
 ;
+;.
+; CHECK: attributes #[[ATTR0:[0-9]+]] = { minsize optsize }
+;.

llvm/test/Transforms/IROutliner/outlining-swift-error.ll

-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --include-generated-funcs
 ; RUN: opt -S -verify -iroutliner -ir-outlining-no-cost < %s | FileCheck %s
 
 %swift.error = type opaque
 
 define void @outlining_swifterror1(%swift.error** swifterror %err) {
-; CHECK-LABEL: @outlining_swifterror1(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[X:%.*]] = alloca i64, align 8
-; CHECK-NEXT:    call void @outlined_ir_func_0(i64 5, i64* [[X]], %swift.error** swifterror [[ERR:%.*]])
-; CHECK-NEXT:    ret void
-;
 entry:
   %x = alloca i64
   %0 = mul i64 5, 5
   %1 = add i64 %0, %0
   store i64 %1, i64* %x
   %casted = bitcast i64* %x to %swift.error*
   store %swift.error* %casted, %swift.error** %err
   ret void
 }
 
 define void @outlining_swifterror2(%swift.error** swifterror %err) {
-; CHECK-LABEL: @outlining_swifterror2(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[X:%.*]] = alloca i64, align 8
-; CHECK-NEXT:    call void @outlined_ir_func_0(i64 3, i64* [[X]], %swift.error** swifterror [[ERR:%.*]])
-; CHECK-NEXT:    ret void
-;
 entry:
   %x = alloca i64
   %0 = mul i64 3, 3
   %1 = add i64 %0, %0
   store i64 %1, i64* %x
   %casted = bitcast i64* %x to %swift.error*
   store %swift.error* %casted, %swift.error** %err
   ret void
 }
 
-; CHECK: define internal void @outlined_ir_func_0(i64 [[ARG0:%.*]], i64* [[ARG1:%.*]], %swift.error** swifterror [[ARG2:%.*]])
-; CHECK: entry_to_outline:
-; CHECK-NEXT:  [[TMP0:%.*]] = mul i64 [[ARG0]], [[ARG0]]
-; CHECK-NEXT:  [[TMP1:%.*]] = add i64 [[TMP0]], [[TMP0]]
-; CHECK-NEXT:  store i64 [[TMP1]], i64* [[ARG1]], align 4
-; CHECK-NEXT:  %casted = bitcast i64* [[ARG1]] to %swift.error*
-; CHECK-NEXT:  store %swift.error* %casted, %swift.error** [[ARG2]], align 8
-; CHECK-NEXT:  br label %entry_after_outline.exitStub
+; CHECK-LABEL: @outlining_swifterror1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[X:%.*]] = alloca i64, align 8
+; CHECK-NEXT:    call void @outlined_ir_func_0(i64 5, i64* [[X]], %swift.error** swifterror [[ERR:%.*]])
+; CHECK-NEXT:    ret void
+;
+;
+; CHECK-LABEL: @outlining_swifterror2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[X:%.*]] = alloca i64, align 8
+; CHECK-NEXT:    call void @outlined_ir_func_0(i64 3, i64* [[X]], %swift.error** swifterror [[ERR:%.*]])
+; CHECK-NEXT:    ret void
+;
+;
+; CHECK-LABEL: define internal void @outlined_ir_func_0(
+; CHECK-NEXT:  newFuncRoot:
+; CHECK-NEXT:    br label [[ENTRY_TO_OUTLINE:%.*]]
+; CHECK:       entry_to_outline:
+; CHECK-NEXT:    [[TMP3:%.*]] = mul i64 [[TMP0:%.*]], [[TMP0]]
+; CHECK-NEXT:    [[TMP4:%.*]] = add i64 [[TMP3]], [[TMP3]]
+; CHECK-NEXT:    store i64 [[TMP4]], i64* [[TMP1:%.*]], align 4
+; CHECK-NEXT:    [[CASTED:%.*]] = bitcast i64* [[TMP1]] to %swift.error*
+; CHECK-NEXT:    store %swift.error* [[CASTED]], %swift.error** [[TMP2:%.*]], align 8
+; CHECK-NEXT:    ret void
+;

llvm/test/Transforms/IROutliner/outlining-swifttailcc.ll

 define swifttailcc void @f2() {
   %a = alloca i32, align 4
   store i32 2, i32* %a, align 4
   musttail call swifttailcc void @musttail()
   ret void
 }
 ; CHECK-LABEL: @f1(
 ; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
-; CHECK-NEXT:    store i32 2, i32* [[A]], align 4
-; CHECK-NEXT:    musttail call swifttailcc void @musttail()
+; CHECK-NEXT:    musttail call swifttailcc void @outlined_ir_func_0(i32* [[A]])
 ; CHECK-NEXT:    ret void
 ;
 ;
 ; CHECK-LABEL: @f2(
 ; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
-; CHECK-NEXT:    store i32 2, i32* [[A]], align 4
+; CHECK-NEXT:    musttail call swifttailcc void @outlined_ir_func_0(i32* [[A]])
+; CHECK-NEXT:    ret void
+;
+;
+; CHECK-LABEL: define internal swifttailcc void @outlined_ir_func_0(
+; CHECK-NEXT:  newFuncRoot:
+; CHECK-NEXT:    br label [[_TO_OUTLINE:%.*]]
+; CHECK:       _to_outline:
+; CHECK-NEXT:    store i32 2, i32* [[TMP0:%.*]], align 4
 ; CHECK-NEXT:    musttail call swifttailcc void @musttail()
 ; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/IROutliner/outlining-tailcc.ll

 define tailcc void @f2() {
   %a = alloca i32, align 4
   store i32 2, i32* %a, align 4
   musttail call tailcc void @musttail()
   ret void
 }
 ; CHECK-LABEL: @f1(
 ; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
-; CHECK-NEXT:    store i32 2, i32* [[A]], align 4
-; CHECK-NEXT:    musttail call tailcc void @musttail()
+; CHECK-NEXT:    musttail call tailcc void @outlined_ir_func_0(i32* [[A]])
 ; CHECK-NEXT:    ret void
 ;
 ;
 ; CHECK-LABEL: @f2(
 ; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
-; CHECK-NEXT:    store i32 2, i32* [[A]], align 4
+; CHECK-NEXT:    musttail call tailcc void @outlined_ir_func_0(i32* [[A]])
+; CHECK-NEXT:    ret void
+;
+;
+; CHECK-LABEL: define internal tailcc void @outlined_ir_func_0(
+; CHECK-NEXT:  newFuncRoot:
+; CHECK-NEXT:    br label [[_TO_OUTLINE:%.*]]
+; CHECK:       _to_outline:
+; CHECK-NEXT:    store i32 2, i32* [[TMP0:%.*]], align 4
 ; CHECK-NEXT:    musttail call tailcc void @musttail()
 ; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/IROutliner/phi-nodes-non-constant.ll

 ;
 ; CHECK-LABEL: @function2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    call void @outlined_ir_func_0(i32* [[TMP0]], i32* [[A:%.*]], i32* [[B:%.*]])
 ; CHECK-NEXT:    ret void
 ;
 ;
-; CHECK: define internal void @outlined_ir_func_0(
+; CHECK-LABEL: define internal void @outlined_ir_func_0(
 ; CHECK-NEXT:  newFuncRoot:
 ; CHECK-NEXT:    br label [[ENTRY_TO_OUTLINE:%.*]]
 ; CHECK:       entry_to_outline:
 ; CHECK-NEXT:    [[C:%.*]] = load i32, i32* [[TMP0:%.*]], align 4
 ; CHECK-NEXT:    br label [[TEST1:%.*]]
 ; CHECK:       test1:
 ; CHECK-NEXT:    [[E:%.*]] = load i32, i32* [[TMP0]], align 4
 ; CHECK-NEXT:    br label [[FIRST:%.*]]
 ; CHECK:       test:
 ; CHECK-NEXT:    [[D:%.*]] = load i32, i32* [[TMP0]], align 4
 ; CHECK-NEXT:    br label [[FIRST]]
 ; CHECK:       first:
 ; CHECK-NEXT:    [[TMP3:%.*]] = phi i32 [ [[C]], [[TEST:%.*]] ], [ [[E]], [[TEST1]] ]
 ; CHECK-NEXT:    store i32 2, i32* [[TMP1:%.*]], align 4
 ; CHECK-NEXT:    store i32 3, i32* [[TMP2:%.*]], align 4
-; CHECK-NEXT:    br label [[ENTRY_AFTER_OUTLINE_EXITSTUB:%.*]]
-; CHECK:       entry_after_outline.exitStub:
 ; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/IROutliner/phi-nodes-simple.ll

 ; CHECK-LABEL: @function2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[TEST:%.*]]
 ; CHECK:       test:
 ; CHECK-NEXT:    call void @outlined_ir_func_0(i32* [[A:%.*]], i32* [[B:%.*]])
 ; CHECK-NEXT:    ret void
 ;
 ;
-; CHECK: define internal void @outlined_ir_func_0(
+; CHECK-LABEL: define internal void @outlined_ir_func_0(
 ; CHECK-NEXT:  newFuncRoot:
 ; CHECK-NEXT:    br label [[TEST_TO_OUTLINE:%.*]]
 ; CHECK:       test_to_outline:
 ; CHECK-NEXT:    br label [[FIRST:%.*]]
 ; CHECK:       first:
 ; CHECK-NEXT:    [[TMP2:%.*]] = phi i32 [ 0, [[TEST_TO_OUTLINE]] ]
 ; CHECK-NEXT:    store i32 2, i32* [[TMP0:%.*]], align 4
 ; CHECK-NEXT:    store i32 3, i32* [[TMP1:%.*]], align 4
-; CHECK-NEXT:    br label [[TEST_AFTER_OUTLINE_EXITSTUB:%.*]]
-; CHECK:       test_after_outline.exitStub:
 ; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/IROutliner/region-end-of-module.ll

 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    call void @outlined_ir_func_0()
 ; CHECK-NEXT:    unreachable
 ; CHECK:       for.end:
 ; CHECK-NEXT:    [[INC3:%.*]] = add nsw i32 2, 1
 ; CHECK-NEXT:    unreachable
 ;
 ;
-; CHECK: define internal void @outlined_ir_func_0(
+; CHECK-LABEL: define internal void @outlined_ir_func_0(
 ; CHECK-NEXT:  newFuncRoot:
 ; CHECK-NEXT:    br label [[ENTRY_TO_OUTLINE:%.*]]
 ; CHECK:       entry_to_outline:
 ; CHECK-NEXT:    br label [[FOR_COND1:%.*]]
 ; CHECK:       for.cond1:
 ; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
 ; CHECK:       for.body:
 ; CHECK-NEXT:    [[INC:%.*]] = add nsw i32 2, 1
-; CHECK-NEXT:    br label [[ENTRY_AFTER_OUTLINE_EXITSTUB:%.*]]
-; CHECK:       entry_after_outline.exitStub:
 ; CHECK-NEXT:    ret void
 ;
 ;
-; CHECK: define internal void @outlined_ir_func_1(
+; CHECK-LABEL: define internal void @outlined_ir_func_1(
 ; CHECK-NEXT:  newFuncRoot:
 ; CHECK-NEXT:    br label [[FOR_BODY_TO_OUTLINE:%.*]]
 ; CHECK:       for.body_to_outline:
 ; CHECK-NEXT:    [[INC:%.*]] = add nsw i32 2, 1
-; CHECK-NEXT:    br label [[FOR_COND1_EXITSTUB:%.*]]
-; CHECK:       for.cond1.exitStub:
 ; CHECK-NEXT:    ret void
 ;