[AMDGPU] gfx940 removes all image instructions

[kzhuravl]

lgtm

llvm/lib/Target/AMDGPU/AMDGPU.td

 >;
 
 def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
   "HasNSAEncoding",
   "true",
   "Support NSA encoding for image instructions"
 >;
 
+def FeatureImageInsts : SubtargetFeature<"image-insts",
+  "HasImageInsts",
+  "true",
+  "Support image instructions"
+>;
+
 def FeatureExtendedImageInsts : SubtargetFeature<"extended-image-insts",
   "HasExtendedImageInsts",
   "true",
   "Support mips != 0, lod != 0, gather4, and get_lod"
 >;
 
 def FeatureGFX10_AEncoding : SubtargetFeature<"gfx10_a-encoding",
   "GFX10_AEncoding",
class GCNSubtargetFeatureGeneration <string Value,
                                      list<SubtargetFeature> Implies> :
         SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
 
 def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
     "southern-islands",
   [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
   FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
   FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
-  FeatureTrigReducedRange, FeatureExtendedImageInsts
+  FeatureTrigReducedRange, FeatureExtendedImageInsts, FeatureImageInsts
   ]
 >;
 
 def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
     "sea-islands",
   [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
   FeatureWavefrontSize64, FeatureFlatAddressSpace,
   FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
-  FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureUnalignedBufferAccess
+  FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureUnalignedBufferAccess,
+  FeatureImageInsts
   ]
 >;
 
 def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
   "volcanic-islands",
   [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
    FeatureWavefrontSize64, FeatureFlatAddressSpace,
    FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
    FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
    FeatureScalarStores, FeatureInv2PiInlineImm,
    FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
    FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
    FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
    FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureFastDenormalF32,
-   FeatureUnalignedBufferAccess
+   FeatureUnalignedBufferAccess, FeatureImageInsts
   ]
 >;
 
 def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
   "gfx9",
   [FeatureFP64, FeatureLocalMemorySize65536,
    FeatureWavefrontSize64, FeatureFlatAddressSpace,
    FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
    FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
    FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
    FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
    FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
    FeatureNoSdstCMPX, FeatureVscnt,
    FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts,
    FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
    FeatureGFX10A16, FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureG16,
-   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
+   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess, FeatureImageInsts
   ]
 >;
 
 class FeatureSet<list<SubtargetFeature> Features_> {
   list<SubtargetFeature> Features = Features_;
 }
 
 def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
def FeatureISAVersion8_1_0 : FeatureSet<
    FeatureImageGather4D16Bug]>;
 
 def FeatureISAVersion9_0_0 : FeatureSet<
   [FeatureGFX9,
    FeatureMadMixInsts,
    FeatureLDSBankCount32,
    FeatureDsSrc2Insts,
    FeatureExtendedImageInsts,
+   FeatureImageInsts,
    FeatureMadMacF32Insts,
    FeatureImageGather4D16Bug]>;
 
 def FeatureISAVersion9_0_2 : FeatureSet<
   [FeatureGFX9,
    FeatureMadMixInsts,
    FeatureLDSBankCount32,
    FeatureDsSrc2Insts,
    FeatureExtendedImageInsts,
+   FeatureImageInsts,
    FeatureMadMacF32Insts,
    FeatureImageGather4D16Bug]>;
 
 def FeatureISAVersion9_0_4 : FeatureSet<
   [FeatureGFX9,
    FeatureLDSBankCount32,
    FeatureDsSrc2Insts,
    FeatureExtendedImageInsts,
+   FeatureImageInsts,
    FeatureMadMacF32Insts,
    FeatureFmaMixInsts,
    FeatureImageGather4D16Bug]>;
 
 def FeatureISAVersion9_0_6 : FeatureSet<
   [FeatureGFX9,
    HalfRate64Ops,
    FeatureFmaMixInsts,
    FeatureLDSBankCount32,
    FeatureDsSrc2Insts,
    FeatureExtendedImageInsts,
+   FeatureImageInsts,
    FeatureMadMacF32Insts,
    FeatureDLInsts,
    FeatureDot1Insts,
    FeatureDot2Insts,
    FeatureDot7Insts,
    FeatureSupportsSRAMECC,
    FeatureImageGather4D16Bug]>;
 
 def FeatureISAVersion9_0_8 : FeatureSet<
   [FeatureGFX9,
    HalfRate64Ops,
    FeatureFmaMixInsts,
    FeatureLDSBankCount32,
    FeatureDsSrc2Insts,
    FeatureExtendedImageInsts,
+   FeatureImageInsts,
    FeatureMadMacF32Insts,
    FeatureDLInsts,
    FeatureDot1Insts,
    FeatureDot2Insts,
    FeatureDot3Insts,
    FeatureDot4Insts,
    FeatureDot5Insts,
    FeatureDot6Insts,
    FeatureDot7Insts,
    FeatureMAIInsts,
    FeaturePkFmacF16Inst,
    FeatureAtomicFaddInsts,
    FeatureSupportsSRAMECC,
    FeatureMFMAInlineLiteralBug,
    FeatureImageGather4D16Bug]>;
 
 def FeatureISAVersion9_0_9 : FeatureSet<
   [FeatureGFX9,
    FeatureMadMixInsts,
    FeatureLDSBankCount32,
    FeatureDsSrc2Insts,
    FeatureExtendedImageInsts,
+   FeatureImageInsts,
    FeatureMadMacF32Insts,
    FeatureImageGather4D16Bug]>;
 
 def FeatureISAVersion9_0_A : FeatureSet<
   [FeatureGFX9,
    FeatureGFX90AInsts,
    FeatureFmaMixInsts,
    FeatureLDSBankCount32,
    FeatureDLInsts,
    FeatureDot1Insts,
    FeatureDot2Insts,
    FeatureDot3Insts,
    FeatureDot4Insts,
    FeatureDot5Insts,
    FeatureDot6Insts,
    FeatureDot7Insts,
    Feature64BitDPP,
    FeaturePackedFP32Ops,
    FeatureMAIInsts,
    FeaturePkFmacF16Inst,
    FeatureAtomicFaddInsts,
+   FeatureImageInsts,
    FeatureMadMacF32Insts,
    FeatureSupportsSRAMECC,
    FeaturePackedTID,
    FullRate64Ops]>;
 
 def FeatureISAVersion9_0_C : FeatureSet<
   [FeatureGFX9,
    FeatureMadMixInsts,
    FeatureLDSBankCount32,
    FeatureDsSrc2Insts,
    FeatureExtendedImageInsts,
+   FeatureImageInsts,
    FeatureMadMacF32Insts,
    FeatureImageGather4D16Bug]>;
 
 def FeatureISAVersion9_4_0 : FeatureSet<
   [FeatureGFX9,
    FeatureGFX90AInsts,
    FeatureGFX940Insts,
    FeatureFmaMixInsts,

 
 def HasPackedFP32Ops : Predicate<"Subtarget->hasPackedFP32Ops()">,
   AssemblerPredicate<(all_of FeaturePackedFP32Ops)>;
 
 def HasFmaakFmamkF32Insts :
   Predicate<"Subtarget->hasFmaakFmamkF32Insts()">,
   AssemblerPredicate<(any_of FeatureGFX10Insts)>;
 
+def HasImageInsts : Predicate<"Subtarget->hasImageInsts()">,
+  AssemblerPredicate<(all_of FeatureImageInsts)>;
+
 def HasExtendedImageInsts : Predicate<"Subtarget->hasExtendedImageInsts()">,
   AssemblerPredicate<(all_of FeatureExtendedImageInsts)>;
 
 def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
   AssemblerPredicate<(all_of FeatureR128A16)>;
 
 def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
   AssemblerPredicate<(all_of FeatureGFX10A16)>;

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
     HasSDWAScalar(false),
     HasSDWASdst(false),
     HasSDWAMac(false),
     HasSDWAOutModsVOPC(false),
     HasDPP(false),
     HasDPP8(false),
     Has64BitDPP(false),
     HasPackedFP32Ops(false),
+    HasImageInsts(false),
     HasExtendedImageInsts(false),
     HasR128A16(false),
     HasGFX10A16(false),
     HasG16(false),
     HasNSAEncoding(false),
     NSAMaxSize(0),
     GFX10_AEncoding(false),
     GFX10_BEncoding(false),

llvm/lib/Target/AMDGPU/GCNSubtarget.h

protected:
   bool HasSDWAScalar;
   bool HasSDWASdst;
   bool HasSDWAMac;
   bool HasSDWAOutModsVOPC;
   bool HasDPP;
   bool HasDPP8;
   bool Has64BitDPP;
   bool HasPackedFP32Ops;
+  bool HasImageInsts;
   bool HasExtendedImageInsts;
   bool HasR128A16;
   bool HasGFX10A16;
   bool HasG16;
   bool HasNSAEncoding;
   unsigned NSAMaxSize;
   bool GFX10_AEncoding;
   bool GFX10_BEncoding;
public:
   bool hasPackedFP32Ops() const {
     return HasPackedFP32Ops;
   }
 
   bool hasFmaakFmamkF32Insts() const {
     return getGeneration() >= GFX10;
   }
 
+  bool hasImageInsts() const {
+    return HasImageInsts;
+  }
+
   bool hasExtendedImageInsts() const {
     return HasExtendedImageInsts;
   }
 
   bool hasR128A16() const {
     return HasR128A16;
   }
 

llvm/lib/Target/AMDGPU/MIMGInstructions.td

def _nsa_gfx10 : MIMG_IntersectRay_nsa_gfx10<op, opcode, info.num_addrs, A16> {
       let VAddrDwords = info.num_addrs;
     }
   }
 }
 
 //===----------------------------------------------------------------------===//
 // MIMG Instructions
 //===----------------------------------------------------------------------===//
+let OtherPredicates = [HasImageInsts] in {
+
 defm IMAGE_LOAD                 : MIMG_NoSampler <mimgopc<0x00>, "image_load", 1>;
 defm IMAGE_LOAD_MIP             : MIMG_NoSampler <mimgopc<0x01>, "image_load_mip", 1, 1>;
 defm IMAGE_LOAD_PCK             : MIMG_NoSampler <mimgopc<0x02>, "image_load_pck", 0>;
 defm IMAGE_LOAD_PCK_SGN         : MIMG_NoSampler <mimgopc<0x03>, "image_load_pck_sgn", 0>;
 defm IMAGE_LOAD_MIP_PCK         : MIMG_NoSampler <mimgopc<0x04>, "image_load_mip_pck", 0, 1>;
 defm IMAGE_LOAD_MIP_PCK_SGN     : MIMG_NoSampler <mimgopc<0x05>, "image_load_mip_pck_sgn", 0, 1>;
 defm IMAGE_STORE                : MIMG_Store <mimgopc<0x08>, "image_store", 1>;
 defm IMAGE_STORE_MIP            : MIMG_Store <mimgopc<0x09>, "image_store_mip", 1, 1>;

 let SubtargetPredicate = HasGFX10_AEncoding in
 defm IMAGE_MSAA_LOAD_X : MIMG_NoSampler <mimgopc<0x80>, "image_msaa_load", 1, 0, 0, 1>;
 
 defm IMAGE_BVH_INTERSECT_RAY       : MIMG_IntersectRay<mimgopc<0xe6>, "image_bvh_intersect_ray", 0, 0>;
 defm IMAGE_BVH_INTERSECT_RAY_a16   : MIMG_IntersectRay<mimgopc<0xe6>, "image_bvh_intersect_ray", 0, 1>;
 defm IMAGE_BVH64_INTERSECT_RAY     : MIMG_IntersectRay<mimgopc<0xe7>, "image_bvh64_intersect_ray", 1, 0>;
 defm IMAGE_BVH64_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<0xe7>, "image_bvh64_intersect_ray", 1, 1>;
 
+} // End let OtherPredicates = [HasImageInsts]
+
 /********** ========================================= **********/
 /********** Table of dimension-aware image intrinsics **********/
 /********** ========================================= **********/
 
 class ImageDimIntrinsicInfo<AMDGPUImageDimIntrinsic I> {
   Intrinsic Intr = I;
   MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(!strconcat("IMAGE_", I.P.OpMod));
   AMDGPUDimProps Dim = I.P.Dim;

llvm/test/MC/AMDGPU/mimg-err-gfx940.s

+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx940 %s 2>&1 | FileCheck %s --check-prefix=NOGFX940 --implicit-check-not=error:
+
+image_load v[4:6], v[238:241], s[28:35] dmask:0x7 unorm
+// NOGFX940: error:
+
+image_load_pck v5, v[0:3], s[8:15] dmask:0x1 glc
+// NOGFX940: error:
+
+image_load_pck_sgn v5, v[0:3], s[8:15] dmask:0x1 lwe
+// NOGFX940: error:
+
+image_load_mip v5, v[0:3], s[8:15]
+// NOGFX940: error: instruction not supported on this GPU
+
+image_load_mip_pck v5, v1, s[8:15] dmask:0x1
+// NOGFX940: error:
+
+image_load_mip_pck_sgn v[4:5], v[0:3], s[8:15] dmask:0x5
+// NOGFX940: error:
+
+image_store v[192:194], v[238:241], s[28:35] dmask:0x7 unorm
+// NOGFX940: error:
+
+image_store_pck v1, v[2:5], s[12:19] dmask:0x1 unorm da
+// NOGFX940: error:
+
+image_store_mip v1, v[2:5], s[12:19]
+// NOGFX940: error: instruction not supported on this GPU
+
+image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 a16
+// NOGFX940: error:
+
+image_atomic_add v4, v192, s[28:35] dmask:0x1 unorm glc
+// NOGFX940: error:
+
+image_atomic_and v4, v192, s[28:35] dmask:0x1 unorm
+// NOGFX940: error:
+
+image_atomic_swap v4, v[192:195], s[28:35] dmask:0x1 unorm glc
+// NOGFX940: error:
+
+image_atomic_cmpswap v[4:5], v[192:195], s[28:35] dmask:0x3 unorm glc
+// NOGFX940: error:
+
+image_atomic_or v4, v192, s[28:35] dmask:0x1 unorm
+// NOGFX940: error:
+
+image_atomic_xor v4, v192, s[28:35] dmask:0x1 unorm
+// NOGFX940: error:
+
+image_atomic_sub v4, v192, s[28:35] dmask:0x1 unorm
+// NOGFX940: error:
+
+image_atomic_smin v4, v192, s[28:35] dmask:0x1 unorm
+// NOGFX940: error:
+
+image_atomic_smax v4, v192, s[28:35] dmask:0x1 unorm
+// NOGFX940: error:
+
+image_atomic_umin v4, v192, s[28:35] dmask:0x1 unorm
+// NOGFX940: error:
+
+image_atomic_umax v4, v192, s[28:35] dmask:0x1 unorm
+// NOGFX940: error:
+
+image_atomic_inc v4, v192, s[28:35] dmask:0x1 unorm
+// NOGFX940: error:
+
+image_atomic_dec v4, v192, s[28:35] dmask:0x1 unorm
+// NOGFX940: error:
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1
+// NOGFX940: error:
+
+image_sample v5, v[0:3], s[8:15], s[12:15] dmask:0x1
+// NOGFX940: error:
+
+image_gather4 v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// NOGFX940: error: