[LoongArch] Add EncoderMethods for transformed immediate operands

[SixWeining]

Summary

This is a split patch of D120476 and thanks to myhsu.

'Transformed' means the encoding of an immediate is not the same as
its binary representation. For example, the bl instruction
requires a signed 28-bits integer as its operand and the low 2 bits
must be 0. So only the upper 26 bits are needed to get encoded into
the instruction.

Based on the above reason this kind of immediate needs a customed
EncoderMethod to get the real value getting encoded into the
instruction.

Currently these immediate includes:

uimm2_plus1
simm14_lsl2
simm16_lsl2
simm21_lsl2
simm26_lsl2

This patch adds those EncoderMethods and revises related .mir test
in previous patch.

[myhsu]

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp

55

are these two functions dedicated to the unusual immediate you mentioned in another patch? If so, can you add some description comments here?

[SixWeining]

Add description comments to the 2 new functions to address @myhsu's comments.

[SixWeining]

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp

55

Yes, they are dedicated to those unusual immediates. I just add some descriptions which I think may improve code readability. Many thanks!

[xen0n]

Maybe something like "transformed operands" is better than "unusual", for the changeset title? The code looks good though, only one minor nit.

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp

64–65

/// The value returned is the value of the immediate shifted right
/// arithmetically by 2.

[SixWeining]

Per @xen0n's comments, change the title from 'unusual' to 'transformed'. Thanks!

[SixWeining]

Fix the nit. Sorry I missed it in last revision.

[xen0n]

The code changes seem good to me. Thanks for fixing the nit!

The title is still somewhat Chinglish-sounding though (wrong plurals), "[LoongArch] Add EncoderMethods for transformed immediate operands" is better.

(Still, approval from someone else would be nice before merging, as usual.)

[SixWeining]

In D120545#3348186, @xen0n wrote:

The code changes seem good to me. Thanks for fixing the nit!

The title is still somewhat Chinglish-sounding though (wrong plurals), "[LoongArch] Add EncoderMethods for transformed immediate operands" is better.

(Still, approval from someone else would be nice before merging, as usual.)

Yes, that looks good. Thanks.

[MaskRay]

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp

94

delete unneeded blank line

97

Inline used-once variable

101

llvm_unreachable does not need a following return

Optional: For regular diagnostics, see https://llvm.org/docs/CodingStandards.html#error-and-warning-messages for the recommended style. I know that some llvm_unreachable used capitalized messages.

117

llvm_unreachable does not need a following return

[SixWeining]

Address @MaskRay's comments. Thanks!

Delete unneeded blank line and returns.

[SixWeining]

Thanks! Just updated the revision.

[rengolin]

With the nit, this looks good to me too, thanks!

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp

97

Not sure what's better here, assert(MO.isImm()) or llvm_unreachable.

On the function above, you return 0 even after llvm_unreachable, but here you don't.

Is that because of compiler warnings? I believe this shouldn't be necessary, but I could be wrong.

[SixWeining]

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp

97

Seems assert is better because this function is dedicated for the uimm2_plus1 immideate operand. It's impossible to be other operand.

As @MaskRay said, llvm_unreachable does not need a following return. In llvm/include/llvm/Support/ErrorHandling.h, I see:

/// This function calls abort(), and prints the optional message to stderr.
/// Use the llvm_unreachable macro (that adds location info), instead of
/// calling this function directly.
[[noreturn]] void
llvm_unreachable_internal(const char *msg = nullptr, const char *file = nullptr,
                          unsigned line = 0); 
}

/// Marks that the current location is not supposed to be reachable.
/// In !NDEBUG builds, prints the message and location info to stderr.
/// In NDEBUG builds, becomes an optimizer hint that the current location
/// is not supposed to be reachable.  On compilers that don't support
/// such hints, prints a reduced message instead and aborts the program.
///
/// Use this instead of assert(0).  It conveys intent more clearly and
/// allows compilers to omit some unnecessary code.
#ifndef NDEBUG
#define llvm_unreachable(msg) \
  ::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
#elif defined(LLVM_BUILTIN_UNREACHABLE)
#define llvm_unreachable(msg) LLVM_BUILTIN_UNREACHABLE
#else
#define llvm_unreachable(msg) ::llvm::llvm_unreachable_internal()
#endif

#endif

Here llvm_unreachable_internal() is marked with [[noreturn]].

As the above function, since it's not introduced in this patch, I will delete the unnecessary return 0 in a seperate patch.

[SixWeining]

Use assert instead of if()... to check input.

[MaskRay]

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp

94

Just use return MO.getImm() - 1;

getImm has an internal assert(isImm() && ...

[MaskRay]

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp

105

Delete assert. getImm has an internal assert

[SixWeining]

Address @MaskRay's comments.

Delete redundant assert.

[SixWeining]

Thanks. I have updated the revision.

[MaskRay]

LGTM.

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

class SImmAsmOperand<int width, string suffix = "">
     : ImmAsmOperand<"S", width, suffix> {
 }
 
 class UImmAsmOperand<int width, string suffix = "">
     : ImmAsmOperand<"U", width, suffix> {
 }
 
 def uimm2 : Operand<GRLenVT>;
-def uimm2_plus1 : Operand<GRLenVT>;
+def uimm2_plus1 : Operand<GRLenVT> {
+  let EncoderMethod = "getImmOpValueSub1";
+}
 def uimm3 : Operand<GRLenVT>;
 def uimm5 : Operand<GRLenVT>;
 def uimm6 : Operand<GRLenVT>;
 def uimm12 : Operand<GRLenVT>;
 def uimm15 : Operand<GRLenVT>;
 def simm12 : Operand<GRLenVT>, ImmLeaf<GRLenVT, [{return isInt<12>(Imm);}]>;
 def simm14 : Operand<GRLenVT>;
-def simm14_lsl2 : Operand<GRLenVT>;
+def simm14_lsl2 : Operand<GRLenVT> {
+  let EncoderMethod = "getImmOpValueAsr2";
+}
 def simm16 : Operand<GRLenVT>;
-def simm16_lsl2 : Operand<GRLenVT>;
+def simm16_lsl2 : Operand<GRLenVT> {
+  let EncoderMethod = "getImmOpValueAsr2";
+}
 def simm20 : Operand<GRLenVT>;
-def simm21_lsl2 : Operand<GRLenVT>;
-def simm26_lsl2 : Operand<GRLenVT>;
+def simm21_lsl2 : Operand<GRLenVT> {
+  let EncoderMethod = "getImmOpValueAsr2";
+}
+def simm26_lsl2 : Operand<GRLenVT> {
+  let EncoderMethod = "getImmOpValueAsr2";
+}
 
 //===----------------------------------------------------------------------===//
 // Instruction Formats
 //===----------------------------------------------------------------------===//
 
 include "LoongArchInstrFormats.td"
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp

uint64_t getBinaryCodeForInstr(const MCInst &MI,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
 
   /// Return binary encoding of operand. If the machine operand requires
   /// relocation, record the relocation and return zero.
   unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
+
+  /// Return binary encoding of an immediate operand specified by OpNo.
+  /// The value returned is the value of the immediate minus 1.
+  /// Note that this function is dedicated to specific immediate types,
+  /// e.g. uimm2_plus1.
+  unsigned getImmOpValueSub1(const MCInst &MI, unsigned OpNo,
+                             SmallVectorImpl<MCFixup> &Fixups,
+                             const MCSubtargetInfo &STI) const;
+
+  /// Return binary encoding of an immediate operand specified by OpNo.
+  /// The value returned is the value of the immediate arithmetical right
+  //  shifts 2.
+  /// Note that this function is dedicated to specific immediate types,
+  /// e.g. simm14_lsl2, simm16_lsl2, simm21_lsl2 and simm26_lsl2.
+  unsigned getImmOpValueAsr2(const MCInst &MI, unsigned OpNo,
+                             SmallVectorImpl<MCFixup> &Fixups,
+                             const MCSubtargetInfo &STI) const;
 };
 } // end anonymous namespace
 
 unsigned
 LoongArchMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                                           SmallVectorImpl<MCFixup> &Fixups,
                                           const MCSubtargetInfo &STI) const {
 
   if (MO.isReg())
     return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
 
   if (MO.isImm())
     return static_cast<unsigned>(MO.getImm());
 
   llvm_unreachable("Unhandled expression!");
   return 0;
 }
 
+unsigned
+LoongArchMCCodeEmitter::getImmOpValueSub1(const MCInst &MI, unsigned OpNo,
+                                          SmallVectorImpl<MCFixup> &Fixups,
+                                          const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpNo);
+
+  if (MO.isImm()) {
+    unsigned Res = MO.getImm();
+    return Res - 1;
+  }
+
+  llvm_unreachable("Unhandled expression!");
+  return 0;
+}
+
+unsigned
+LoongArchMCCodeEmitter::getImmOpValueAsr2(const MCInst &MI, unsigned OpNo,
+                                          SmallVectorImpl<MCFixup> &Fixups,
+                                          const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpNo);
+
+  if (MO.isImm()) {
+    unsigned Res = MO.getImm();
+    assert((Res & 3) == 0 && "lowest 2 bits are non-zero");
+    return Res >> 2;
+  }
+
+  llvm_unreachable("Unhandled expression!");
+  return 0;
+}
+
 void LoongArchMCCodeEmitter::encodeInstruction(
     const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
     const MCSubtargetInfo &STI) const {
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   // Get byte count of instruction.
   unsigned Size = Desc.getSize();
 
   switch (Size) {

llvm/test/CodeGen/LoongArch/1ri.mir

 #  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
 # ------------------+-----------------------------------------------+--------------+---------------
 #      opcode       |                    imm21{15-0}                |      rj      | imm21{20-16}
 # ------------------+-----------------------------------------------+--------------+---------------
 
 ---
 # CHECK-LABEL: test_BEQZ:
 # CHECK-ENC: 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0
-# CHECK-ASM: beqz $a0, 23
+# CHECK-ASM: beqz $a0, 92
 name: test_BEQZ
 body: |
   bb.0:
-    BEQZ $r4, 23
+    BEQZ $r4, 92
 ...
 ---
 # CHECK-LABEL: test_BNEZ:
 # CHECK-ENC: 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0
-# CHECK-ASM: bnez $a0, 21
+# CHECK-ASM: bnez $a0, 84
 name: test_BNEZ
 body: |
   bb.0:
-    BNEZ $r4, 21
+    BNEZ $r4, 84

llvm/test/CodeGen/LoongArch/2ri.mir

 #  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
 # ------------------------+-----------------------------------------+--------------+---------------
 #         opcode          |              imm14                      |      rj      |      rd
 # ------------------------+-----------------------------------------+--------------+---------------
 
 ---
 # CHECK-LABEL: test_LDPTR_W:
 # CHECK-ENC: 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0
-# CHECK-ASM: ldptr.w  $a0, $a1, 66
+# CHECK-ASM: ldptr.w  $a0, $a1, 264
 name: test_LDPTR_W
 body: |
   bb.0:
-    $r4 = LDPTR_W $r5, 66
+    $r4 = LDPTR_W $r5, 264
 ...
 ---
 # CHECK-LABEL: test_LDPTR_D:
 # CHECK-ENC: 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0
-# CHECK-ASM: ldptr.d  $a0, $a1, 56
+# CHECK-ASM: ldptr.d  $a0, $a1, 224
 name: test_LDPTR_D
 body: |
   bb.0:
-    $r4 = LDPTR_D $r5, 56
+    $r4 = LDPTR_D $r5, 224
 ...
 ---
 # CHECK-LABEL: test_STPTR_W:
 # CHECK-ENC: 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0
-# CHECK-ASM: stptr.w  $a0, $a1, 87
+# CHECK-ASM: stptr.w  $a0, $a1, 348
 name: test_STPTR_W
 body: |
   bb.0:
-    STPTR_W $r4, $r5, 87
+    STPTR_W $r4, $r5, 348
 ...
 ---
 # CHECK-LABEL: test_STPTR_D:
 # CHECK-ENC: 0 0 1 0 0 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0
-# CHECK-ASM: stptr.d  $a0, $a1, 145
+# CHECK-ASM: stptr.d  $a0, $a1, 580
 name: test_STPTR_D
 body: |
   bb.0:
-    STPTR_D $r4, $r5, 145
+    STPTR_D $r4, $r5, 580
 ...
 ---
 # CHECK-LABEL: test_LL_W:
 # CHECK-ENC: 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0
-# CHECK-ASM: ll.w $a0, $a1, 243
+# CHECK-ASM: ll.w $a0, $a1, 972
 name: test_LL_W
 body: |
   bb.0:
-    $r4 = LL_W $r5, 243
+    $r4 = LL_W $r5, 972
 ...
 ---
 # CHECK-LABEL: test_LL_D:
 # CHECK-ENC: 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0
-# CHECK-ASM: ll.d $a0, $a1, 74
+# CHECK-ASM: ll.d $a0, $a1, 296
 name: test_LL_D
 body: |
   bb.0:
-    $r4 = LL_D $r5, 74
+    $r4 = LL_D $r5, 296
 ...
 ---
 # CHECK-LABEL: test_SC_W:
 # CHECK-ENC: 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0
-# CHECK-ASM: sc.w $a0, $a1, 96
+# CHECK-ASM: sc.w $a0, $a1, 384
 name: test_SC_W
 body: |
   bb.0:
-    $r4 = SC_W $r4, $r5, 96
+    $r4 = SC_W $r4, $r5, 384
 ...
 ---
 # CHECK-LABEL: test_SC_D:
 # CHECK-ENC: 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0
-# CHECK-ASM: sc.d $a0, $a1, 105
+# CHECK-ASM: sc.d $a0, $a1, 420
 name: test_SC_D
 body: |
   bb.0:
-    $r4 = SC_D $r4, $r5, 105
+    $r4 = SC_D $r4, $r5, 420
 ...
 
 # -------------------------------------------------------------------------------------------------
 #                                           Encoding format: 2RI16
 # -------------------------------------------------------------------------------------------------
 # ------------------+-----------------------------------------------+--------------+---------------
 #  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
 # ------------------+-----------------------------------------------+--------------+---------------
 #     opcode        |                imm16                          |      rj      |      rd
 # ------------------+-----------------------------------------------+--------------+---------------
 
 ---
 # CHECK-LABEL: test_ADDU16I_D:
 # CHECK-ENC: 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0
 # CHECK-ASM: addu16i.d  $a0, $a1, 23
 name: test_ADDU16I_D
 body: |
   bb.0:
     $r4 = ADDU16I_D $r5, 23
 ...
 ---
 # CHECK-LABEL: test_JIRL:
 # CHECK-ENC: 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0
-# CHECK-ASM: jirl $a0, $a1, 49
+# CHECK-ASM: jirl $a0, $a1, 196
 name: test_JIRL
 body: |
   bb.0:
-    $r4 = JIRL $r5, 49
+    $r4 = JIRL $r5, 196
 ...
 ---
 # CHECK-LABEL: test_BEQ:
 # CHECK-ENC: 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1
-# CHECK-ASM: beq  $a0, $a1, 196
+# CHECK-ASM: beq  $a0, $a1, 784
 name: test_BEQ
 body: |
   bb.0:
-    BEQ $r4, $r5, 196
+    BEQ $r4, $r5, 784
 ...
 ---
 # CHECK-LABEL: test_BNE:
 # CHECK-ENC: 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1
-# CHECK-ASM: bne  $a0, $a1, 19
+# CHECK-ASM: bne  $a0, $a1, 76
 name: test_BNE
 body: |
   bb.0:
-    BNE $r4, $r5, 19
+    BNE $r4, $r5, 76
 ...
 ---
 # CHECK-LABEL: test_BLT:
 # CHECK-ENC: 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 0 0 0 0 1 0 1
-# CHECK-ASM: blt  $a0, $a1, 123
+# CHECK-ASM: blt  $a0, $a1, 492
 name: test_BLT
 body: |
   bb.0:
-    BLT $r4, $r5, 123
+    BLT $r4, $r5, 492
 ...
 ---
 # CHECK-LABEL: test_BGE:
 # CHECK-ENC: 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 1
-# CHECK-ASM: bge  $a0, $a1, 12
+# CHECK-ASM: bge  $a0, $a1, 48
 name: test_BGE
 body: |
   bb.0:
-    BGE $r4, $r5, 12
+    BGE $r4, $r5, 48
 ...
 ---
 # CHECK-LABEL: test_BLTU:
 # CHECK-ENC: 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 1
-# CHECK-ASM: bltu $a0, $a1, 17
+# CHECK-ASM: bltu $a0, $a1, 68
 name: test_BLTU
 body: |
   bb.0:
-    BLTU $r4, $r5, 17
+    BLTU $r4, $r5, 68
 ...
 ---
 # CHECK-LABEL: test_BGEU:
 # CHECK-ENC: 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1
-# CHECK-ASM: bgeu $a0, $a1, 88
+# CHECK-ASM: bgeu $a0, $a1, 352
 name: test_BGEU
 body: |
   bb.0:
-    BGEU $r4, $r5, 88
+    BGEU $r4, $r5, 352

llvm/test/CodeGen/LoongArch/3ri.mir

 #  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
 # ---------------------------------------------+-----+--------------+--------------+---------------
 #                  opcode                      |imm2 |      rk      |      rj      |      rd
 # ---------------------------------------------+-----+--------------+--------------+---------------
 
 ---
 # CHECK-LABEL: test_ALSL_W:
 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
-# CHECK-ASM: alsl.w $a0, $a1, $a2, 3
+# CHECK-ASM: alsl.w $a0, $a1, $a2, 4
 name: test_ALSL_W
 body: |
   bb.0:
-    $r4 = ALSL_W $r5, $r6, 3
+    $r4 = ALSL_W $r5, $r6, 4
 ...
 ---
 # CHECK-LABEL: test_ALSL_WU:
 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
-# CHECK-ASM: alsl.wu  $a0, $a1, $a2, 1
+# CHECK-ASM: alsl.wu  $a0, $a1, $a2, 2
 name: test_ALSL_WU
 body: |
   bb.0:
-    $r4 = ALSL_WU $r5, $r6, 1
+    $r4 = ALSL_WU $r5, $r6, 2
 ...
 ---
 # CHECK-LABEL: test_ALSL_D:
 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
-# CHECK-ASM: alsl.d $a0, $a1, $a2, 3
+# CHECK-ASM: alsl.d $a0, $a1, $a2, 4
 name: test_ALSL_D
 body: |
   bb.0:
-    $r4 = ALSL_D $r5, $r6, 3
+    $r4 = ALSL_D $r5, $r6, 4
 ...
 ---
 # CHECK-LABEL: test_BYTEPICK_W:
 # CHECK-ENC: 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0
 # CHECK-ASM: bytepick.w $a0, $a1, $a2, 0
 name: test_BYTEPICK_W
 body: |
   bb.0:

llvm/test/CodeGen/LoongArch/misc.mir

 #  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
 # ------------------+-----------------------------------------------+------------------------------
 #     opcode        |                   imm26{15-0}                 |       imm26{25-16}
 # ------------------+-----------------------------------------------+------------------------------
 
 ---
 # CHECK-LABEL: test_B:
 # CHECK-ENC: 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
-# CHECK-ASM: b  20
+# CHECK-ASM: b  80
 name: test_B
 body: |
   bb.0:
-    B 20
+    B 80
 ...
 ---
 # CHECK-LABEL: test_BL:
 # CHECK-ENC: 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
-# CHECK-ASM: bl 34
+# CHECK-ASM: bl 136
 name: test_BL
 body: |
   bb.0:
-    BL 34
+    BL 136
 ...
 
 # --------------------------------------------------------------------------------------------------------
 #                                           Encoding format: BSTR_W
 # --------------------------------------------------------------------------------------------------------
 # ---------------------------------+--------------+---------+--------------+--------------+---------------
 #  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16     15    14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
 # ---------------------------------+--------------+---------+--------------+--------------+---------------