[AMDGPU] Remove redundand check in the SILoadStoreOptimizer

[arsenm]

llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

751

Losing the S_BUFFER_LOAD_IMM check is suspicious but I'm not sure why it was here in the first place

[rampitec]

llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

751

a && (b || a) == a if I am not missing something.

I vaguely remember the history of this check. First it was comparing policy bits independently and s_buffer_load_imm did not have glc, so it was comparing with uninitialized memory. Then policy bits were combined into a single cpol operand and I guess the check was mechanically translated.

llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

bool SILoadStoreOptimizer::offsetsCanBeCombined(CombineInfo &CI,
   uint32_t EltOffset1 = Paired.Offset / CI.EltSize;
   CI.UseST64 = false;
   CI.BaseOff = 0;
 
   // Handle all non-DS instructions.
   if ((CI.InstClass != DS_READ) && (CI.InstClass != DS_WRITE)) {
     return (EltOffset0 + CI.Width == EltOffset1 ||
             EltOffset1 + Paired.Width == EltOffset0) &&
-           CI.CPol == Paired.CPol &&
-           (CI.InstClass == S_BUFFER_LOAD_IMM || CI.CPol == Paired.CPol);
+           CI.CPol == Paired.CPol;
   }
 
   // If the offset in elements doesn't fit in 8-bits, we might be able to use
   // the stride 64 versions.
   if ((EltOffset0 % 64 == 0) && (EltOffset1 % 64) == 0 &&
       isUInt<8>(EltOffset0 / 64) && isUInt<8>(EltOffset1 / 64)) {
     if (Modify) {
       CI.Offset = EltOffset0 / 64;