[CodeGen] Forward declare classes & remove includes

[clemenswasser]

Summary

llvm/CodeGen/Machine*.h, llvm/ADT/ArrayRef.h, llvm/IR/Instructions.h and llvm/CodeGen/SelectionDAG.h were identified as being quiet heavy by clang build analyzer.
Removing includes and forward declaring the relevant classes saves compilation time.

llvm/include/llvm/CodeGen/FastISel.h

   bool selectXRayCustomEvent(const CallInst *II);
   bool selectXRayTypedEvent(const CallInst *II);
 
-  bool shouldOptForSize(const MachineFunction *MF) const {
-    // TODO: Implement PGSO.
-    return MF->getFunction().hasOptSize();
-  }
+  bool shouldOptForSize(const MachineFunction *MF) const;
 
 private:
   /// Handle PHI nodes in successor blocks.

llvm/include/llvm/CodeGen/LivePhysRegs.h

 #define LLVM_CODEGEN_LIVEPHYSREGS_H
 
 #include "llvm/ADT/SparseSet.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include <cassert>

llvm/include/llvm/CodeGen/MachineFunction.h

 #ifndef LLVM_CODEGEN_MACHINEFUNCTION_H
 #define LLVM_CODEGEN_MACHINEFUNCTION_H
 
-#include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/GraphTraits.h"

llvm/include/llvm/CodeGen/MachineModuleInfo.h

 #ifndef LLVM_CODEGEN_MACHINEMODULEINFO_H
 #define LLVM_CODEGEN_MACHINEMODULEINFO_H
 
-#include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/PointerIntPair.h"
 #include "llvm/IR/PassManager.h"

llvm/include/llvm/CodeGen/ScheduleDAG.h

 #include "llvm/ADT/PointerIntPair.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/iterator.h"
-#include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/Support/ErrorHandling.h"
 #include <cassert>

 
     /// Adds a barrier edge to SU by calling addPred(), with latency 0
     /// generally or latency 1 for a store followed by a load.
-    bool addPredBarrier(SUnit *SU) {
-      SDep Dep(SU, SDep::Barrier);
-      unsigned TrueMemOrderLatency =
-        ((SU->getInstr()->mayStore() && this->getInstr()->mayLoad()) ? 1 : 0);
-      Dep.setLatency(TrueMemOrderLatency);
-      return addPred(Dep);
-    }
+    bool addPredBarrier(SUnit *SU);
 
     /// Removes the specified edge as a pred of the current node if it exists.
     /// It also removes the current node as a successor of the specified node.

 
     /// Returns the MCInstrDesc of this SUnit.
     /// Returns NULL for SDNodes without a machine opcode.
-    const MCInstrDesc *getInstrDesc(const SUnit *SU) const {
-      if (SU->isInstr()) return &SU->getInstr()->getDesc();
-      return getNodeDesc(SU->getNode());
-    }
+    const MCInstrDesc *getInstrDesc(const SUnit *SU) const;
 
     /// Pops up a GraphViz/gv window with the ScheduleDAG rendered using 'dot'.
     virtual void viewGraph(const Twine &Name, const Twine &Title);

llvm/include/llvm/CodeGen/StackProtector.h

 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/IR/Instructions.h"
 #include "llvm/IR/ValueMap.h"
 #include "llvm/Pass.h"
 

 class TargetLoweringBase;
 class TargetMachine;
 class Type;
+class PHINode;
+class TypeSize;
 
 class StackProtector : public FunctionPass {
 private:

llvm/include/llvm/CodeGen/TargetLowering.h

 #include "llvm/CodeGen/ISDOpcodes.h"
 #include "llvm/CodeGen/LowLevelType.h"
 #include "llvm/CodeGen/RuntimeLibcalls.h"
-#include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/CodeGen/TargetCallingConv.h"
 #include "llvm/CodeGen/ValueTypes.h"

   /// dag combiner.
   virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
                                        const SelectionDAG &DAG,
-                                       const MachineMemOperand &MMO) const {
-    // Don't do if we could do an indexed load on the original type, but not on
-    // the new one.
-    if (!LoadVT.isSimple() || !BitcastVT.isSimple())
-      return true;
-
-    MVT LoadMVT = LoadVT.getSimpleVT();
-
-    // Don't bother doing this if it's just going to be promoted again later, as
-    // doing so might interfere with other combines.
-    if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
-        getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
-      return false;
-
-    bool Fast = false;
-    return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), BitcastVT,
-                              MMO, &Fast) && Fast;
-  }
+                                       const MachineMemOperand &MMO) const;
 
   /// Return true if the following transform is beneficial:
   /// (store (y (conv x)), y*)) -> (store x, (x*))

   ///
   /// ValVT is the type of values that produced the boolean.
   SDValue promoteTargetBoolean(SelectionDAG &DAG, SDValue Bool,
-                               EVT ValVT) const {
-    SDLoc dl(Bool);
-    EVT BoolVT =
-        getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), ValVT);
-    ISD::NodeType ExtendCode = getExtendForContent(getBooleanContents(ValVT));
-    return DAG.getNode(ExtendCode, dl, BoolVT, Bool);
-  }
+                               EVT ValVT) const;
 
   /// Return target scheduling preference.
   Sched::Preference getSchedulingPreference() const {

   /// form TargetOpcode::G_FMAD. \p N may be an TargetOpcode::G_FADD,
   /// TargetOpcode::G_FSUB, or an TargetOpcode::G_FMUL which will be
   /// distributed into an fadd/fsub.
-  virtual bool isFMADLegal(const MachineInstr &MI, LLT Ty) const {
-    assert((MI.getOpcode() == TargetOpcode::G_FADD ||
-            MI.getOpcode() == TargetOpcode::G_FSUB ||
-            MI.getOpcode() == TargetOpcode::G_FMUL) &&
-           "unexpected node in FMAD forming combine");
-    switch (Ty.getScalarSizeInBits()) {
-    case 16:
-      return isOperationLegal(TargetOpcode::G_FMAD, MVT::f16);
-    case 32:
-      return isOperationLegal(TargetOpcode::G_FMAD, MVT::f32);
-    case 64:
-      return isOperationLegal(TargetOpcode::G_FMAD, MVT::f64);
-    default:
-      break;
-    }
-
-    return false;
-  }
+  virtual bool isFMADLegal(const MachineInstr &MI, LLT Ty) const;
 
   /// Returns true if be combined with to form an ISD::FMAD. \p N may be an
   /// ISD::FADD, ISD::FSUB, or an ISD::FMUL which will be distributed into an

   /// when the cost is cheaper.
   SDValue getCheaperNegatedExpression(SDValue Op, SelectionDAG &DAG,
                                       bool LegalOps, bool OptForSize,
-                                      unsigned Depth = 0) const {
-    NegatibleCost Cost = NegatibleCost::Expensive;
-    SDValue Neg =
-        getNegatedExpression(Op, DAG, LegalOps, OptForSize, Cost, Depth);
-    if (Neg && Cost == NegatibleCost::Cheaper)
-      return Neg;
-    // Remove the new created node to avoid the side effect to the DAG.
-    if (Neg && Neg.getNode()->use_empty())
-      DAG.RemoveDeadNode(Neg.getNode());
-    return SDValue();
-  }
+                                      unsigned Depth = 0) const;
 
   /// This is the helper function to return the newly negated expression if
   /// the cost is not expensive.

 
     // setCallee with target/module-specific attributes
     CallLoweringInfo &setLibCallee(CallingConv::ID CC, Type *ResultType,
-                                   SDValue Target, ArgListTy &&ArgsList) {
-      RetTy = ResultType;
-      Callee = Target;
-      CallConv = CC;
-      NumFixedArgs = ArgsList.size();
-      Args = std::move(ArgsList);
-
-      DAG.getTargetLoweringInfo().markLibCallAttributes(
-          &(DAG.getMachineFunction()), CC, Args);
-      return *this;
-    }
+                                   SDValue Target, ArgListTy &&ArgsList);
 
     CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
                                 SDValue Target, ArgListTy &&ArgsList) {

   /// Return a target-dependent result if the input operand is not suitable for
   /// use with a square root estimate calculation.
   virtual SDValue getSqrtResultForDenormInput(SDValue Operand,
-                                              SelectionDAG &DAG) const {
-    return DAG.getConstantFP(0.0, SDLoc(Operand), Operand.getValueType());
-  }
+                                              SelectionDAG &DAG) const;
 
   //===--------------------------------------------------------------------===//
   // Legalization utility functions

 
   /// Expands target specific indirect branch for the case of JumpTable
   /// expanasion.
-  virtual SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value, SDValue Addr,
-                                         SelectionDAG &DAG) const {
-    return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
-  }
+  virtual SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value,
+                                         SDValue Addr, SelectionDAG &DAG) const;
 
   // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
   // If we're comparing for equality to zero and isCtlzFast is true, expose the

llvm/include/llvm/CodeGen/WasmEHFuncInfo.h

 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/PointerUnion.h"
 #include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 
 namespace llvm {
 
 class BasicBlock;
 class Function;
-class MachineBasicBlock;
 
 namespace WebAssembly {
 enum Tag { CPP_EXCEPTION = 0, C_LONGJMP = 1 };

llvm/lib/CodeGen/CFGuardLongjmp.cpp

 //===----------------------------------------------------------------------===//
 
 #include "llvm/ADT/Statistic.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"

llvm/lib/CodeGen/CFIInstrInserter.cpp

 #include "llvm/ADT/DepthFirstIterator.h"
 #include "llvm/ADT/Optional.h"
 #include "llvm/ADT/SetOperations.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/Passes.h"

llvm/lib/CodeGen/CMakeLists.txt

   Core
   MC
   ProfileData
+  SelectionDAG
   Scalar
   Support
   Target

llvm/lib/CodeGen/EHContGuardCatchret.cpp

 //===----------------------------------------------------------------------===//
 
 #include "llvm/ADT/Statistic.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"

llvm/lib/CodeGen/InterleavedAccessPass.cpp

 
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/CodeGen/TargetPassConfig.h"

llvm/lib/CodeGen/MachineFunctionPrinterPass.cpp

 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/SlotIndexes.h"

llvm/lib/CodeGen/MacroFusion.cpp

 #include "llvm/CodeGen/MacroFusion.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/Statistic.h"
-#include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineScheduler.h"
 #include "llvm/CodeGen/ScheduleDAG.h"
 #include "llvm/CodeGen/ScheduleDAGMutation.h"

llvm/lib/CodeGen/PatchableFunction.cpp

 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/Passes.h"

llvm/lib/CodeGen/RegUsageInfoPropagate.cpp

 ///
 //===----------------------------------------------------------------------===//
 
-#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstr.h"

llvm/lib/CodeGen/ResetMachineFunctionPass.cpp

 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/StackProtector.h"
 #include "llvm/IR/DiagnosticInfo.h"
+#include "llvm/IR/Function.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/Support/Debug.h"
 using namespace llvm;

llvm/lib/CodeGen/ScheduleDAG.cpp

   ExitSU = SUnit();
 }
 
+const MCInstrDesc *ScheduleDAG::getInstrDesc(const SUnit *SU) const {
+  if (SU->isInstr())
+    return &SU->getInstr()->getDesc();
+  return getNodeDesc(SU->getNode());
+}
+
 const MCInstrDesc *ScheduleDAG::getNodeDesc(const SDNode *Node) const {
   if (!Node || !Node->isMachineOpcode()) return nullptr;
   return &TII->get(Node->getMachineOpcode());

   return true;
 }
 
+bool SUnit::addPredBarrier(SUnit *SU) {
+  SDep Dep(SU, SDep::Barrier);
+  unsigned TrueMemOrderLatency =
+      ((SU->getInstr()->mayStore() && this->getInstr()->mayLoad()) ? 1 : 0);
+  Dep.setLatency(TrueMemOrderLatency);
+  return addPred(Dep);
+}
+
 void SUnit::removePred(const SDep &D) {
   // Find the matching predecessor.
   SmallVectorImpl<SDep>::iterator I = llvm::find(Preds, D);

llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

   return true;
 }
 
+bool FastISel::shouldOptForSize(const MachineFunction *MF) const {
+  // TODO: Implement PGSO.
+  return MF->getFunction().hasOptSize();
+}
+
 /// Returns an AttributeList representing the attributes applied to the return
 /// value of the given call.
 static AttributeList getReturnAttrs(FastISel::CallLoweringInfo &CLI) {

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TargetLowering.h"

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

 
 #include "LegalizeTypes.h"
 #include "llvm/Analysis/TargetLibraryInfo.h"
+#include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

 
 #include "LegalizeTypes.h"
 #include "llvm/Analysis/TargetLibraryInfo.h"
+#include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/KnownBits.h"

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

 #define LLVM_LIB_CODEGEN_SELECTIONDAG_LEGALIZETYPES_H
 
 #include "llvm/ADT/DenseMap.h"
-#include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
 
 namespace llvm {
 
+class SelectionDAG;
+
 //===----------------------------------------------------------------------===//
 /// This takes an arbitrary SelectionDAG as input and hacks on it until only
 /// value types the target machine can handle are left. This involves promoting

   TargetLowering::ValueTypeActionImpl ValueTypeActions;
 
   /// Return how we should legalize values of this type.
-  TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const {
-    return TLI.getTypeAction(*DAG.getContext(), VT);
-  }
+  TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const;
 
   /// Return true if this type is legal on this target.
-  bool isTypeLegal(EVT VT) const {
-    return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal;
-  }
+  bool isTypeLegal(EVT VT) const;
 
   /// Return true if this is a simple legal type.
   bool isSimpleLegalType(EVT VT) const {
     return VT.isSimple() && TLI.isTypeLegal(VT);
   }
 
-  EVT getSetCCResultType(EVT VT) const {
-    return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
-  }
+  EVT getSetCCResultType(EVT VT) const;
 
   /// Pretend all of this node's results are legal.
   bool IgnoreNodeResults(SDNode *N) const {

   }
 
 public:
-  explicit DAGTypeLegalizer(SelectionDAG &dag)
-    : TLI(dag.getTargetLoweringInfo()), DAG(dag),
-    ValueTypeActions(TLI.getValueTypeActions()) {
-    static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
-                  "Too many value types for ValueTypeActions to hold!");
-  }
+  explicit DAGTypeLegalizer(SelectionDAG &dag);
 
   /// This is the main entry point for the type legalizer.  This does a
   /// top-down traversal of the dag, legalizing types as it goes.  Returns

   void SetPromotedInteger(SDValue Op, SDValue Result);
 
   /// Get a promoted operand and sign extend it to the final size.
-  SDValue SExtPromotedInteger(SDValue Op) {
-    EVT OldVT = Op.getValueType();
-    SDLoc dl(Op);
-    Op = GetPromotedInteger(Op);
-    return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
-                       DAG.getValueType(OldVT));
-  }
+  SDValue SExtPromotedInteger(SDValue Op);
 
   /// Get a promoted operand and zero extend it to the final size.
-  SDValue ZExtPromotedInteger(SDValue Op) {
-    EVT OldVT = Op.getValueType();
-    SDLoc dl(Op);
-    Op = GetPromotedInteger(Op);
-    return DAG.getZeroExtendInReg(Op, dl, OldVT);
-  }
+  SDValue ZExtPromotedInteger(SDValue Op);
 
   // Get a promoted operand and sign or zero extend it to the final size
   // (depending on TargetLoweringInfo::isSExtCheaperThanZExt). For a given
   // subtarget and type, the choice of sign or zero-extension will be
   // consistent.
-  SDValue SExtOrZExtPromotedInteger(SDValue Op) {
-    EVT OldVT = Op.getValueType();
-    SDLoc DL(Op);
-    Op = GetPromotedInteger(Op);
-    if (TLI.isSExtCheaperThanZExt(OldVT, Op.getValueType()))
-      return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), Op,
-                         DAG.getValueType(OldVT));
-    return DAG.getZeroExtendInReg(Op, DL, OldVT);
-  }
+  SDValue SExtOrZExtPromotedInteger(SDValue Op);
 
   // Promote the given operand V (vector or scalar) according to N's specific
   // reduction kind. N must be an integer VECREDUCE_* or VP_REDUCE_*. Returns

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp

 #include "SDNodeDbgValue.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/Support/CommandLine.h"

 static cl::opt<bool>
 EnableExpensiveChecks("enable-legalize-types-checking", cl::Hidden);
 
+DAGTypeLegalizer::DAGTypeLegalizer(SelectionDAG &dag)
+    : TLI(dag.getTargetLoweringInfo()), DAG(dag),
+      ValueTypeActions(TLI.getValueTypeActions()) {
+  static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
+                "Too many value types for ValueTypeActions to hold!");
+}
+
+TargetLowering::LegalizeTypeAction
+DAGTypeLegalizer::getTypeAction(EVT VT) const {
+  return TLI.getTypeAction(*DAG.getContext(), VT);
+}
+
+bool DAGTypeLegalizer::isTypeLegal(EVT VT) const {
+  return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal;
+}
+
+EVT DAGTypeLegalizer::getSetCCResultType(EVT VT) const {
+  return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+}
+
 /// Do extensive, expensive, basic correctness checking.
 void DAGTypeLegalizer::PerformExpensiveChecks() {
   // If a node is not processed, then none of its values should be mapped by any

   SplitInteger(Op, HalfVT, HalfVT, Lo, Hi);
 }
 
+SDValue DAGTypeLegalizer::SExtPromotedInteger(SDValue Op) {
+  EVT OldVT = Op.getValueType();
+  SDLoc dl(Op);
+  Op = GetPromotedInteger(Op);
+  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
+                     DAG.getValueType(OldVT));
+}
+
+/// Get a promoted operand and zero extend it to the final size.
+SDValue DAGTypeLegalizer::ZExtPromotedInteger(SDValue Op) {
+  EVT OldVT = Op.getValueType();
+  SDLoc dl(Op);
+  Op = GetPromotedInteger(Op);
+  return DAG.getZeroExtendInReg(Op, dl, OldVT);
+}
+
+// Get a promoted operand and sign or zero extend it to the final size
+// (depending on TargetLoweringInfo::isSExtCheaperThanZExt). For a given
+// subtarget and type, the choice of sign or zero-extension will be
+// consistent.
+SDValue DAGTypeLegalizer::SExtOrZExtPromotedInteger(SDValue Op) {
+  EVT OldVT = Op.getValueType();
+  SDLoc DL(Op);
+  Op = GetPromotedInteger(Op);
+  if (TLI.isSExtCheaperThanZExt(OldVT, Op.getValueType()))
+    return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), Op,
+                       DAG.getValueType(OldVT));
+  return DAG.getZeroExtendInReg(Op, DL, OldVT);
+}
 
 //===----------------------------------------------------------------------===//
 //  Entry Point

llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp

 //===----------------------------------------------------------------------===//
 
 #include "LegalizeTypes.h"
+#include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/IR/DataLayout.h"
 using namespace llvm;
 

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

 
 #include "LegalizeTypes.h"
 #include "llvm/Analysis/MemoryLocation.h"
+#include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TypeSize.h"

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h

   LLVMContext *Context;
 
   SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
-                      SwiftErrorValueTracking &swifterror, CodeGenOpt::Level ol)
-      : SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()), DAG(dag),
-        SL(std::make_unique<SDAGSwitchLowering>(this, funcinfo)), FuncInfo(funcinfo),
-        SwiftError(swifterror) {}
+                      SwiftErrorValueTracking &swifterror,
+                      CodeGenOpt::Level ol);
 
   void init(GCFunctionInfo *gfi, AAResults *AA,
             const TargetLibraryInfo *li);

                                         bool ForceVoidReturnTy);
 
   /// Returns the type of FrameIndex and TargetFrameIndex nodes.
-  MVT getFrameIndexTy() {
-    return DAG.getTargetLoweringInfo().getFrameIndexTy(DAG.getDataLayout());
-  }
+  MVT getFrameIndexTy();
 
 private:
   // Terminator instructions.

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

   return OutVec;
 }
 
+SelectionDAGBuilder::SelectionDAGBuilder(SelectionDAG &dag,
+                                         FunctionLoweringInfo &funcinfo,
+                                         SwiftErrorValueTracking &swifterror,
+                                         CodeGenOpt::Level ol)
+    : SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()), DAG(dag),
+      SL(std::make_unique<SDAGSwitchLowering>(this, funcinfo)),
+      FuncInfo(funcinfo), SwiftError(swifterror) {}
+
 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis *aa,
                                const TargetLibraryInfo *li) {
   AA = aa;

llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp

   }
 }
 
+MVT SelectionDAGBuilder::getFrameIndexTy() {
+  return DAG.getTargetLoweringInfo().getFrameIndexTy(DAG.getDataLayout());
+}
+
 void SelectionDAGBuilder::LowerCallSiteWithDeoptBundle(
     const CallBase *Call, SDValue Callee, const BasicBlock *EHPadBB) {
   LowerCallSiteWithDeoptBundleImpl(Call, Callee, EHPadBB,

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

   return DAG.getSetCC(DL, CCVT, Op, FPZero, ISD::SETEQ);
 }
 
+SDValue TargetLowering::getSqrtResultForDenormInput(SDValue Operand,
+                                                    SelectionDAG &DAG) const {
+  return DAG.getConstantFP(0.0, SDLoc(Operand), Operand.getValueType());
+}
+
 SDValue TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG,
                                              bool LegalOps, bool OptForSize,
                                              NegatibleCost &Cost,

   return SDValue();
 }
 
+SDValue TargetLowering::getCheaperNegatedExpression(SDValue Op,
+                                                    SelectionDAG &DAG,
+                                                    bool LegalOps,
+                                                    bool OptForSize,
+                                                    unsigned Depth) const {
+  NegatibleCost Cost = NegatibleCost::Expensive;
+  SDValue Neg =
+      getNegatedExpression(Op, DAG, LegalOps, OptForSize, Cost, Depth);
+  if (Neg && Cost == NegatibleCost::Cheaper)
+    return Neg;
+  // Remove the new created node to avoid the side effect to the DAG.
+  if (Neg && Neg.getNode()->use_empty())
+    DAG.RemoveDeadNode(Neg.getNode());
+  return SDValue();
+}
+
+TargetLowering::CallLoweringInfo &
+TargetLowering::CallLoweringInfo::setLibCallee(CallingConv::ID CC,
+                                               Type *ResultType, SDValue Target,
+                                               ArgListTy &&ArgsList) {
+  RetTy = ResultType;
+  Callee = Target;
+  CallConv = CC;
+  NumFixedArgs = ArgsList.size();
+  Args = std::move(ArgsList);
+
+  DAG.getTargetLoweringInfo().markLibCallAttributes(&(DAG.getMachineFunction()),
+                                                    CC, Args);
+  return *this;
+}
+
 //===----------------------------------------------------------------------===//
 // Legalization Utilities
 //===----------------------------------------------------------------------===//

   return CallResult.first;
 }
 
+SDValue TargetLowering::expandIndirectJTBranch(const SDLoc &dl, SDValue Value,
+                                               SDValue Addr,
+                                               SelectionDAG &DAG) const {
+  return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
+}
+
 SDValue TargetLowering::lowerCmpEqZeroToCtlzSrl(SDValue Op,
                                                 SelectionDAG &DAG) const {
   assert((Op->getOpcode() == ISD::SETCC) && "Input has to be a SETCC node.");

llvm/lib/CodeGen/SwitchLoweringUtils.cpp

 
 #include "llvm/CodeGen/SwitchLoweringUtils.h"
 #include "llvm/CodeGen/FunctionLoweringInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/Target/TargetMachine.h"

llvm/lib/CodeGen/TargetLoweringBase.cpp

 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RuntimeLibcalls.h"
+#include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/StackMaps.h"
 #include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/CodeGen/TargetOpcodes.h"

   }
 }
 
+bool TargetLoweringBase::isLoadBitCastBeneficial(
+    EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG,
+    const MachineMemOperand &MMO) const {
+  // Don't do if we could do an indexed load on the original type, but not on
+  // the new one.
+  if (!LoadVT.isSimple() || !BitcastVT.isSimple())
+    return true;
+
+  MVT LoadMVT = LoadVT.getSimpleVT();
+
+  // Don't bother doing this if it's just going to be promoted again later, as
+  // doing so might interfere with other combines.
+  if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
+      getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
+    return false;
+
+  bool Fast = false;
+  return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), BitcastVT,
+                            MMO, &Fast) &&
+         Fast;
+}
+
 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
                                            EVT VT) const {
   assert(!VT.isVector() && "No default SetCC type for vectors!");

   return MVT::i32; // return the default value
 }
 
+SDValue TargetLoweringBase::promoteTargetBoolean(SelectionDAG &DAG,
+                                                 SDValue Bool,
+                                                 EVT ValVT) const {
+  SDLoc dl(Bool);
+  EVT BoolVT =
+      getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), ValVT);
+  ISD::NodeType ExtendCode = getExtendForContent(getBooleanContents(ValVT));
+  return DAG.getNode(ExtendCode, dl, BoolVT, Bool);
+}
+
 /// getVectorTypeBreakdown - Vector types are broken down into some number of
 /// legal first class types.  For example, MVT::v8f32 maps to 2 MVT::v4f32
 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.

   return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
 }
 
+bool TargetLoweringBase::isFMADLegal(const MachineInstr &MI, LLT Ty) const {
+  assert((MI.getOpcode() == TargetOpcode::G_FADD ||
+          MI.getOpcode() == TargetOpcode::G_FSUB ||
+          MI.getOpcode() == TargetOpcode::G_FMUL) &&
+         "unexpected node in FMAD forming combine");
+  switch (Ty.getScalarSizeInBits()) {
+  case 16:
+    return isOperationLegal(TargetOpcode::G_FMAD, MVT::f16);
+  case 32:
+    return isOperationLegal(TargetOpcode::G_FMAD, MVT::f32);
+  case 64:
+    return isOperationLegal(TargetOpcode::G_FMAD, MVT::f64);
+  default:
+    break;
+  }
+
+  return false;
+}
+
 void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
   MF.getRegInfo().freezeReservedRegs(MF);
 }

llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h

 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H
 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H
 
-#include "llvm/ADT/ArrayRef.h"
 #include "llvm/CodeGen/Register.h"
 #include <utility>
 
 namespace llvm {
 
 class MachineRegisterInfo;
+template <typename T> class ArrayRef;
 
 namespace AMDGPU {
 

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h

 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
 
 #include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/TargetLowering.h"
 
 namespace llvm {

                                Register Reg, EVT VT,
                                const SDLoc &SL,
                                bool RawReg = false) const;
-  SDValue CreateLiveInRegister(SelectionDAG &DAG,
-                               const TargetRegisterClass *RC,
-                               Register Reg, EVT VT) const {
-    return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
-  }
-
+  SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
+                               Register Reg, EVT VT) const;
   // Returns the raw live in register rather than a copy from it.
   SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
-                                  const TargetRegisterClass *RC,
-                                  Register Reg, EVT VT) const {
-    return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
-  }
+                                  const TargetRegisterClass *RC, Register Reg,
+                                  EVT VT) const;
 
   /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
   /// slot rather than passed in a register.

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

   return DAG.getCopyFromReg(DAG.getEntryNode(), SL, VReg, VT);
 }
 
+SDValue
+AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
+                                           const TargetRegisterClass *RC,
+                                           Register Reg, EVT VT) const {
+  return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
+}
+
+// Returns the raw live in register rather than a copy from it.
+SDValue
+AMDGPUTargetLowering::CreateLiveInRegisterRaw(SelectionDAG &DAG,
+                                              const TargetRegisterClass *RC,
+                                              Register Reg, EVT VT) const {
+  return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()),
+                              true);
+}
+
 // This may be called multiple times, and nothing prevents creating multiple
 // objects at the same offset. See if we already defined this object.
 static int getOrCreateFixedStackObject(MachineFrameInfo &MFI, unsigned Size,

llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp

 ///
 //===----------------------------------------------------------------------===//
 
-#include "AMDGPU.h"
 #include "AMDGPUPerfHintAnalysis.h"
+#include "AMDGPU.h"
 #include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/Statistic.h"

 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Printable.h"
 #include "llvm/Target/TargetMachine.h"
 
 using namespace llvm;

llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/SmallVector.h"

llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

 #include "MVETailPredUtils.h"
 #include "Thumb2InstrInfo.h"
 #include "llvm/ADT/SetOperations.h"
+#include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/CodeGen/LivePhysRegs.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"

llvm/lib/Target/ARM/MVELaneInterleavingPass.cpp

 #include "ARM.h"
 #include "ARMBaseInstrInfo.h"
 #include "ARMSubtarget.h"
+#include "llvm/ADT/SetVector.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/CodeGen/TargetPassConfig.h"

llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp

 #include "HexagonInstrInfo.h"
 #include "HexagonRegisterInfo.h"
 #include "HexagonSubtarget.h"
+#include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"

llvm/lib/Target/Hexagon/HexagonISelLowering.h

 #include "llvm/CodeGen/ISDOpcodes.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/IR/InlineAsm.h"

     return Op.getOpcode() == ISD::UNDEF;
   }
   SDValue getInstr(unsigned MachineOpc, const SDLoc &dl, MVT Ty,
-                   ArrayRef<SDValue> Ops, SelectionDAG &DAG) const {
-    SDNode *N = DAG.getMachineNode(MachineOpc, dl, Ty, Ops);
-    return SDValue(N, 0);
-  }
+                   ArrayRef<SDValue> Ops, SelectionDAG &DAG) const;
   SDValue getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG) const;
 
   using VectorPair = std::pair<SDValue, SDValue>;

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

   return getInstr(Hexagon::S2_vtrunehb, dl, MVT::i32, {Vec64}, DAG);
 }
 
+SDValue HexagonTargetLowering::getInstr(unsigned MachineOpc, const SDLoc &dl,
+                                        MVT Ty, ArrayRef<SDValue> Ops,
+                                        SelectionDAG &DAG) const {
+  SDNode *N = DAG.getMachineNode(MachineOpc, dl, Ty, Ops);
+  return SDValue(N, 0);
+}
+
 SDValue
 HexagonTargetLowering::getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG)
       const {

llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

 #include "HexagonRegisterInfo.h"
 #include "HexagonSubtarget.h"
 #include "llvm/Analysis/MemoryLocation.h"
+#include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/IR/IntrinsicsHexagon.h"
 #include "llvm/Support/CommandLine.h"
 

llvm/lib/Target/NVPTX/NVPTXUtilities.h

 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXUTILITIES_H
 #define LLVM_LIB_TARGET_NVPTX_NVPTXUTILITIES_H
 
-#include "llvm/IR/Function.h"
 #include "llvm/IR/GlobalVariable.h"
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/Value.h"

llvm/lib/Target/VE/VEISelLowering.h

 #define LLVM_LIB_TARGET_VE_VEISELLOWERING_H
 
 #include "VE.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/TargetLowering.h"
 
 namespace llvm {

llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp

 //===----------------------------------------------------------------------===//
 
 #include "WebAssemblyTargetMachine.h"
+#include "llvm/CodeGen/SelectionDAG.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-selectiondag-info"

llvm/lib/Target/X86/X86ISelLowering.cpp

 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/CodeGen/WinEHFuncInfo.h"
 #include "llvm/IR/CallingConv.h"

llvm/lib/Target/X86/X86InstrInfo.cpp

 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/StackMaps.h"
 #include "llvm/IR/DebugInfoMetadata.h"
 #include "llvm/IR/DerivedTypes.h"