[AVR][MC] Emit some aliases for GPRs and IO registers

[benshi001]

Summary

Emit the following aliases (if available):

.set __tmp_reg__, [0|16]
.set __zero_reg__, [1|17]
.set __SREG__, 63
.set __SP_H__, 62
.set __SP_L__, 61
.set __EIND__, 60
.set __RAMPZ__, 59

[benshi001]

llvm/lib/Target/AVR/AVRDevices.td

178

This is just re-format, no functional change.

[benshi001]

this patch fixes https://github.com/llvm/llvm-project/issues/51557

[aykevl]

I think there is one issue in the test. Other than that, this looks good to me.

llvm/test/MC/AVR/registers.s

7–10 ↗

(On Diff #414546)

I don't think this should be needed? The goal of this patch is to avoid the need for these aliases, after all.

[benshi001]

In D119807#3401148, @aykevl wrote:

I think there is one issue in the test. Other than that, this looks good to me.

I have deleted the MC test, since it is uncessary as you pointed.

My patch is only about emiting aliases when doing CodeGen, so one .ll test is enough.

[aykevl]

Hmm, ok. An assembly test might have been useful to show that it actually works but the patch looks fine to me so I'll accept it.

llvm/lib/Target/AVR/AVRAsmPrinter.cpp

 //===-- AVRAsmPrinter.cpp - AVR LLVM assembly writer ----------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains a printer that converts from our internal representation
 // of machine-dependent LLVM code to GAS-format AVR assembly language.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AVR.h"
 #include "AVRMCInstLower.h"
 #include "AVRSubtarget.h"
+#include "AVRTargetMachine.h"
 #include "MCTargetDesc/AVRInstPrinter.h"
 #include "MCTargetDesc/AVRMCExpr.h"
 #include "TargetInfo/AVRTargetInfo.h"
 
 #include "llvm/CodeGen/AsmPrinter.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/Mangler.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/TargetRegistry.h"
public:
   void emitInstruction(const MachineInstr *MI) override;
 
   const MCExpr *lowerConstant(const Constant *CV) override;
 
   void emitXXStructor(const DataLayout &DL, const Constant *CV) override;
 
   bool doFinalization(Module &M) override;
 
+  void emitStartOfAsmFile(Module &M) override;
+
 private:
   const MCRegisterInfo &MRI;
   bool EmittedStructorSymbolAttrs = false;
 };
 
 void AVRAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
                                  raw_ostream &O) {
   const MachineOperand &MO = MI->getOperand(OpNo);
bool AVRAsmPrinter::doFinalization(Module &M) {
   OutStreamer->emitRawComment(
       " Declaring this symbol tells the CRT that it should");
   OutStreamer->emitRawComment("clear the zeroed data section on startup");
   OutStreamer->emitSymbolAttribute(DoClearBss, MCSA_Global);
 
   return AsmPrinter::doFinalization(M);
 }
 
+void AVRAsmPrinter::emitStartOfAsmFile(Module &M) {
+  const AVRTargetMachine &TM = (const AVRTargetMachine &)MMI->getTarget();
+  const AVRSubtarget *SubTM = (const AVRSubtarget *)TM.getSubtargetImpl();
+  if (!SubTM)
+    return;
+
+  // Emit __tmp_reg__.
+  OutStreamer->emitAssignment(
+      MMI->getContext().getOrCreateSymbol(StringRef("__tmp_reg__")),
+      MCConstantExpr::create(SubTM->getRegTmpIndex(), MMI->getContext()));
+  // Emit __zero_reg__.
+  OutStreamer->emitAssignment(
+      MMI->getContext().getOrCreateSymbol(StringRef("__zero_reg__")),
+      MCConstantExpr::create(SubTM->getRegZeroIndex(), MMI->getContext()));
+  // Emit __SREG__.
+  OutStreamer->emitAssignment(
+      MMI->getContext().getOrCreateSymbol(StringRef("__SREG__")),
+      MCConstantExpr::create(SubTM->getIORegSREG(), MMI->getContext()));
+  // Emit __SP_H__ if available.
+  if (!SubTM->hasSmallStack())
+    OutStreamer->emitAssignment(
+        MMI->getContext().getOrCreateSymbol(StringRef("__SP_H__")),
+        MCConstantExpr::create(SubTM->getIORegSPH(), MMI->getContext()));
+  // Emit __SP_L__.
+  OutStreamer->emitAssignment(
+      MMI->getContext().getOrCreateSymbol(StringRef("__SP_L__")),
+      MCConstantExpr::create(SubTM->getIORegSPL(), MMI->getContext()));
+  // Emit __EIND__ if available.
+  if (SubTM->hasEIJMPCALL())
+    OutStreamer->emitAssignment(
+        MMI->getContext().getOrCreateSymbol(StringRef("__EIND__")),
+        MCConstantExpr::create(SubTM->getIORegEIND(), MMI->getContext()));
+  // Emit __RAMPZ__ if available.
+  if (SubTM->hasELPM())
+    OutStreamer->emitAssignment(
+        MMI->getContext().getOrCreateSymbol(StringRef("__RAMPZ__")),
+        MCConstantExpr::create(SubTM->getIORegRAMPZ(), MMI->getContext()));
+}
+
 } // end of namespace llvm
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRAsmPrinter() {
   llvm::RegisterAsmPrinter<llvm::AVRAsmPrinter> X(llvm::getTheAVRTarget());
 }

llvm/lib/Target/AVR/AVRDevices.td

 def FamilyAVR3 : Family<"avr3", [FamilyAVR2, FeatureJMPCALL]>;
 
 def FamilyAVR31 : Family<"avr31", [FamilyAVR3, FeatureELPM]>;
 
 def FamilyAVR35
     : Family<"avr35",
              [FamilyAVR3, FeatureMOVW, FeatureLPMX, FeatureSPM, FeatureBREAK]>;
 
-def FamilyAVR4 : Family<"avr4", [
-  FamilyAVR2, FeatureMultiplication, FeatureMOVW, FeatureLPMX, FeatureSPM,
-  FeatureBREAK
-]>;
-
-def FamilyAVR5 : Family<"avr5", [
-  FamilyAVR3, FeatureMultiplication, FeatureMOVW, FeatureLPMX, FeatureSPM,
-  FeatureBREAK
-]>;
+def FamilyAVR4
+    : Family<"avr4",
+             [FamilyAVR2, FeatureMultiplication, FeatureMOVW, FeatureLPMX,
+              FeatureSPM, FeatureBREAK]>;
+
+def FamilyAVR5
+    : Family<"avr5",
+             [FamilyAVR3, FeatureMultiplication, FeatureMOVW, FeatureLPMX,
+              FeatureSPM, FeatureBREAK]>;
 
 def FamilyAVR51 : Family<"avr51", [FamilyAVR5, FeatureELPM, FeatureELPMX]>;
 
 def FamilyAVR6 : Family<"avr6", [FamilyAVR51]>;
 
 def FamilyTiny
     : Family<"avrtiny",
-             [FamilyAVR0, FeatureBREAK, FeatureSRAM, FeatureTinyEncoding]>;
+             [FamilyAVR0, FeatureBREAK, FeatureSRAM, FeatureTinyEncoding,
+              FeatureSmallStack]>;
 
-def FamilyXMEGA : Family<"xmega", [
-  FamilyAVR0, FeatureLPM, FeatureIJMPCALL, FeatureADDSUBIW, FeatureSRAM,
-  FeatureJMPCALL, FeatureMultiplication, FeatureMOVW, FeatureLPMX, FeatureSPM,
-  FeatureBREAK, FeatureEIJMPCALL, FeatureSPMX, FeatureDES, FeatureELPM,
-  FeatureELPMX
-]>;
+def FamilyXMEGA
+    : Family<"xmega",
+             [FamilyAVR0, FeatureLPM, FeatureIJMPCALL, FeatureADDSUBIW,
+              FeatureSRAM, FeatureJMPCALL, FeatureMultiplication, FeatureMOVW,
+              FeatureLPMX, FeatureSPM, FeatureBREAK, FeatureEIJMPCALL, FeatureSPMX,
+              FeatureDES, FeatureELPM, FeatureELPMX]>;
 
 def FamilyXMEGAU : Family<"xmegau", [FamilyXMEGA, FeatureRMW]>;
 
 def FeatureSetSpecial
     : FeatureSet<"special",
                  "Enable use of the entire instruction "
                  "set - used for debugging",
                  [

 def : Device<"avrxmega3", FamilyXMEGA, ELFArchXMEGA3>;
 def : Device<"avrxmega4", FamilyXMEGA, ELFArchXMEGA4>;
 def : Device<"avrxmega5", FamilyXMEGA, ELFArchXMEGA5>;
 def : Device<"avrxmega6", FamilyXMEGA, ELFArchXMEGA6>;
 def : Device<"avrxmega7", FamilyXMEGA, ELFArchXMEGA7>;
 def : Device<"avrtiny", FamilyTiny, ELFArchTiny>;
 
 // Specific MCUs
-def : Device<"at90s1200", FamilyAVR0, ELFArchAVR1>;
-def : Device<"attiny11", FamilyAVR1, ELFArchAVR1>;
-def : Device<"attiny12", FamilyAVR1, ELFArchAVR1>;
-def : Device<"attiny15", FamilyAVR1, ELFArchAVR1>;
-def : Device<"attiny28", FamilyAVR1, ELFArchAVR1>;
-def : Device<"at90s2313", FamilyAVR2, ELFArchAVR2>;
-def : Device<"at90s2323", FamilyAVR2, ELFArchAVR2>;
-def : Device<"at90s2333", FamilyAVR2, ELFArchAVR2>;
-def : Device<"at90s2343", FamilyAVR2, ELFArchAVR2>;
-def : Device<"attiny22", FamilyAVR2, ELFArchAVR2>;
-def : Device<"attiny26", FamilyAVR2, ELFArchAVR2, [FeatureLPMX]>;
+def : Device<"at90s1200", FamilyAVR0, ELFArchAVR1, [FeatureSmallStack]>;
+def : Device<"attiny11", FamilyAVR1, ELFArchAVR1, [FeatureSmallStack]>;
+def : Device<"attiny12", FamilyAVR1, ELFArchAVR1, [FeatureSmallStack]>;
+def : Device<"attiny15", FamilyAVR1, ELFArchAVR1, [FeatureSmallStack]>;
+def : Device<"attiny28", FamilyAVR1, ELFArchAVR1, [FeatureSmallStack]>;
+def : Device<"at90s2313", FamilyAVR2, ELFArchAVR2, [FeatureSmallStack]>;
+def : Device<"at90s2323", FamilyAVR2, ELFArchAVR2, [FeatureSmallStack]>;
+def : Device<"at90s2333", FamilyAVR2, ELFArchAVR2, [FeatureSmallStack]>;
+def : Device<"at90s2343", FamilyAVR2, ELFArchAVR2, [FeatureSmallStack]>;
+def : Device<"attiny22", FamilyAVR2, ELFArchAVR2, [FeatureSmallStack]>;
+def : Device<"attiny26", FamilyAVR2, ELFArchAVR2,
+             [FeatureSmallStack, FeatureLPMX]>;
 def : Device<"at86rf401", FamilyAVR2, ELFArchAVR25, [FeatureMOVW, FeatureLPMX]>;
-def : Device<"at90s4414", FamilyAVR2, ELFArchAVR2>;
-def : Device<"at90s4433", FamilyAVR2, ELFArchAVR2>;
-def : Device<"at90s4434", FamilyAVR2, ELFArchAVR2>;
+def : Device<"at90s4414", FamilyAVR2, ELFArchAVR2, [FeatureSmallStack]>;
+def : Device<"at90s4433", FamilyAVR2, ELFArchAVR2, [FeatureSmallStack]>;
+def : Device<"at90s4434", FamilyAVR2, ELFArchAVR2, [FeatureSmallStack]>;
 def : Device<"at90s8515", FamilyAVR2, ELFArchAVR2>;
 def : Device<"at90c8534", FamilyAVR2, ELFArchAVR2>;
 def : Device<"at90s8535", FamilyAVR2, ELFArchAVR2>;
 def : Device<"ata5272", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny13", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny13a", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny2313", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny2313a", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny24", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny24a", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny13", FamilyAVR25, ELFArchAVR25, [FeatureSmallStack]>;
+def : Device<"attiny13a", FamilyAVR25, ELFArchAVR25, [FeatureSmallStack]>;
+def : Device<"attiny2313", FamilyAVR25, ELFArchAVR25, [FeatureSmallStack]>;
+def : Device<"attiny2313a", FamilyAVR25, ELFArchAVR25, [FeatureSmallStack]>;
+def : Device<"attiny24", FamilyAVR25, ELFArchAVR25, [FeatureSmallStack]>;
+def : Device<"attiny24a", FamilyAVR25, ELFArchAVR25, [FeatureSmallStack]>;
 def : Device<"attiny4313", FamilyAVR25, ELFArchAVR25>;
 def : Device<"attiny44", FamilyAVR25, ELFArchAVR25>;
 def : Device<"attiny44a", FamilyAVR25, ELFArchAVR25>;
 def : Device<"attiny84", FamilyAVR25, ELFArchAVR25>;
 def : Device<"attiny84a", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny25", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny25", FamilyAVR25, ELFArchAVR25, [FeatureSmallStack]>;
 def : Device<"attiny45", FamilyAVR25, ELFArchAVR25>;
 def : Device<"attiny85", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny261", FamilyAVR25, ELFArchAVR25>;
-def : Device<"attiny261a", FamilyAVR25, ELFArchAVR25>;
+def : Device<"attiny261", FamilyAVR25, ELFArchAVR25, [FeatureSmallStack]>;
+def : Device<"attiny261a", FamilyAVR25, ELFArchAVR25, [FeatureSmallStack]>;
 def : Device<"attiny441", FamilyAVR25, ELFArchAVR25>;
 def : Device<"attiny461", FamilyAVR25, ELFArchAVR25>;
 def : Device<"attiny461a", FamilyAVR25, ELFArchAVR25>;
 def : Device<"attiny841", FamilyAVR25, ELFArchAVR25>;
 def : Device<"attiny861", FamilyAVR25, ELFArchAVR25>;
 def : Device<"attiny861a", FamilyAVR25, ELFArchAVR25>;
 def : Device<"attiny87", FamilyAVR25, ELFArchAVR25>;
 def : Device<"attiny43u", FamilyAVR25, ELFArchAVR25>;

llvm/lib/Target/AVR/AVRSubtarget.h

public:
   /// Gets the ELF architecture for the e_flags field
   /// of an ELF object file.
   unsigned getELFArch() const {
     assert(ELFArch != 0 &&
            "every device must have an associate ELF architecture");
     return ELFArch;
   }
 
-  /// Get I/O register address.
-  int getIORegRAMPZ(void) const { return 0x3b; }
+  /// Get I/O register addresses.
+  int getIORegRAMPZ(void) const { return hasELPM() ? 0x3b : -1; }
+  int getIORegEIND(void) const { return hasEIJMPCALL() ? 0x3c : -1; }
+  int getIORegSPL(void) const { return 0x3d; }
+  int getIORegSPH(void) const { return hasSmallStack() ? -1 : 0x3e; }
   int getIORegSREG(void) const { return 0x3f; }
 
+  /// Get GPR aliases.
+  int getRegTmpIndex(void) const { return hasTinyEncoding() ? 16 : 0; }
+  int getRegZeroIndex(void) const { return hasTinyEncoding() ? 17 : 1; }
+
 private:
   /// The ELF e_flags architecture.
   unsigned ELFArch;
 
   // Subtarget feature settings
   // See AVR.td for details.
   bool m_hasSRAM;
   bool m_hasJMPCALL;

llvm/test/CodeGen/AVR/global-aliases.ll

+; RUN: llc < %s -mtriple=avr -mcpu=atxmega384c3 | FileCheck %s --check-prefixes=MEGA
+; RUN: llc < %s -mtriple=avr -mcpu=attiny40 | FileCheck %s --check-prefixes=TINY
+
+; MEGA: .set __tmp_reg__, 0
+; MEGA: .set __zero_reg__, 1
+; MEGA: .set __SREG__, 63
+; MEGA: .set __SP_H__, 62
+; MEGA: .set __SP_L__, 61
+; MEGA: .set __EIND__, 60
+; MEGA: .set __RAMPZ__, 59
+
+; TINY:     .set __tmp_reg__, 16
+; TINY:     .set __zero_reg__, 17
+; TINY:     .set __SREG__, 63
+; TINY-NOT: .set __SP_H__, 62
+; TINY:     .set __SP_L__, 61
+; TINY-NOT: .set __EIND__, 60
+; TINY-NOT: .set __RAMPZ__, 59