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[InstCombine] SimplifyDemandedBits - mul(x,x) is odd iff x is odd
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Authored by spatel on Feb 5 2022, 7:46 AM.

Details

Summary

This was mentioned in D118539.

With proof adapted from a comment there:
https://alive2.llvm.org/ce/z/AXPr3k

Diff Detail

Event Timeline

spatel created this revision.Feb 5 2022, 7:46 AM
spatel requested review of this revision.Feb 5 2022, 7:46 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 5 2022, 7:46 AM
RKSimon accepted this revision.Feb 5 2022, 8:57 AM

LGTM - cheers

This revision is now accepted and ready to land.Feb 5 2022, 8:57 AM
lebedev.ri added inline comments.Feb 5 2022, 9:06 AM
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
550–556

Can we generalize this to something along the lines of:
if we only demand 2 low bits, then replace with and %x, 0b00001 ?

lebedev.ri added inline comments.Feb 5 2022, 9:11 AM
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
550–556
spatel added inline comments.Feb 7 2022, 5:52 AM
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
550–556

Yes, that does seem better. I'll go ahead and commit this patch as a minimum improvement, then update with more tests and fix up the code to reduce risk.