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Differential D118860

[AMDGPU] HWRegs TMA and TBA also supported on gfx9
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Authored by rampitec on Feb 2 2022, 4:17 PM.

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dp
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rGd3b87e4a1c5a: [AMDGPU] HWRegs TMA and TBA also supported on gfx9

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rampitec created this revision.Feb 2 2022, 4:17 PM
Herald added subscribers: foad, kerbowa, hiraditya and 7 others. · View Herald TranscriptFeb 2 2022, 4:17 PM
rampitec requested review of this revision.Feb 2 2022, 4:17 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 2 2022, 4:17 PM
Herald added a subscriber: wdng. · View Herald Transcript
Harbormaster completed remote builds in B147287: Diff 405491.Feb 2 2022, 7:24 PM
dp accepted this revision.Feb 3 2022, 1:27 AM

LGTM. Actually, this is a duplicate of https://reviews.llvm.org/D118123. I'm sorry that I did not add you to that review.

This revision is now accepted and ready to land.Feb 3 2022, 1:27 AM
foad added a comment.Feb 3 2022, 1:31 AM

Do we also need the update to docs/AMDGPU/gfx9_hwreg.rst from D118123?

dp added a comment.Feb 3 2022, 2:10 AM
In D118860#3292894, @foad wrote:

Do we also need the update to docs/AMDGPU/gfx9_hwreg.rst from D118123?

It is optional. Usually I update documentation myself.

rampitec added a comment.Feb 3 2022, 9:26 AM
In D118860#3292885, @dp wrote:

LGTM. Actually, this is a duplicate of https://reviews.llvm.org/D118123. I'm sorry that I did not add you to that review.

I actually like moving ID_SYMBOLIC_FIRST_GFX10_ more than special casing register names in the validation.

rampitec added a comment.Feb 3 2022, 9:27 AM
In D118860#3292969, @dp wrote:
In D118860#3292894, @foad wrote:

Do we also need the update to docs/AMDGPU/gfx9_hwreg.rst from D118123?

It is optional. Usually I update documentation myself.

Thanks, I will defer that to you.

This revision was landed with ongoing or failed builds.Feb 3 2022, 9:36 AM
Closed by commit rGd3b87e4a1c5a: [AMDGPU] HWRegs TMA and TBA also supported on gfx9 (authored by rampitec). · Explain Why
This revision was automatically updated to reflect the committed changes.
rampitec added a commit: rGd3b87e4a1c5a: [AMDGPU] HWRegs TMA and TBA also supported on gfx9.
dp mentioned this in D118123: [AMDGPU][MC][GFX9] Enabled TBA/TMA access via setreg/getreg.Feb 3 2022, 10:30 AM
dp mentioned this in rG95a52b376ab2: [AMDGPU][GFX9][DOC][NFC] Corrected description of registers available via….Feb 4 2022, 6:51 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
2 lines
test/
MC/
AMDGPU/
8 lines
28 lines
Disassembler/
AMDGPU/
6 lines

Diff 405491

llvm/lib/Target/AMDGPU/SIDefines.h

Show First 20 Lines • Show All 366 Lines • ▼ Show 20 Linesenum Id { // HwRegCode, (6) [5:0]
ID_TRAPSTS = 3, ID_TRAPSTS = 3,
ID_HW_ID = 4, ID_HW_ID = 4,
ID_GPR_ALLOC = 5, ID_GPR_ALLOC = 5,
ID_LDS_ALLOC = 6, ID_LDS_ALLOC = 6,
ID_IB_STS = 7, ID_IB_STS = 7,
ID_MEM_BASES = 15, ID_MEM_BASES = 15,
ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES, ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES,
ID_TBA_LO = 16, ID_TBA_LO = 16,
ID_SYMBOLIC_FIRST_GFX10_ = ID_TBA_LO,
ID_TBA_HI = 17, ID_TBA_HI = 17,
ID_TMA_LO = 18, ID_TMA_LO = 18,
ID_TMA_HI = 19, ID_TMA_HI = 19,
ID_FLAT_SCR_LO = 20, ID_FLAT_SCR_LO = 20,
ID_SYMBOLIC_FIRST_GFX10_ = ID_FLAT_SCR_LO,
ID_FLAT_SCR_HI = 21, ID_FLAT_SCR_HI = 21,
ID_XNACK_MASK = 22, ID_XNACK_MASK = 22,
ID_HW_ID1 = 23, ID_HW_ID1 = 23,
ID_HW_ID2 = 24, ID_HW_ID2 = 24,
ID_POPS_PACKER = 25, ID_POPS_PACKER = 25,
ID_SHADER_CYCLES = 29, ID_SHADER_CYCLES = 29,
ID_SYMBOLIC_FIRST_GFX1030_ = ID_SHADER_CYCLES, ID_SYMBOLIC_FIRST_GFX1030_ = ID_SHADER_CYCLES,
ID_SYMBOLIC_LAST_ = 30, ID_SYMBOLIC_LAST_ = 30,
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llvm/test/MC/AMDGPU/sopk-err.s

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9]
// SICIVI-ERR: error: specified hardware register is not supported on this GPU // SICIVI-ERR: error: specified hardware register is not supported on this GPU
// GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8] // GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) s_getreg_b32 s2, hwreg(HW_REG_TBA_LO)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9]
// SICIVI-ERR: error: specified hardware register is not supported on this GPU // SICIVI-ERR: error: specified hardware register is not supported on this GPU
// GFX9-ERR: error: specified hardware register is not supported on this GPU // GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) s_getreg_b32 s2, hwreg(HW_REG_TBA_HI)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9]
// SICIVI-ERR: error: specified hardware register is not supported on this GPU // SICIVI-ERR: error: specified hardware register is not supported on this GPU
// GFX9-ERR: error: specified hardware register is not supported on this GPU // GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) s_getreg_b32 s2, hwreg(HW_REG_TMA_LO)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9]
// SICIVI-ERR: error: specified hardware register is not supported on this GPU // SICIVI-ERR: error: specified hardware register is not supported on this GPU
// GFX9-ERR: error: specified hardware register is not supported on this GPU // GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) s_getreg_b32 s2, hwreg(HW_REG_TMA_HI)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9]
// SICIVI-ERR: error: specified hardware register is not supported on this GPU // SICIVI-ERR: error: specified hardware register is not supported on this GPU
// GFX9-ERR: error: specified hardware register is not supported on this GPU // GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9]
// SICIVI-ERR: error: specified hardware register is not supported on this GPU // SICIVI-ERR: error: specified hardware register is not supported on this GPU
// GFX9-ERR: error: specified hardware register is not supported on this GPU // GFX9-ERR: error: specified hardware register is not supported on this GPU
s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI) s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI) ; encoding: [0x15,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI) ; encoding: [0x15,0xf8,0x02,0xb9]
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llvm/test/MC/AMDGPU/sopk.s

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// HW_REG_SH_MEM_BASES valid starting from GFX9 // HW_REG_SH_MEM_BASES valid starting from GFX9
s_getreg_b32 s2, hwreg(15) s_getreg_b32 s2, hwreg(15)
// SICI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x02,0xb9]
// VI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x82,0xb8] // VI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x82,0xb8]
// GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8] // GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9]
// GFX10+ registers
s_getreg_b32 s2, hwreg(16) s_getreg_b32 s2, hwreg(16)
// SICI: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x82,0xb8] // VI: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x82,0xb8]
// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9]
s_getreg_b32 s2, hwreg(17) s_getreg_b32 s2, hwreg(17)
// SICI: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x82,0xb8] // VI: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x82,0xb8]
// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9]
s_getreg_b32 s2, hwreg(18) s_getreg_b32 s2, hwreg(18)
// SICI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x82,0xb8] // VI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x82,0xb8]
// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9]
s_getreg_b32 s2, hwreg(19) s_getreg_b32 s2, hwreg(19)
// SICI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x82,0xb8] // VI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x82,0xb8]
// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9]
// GFX10+ registers
s_getreg_b32 s2, hwreg(20) s_getreg_b32 s2, hwreg(20)
// SICI: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x82,0xb8] // VI9: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9]
s_getreg_b32 s2, hwreg(21) s_getreg_b32 s2, hwreg(21)
// SICI: s_getreg_b32 s2, hwreg(21) ; encoding: [0x15,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(21) ; encoding: [0x15,0xf8,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(21) ; encoding: [0x15,0xf8,0x82,0xb8] // VI9: s_getreg_b32 s2, hwreg(21) ; encoding: [0x15,0xf8,0x82,0xb8]
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// HW_REG_SH_MEM_BASES valid starting from GFX9 // HW_REG_SH_MEM_BASES valid starting from GFX9
s_setreg_b32 hwreg(15), s2 s_setreg_b32 hwreg(15), s2
// SICI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x82,0xb9]
// VI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x02,0xb9] // VI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x02,0xb9]
// GFX9: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x02,0xb9] // GFX9: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x82,0xb9] // GFX10: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x82,0xb9]
// GFX10+ registers
s_setreg_b32 hwreg(16), s2 s_setreg_b32 hwreg(16), s2
// SICI: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x02,0xb9] // VI: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x02,0xb9]
// GFX9: s_setreg_b32 hwreg(HW_REG_TBA_LO), s2 ; encoding: [0x10,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_TBA_LO), s2 ; encoding: [0x10,0xf8,0x82,0xb9] // GFX10: s_setreg_b32 hwreg(HW_REG_TBA_LO), s2 ; encoding: [0x10,0xf8,0x82,0xb9]
s_setreg_b32 hwreg(17), s2 s_setreg_b32 hwreg(17), s2
// SICI: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x02,0xb9] // VI: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x02,0xb9]
// GFX9: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x82,0xb9] // GFX10: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x82,0xb9]
s_setreg_b32 hwreg(18), s2 s_setreg_b32 hwreg(18), s2
// SICI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x02,0xb9] // VI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x02,0xb9]
// GFX9: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x82,0xb9] // GFX10: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x82,0xb9]
s_setreg_b32 hwreg(19), s2 s_setreg_b32 hwreg(19), s2
// SICI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x02,0xb9] // VI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x02,0xb9]
// GFX9: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x82,0xb9] // GFX10: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x82,0xb9]
// GFX10+ registers
s_setreg_b32 hwreg(20), s2 s_setreg_b32 hwreg(20), s2
// SICI: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x02,0xb9] // VI9: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; encoding: [0x14,0xf8,0x82,0xb9] // GFX10: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; encoding: [0x14,0xf8,0x82,0xb9]
s_setreg_b32 hwreg(21), s2 s_setreg_b32 hwreg(21), s2
// SICI: s_setreg_b32 hwreg(21), s2 ; encoding: [0x15,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(21), s2 ; encoding: [0x15,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(21), s2 ; encoding: [0x15,0xf8,0x02,0xb9] // VI9: s_setreg_b32 hwreg(21), s2 ; encoding: [0x15,0xf8,0x02,0xb9]
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llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt

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0x41,0x31,0xfc,0xb8 0x41,0x31,0xfc,0xb8
# CHECK: s_getreg_b32 exec_lo, hwreg(HW_REG_MODE, 5, 7) ; encoding: [0x41,0x31,0xfe,0xb8] # CHECK: s_getreg_b32 exec_lo, hwreg(HW_REG_MODE, 5, 7) ; encoding: [0x41,0x31,0xfe,0xb8]
0x41,0x31,0xfe,0xb8 0x41,0x31,0xfe,0xb8
# CHECK: s_getreg_b32 exec_hi, hwreg(HW_REG_MODE, 5, 7) ; encoding: [0x41,0x31,0xff,0xb8] # CHECK: s_getreg_b32 exec_hi, hwreg(HW_REG_MODE, 5, 7) ; encoding: [0x41,0x31,0xff,0xb8]
0x41,0x31,0xff,0xb8 0x41,0x31,0xff,0xb8
# CHECK: s_getreg_b32 s5, hwreg(17, 7, 25) ; encoding: [0xd1,0xc1,0x85,0xb8] # CHECK: s_getreg_b32 s5, hwreg(HW_REG_TBA_HI, 7, 25) ; encoding: [0xd1,0xc1,0x85,0xb8]
0xd1,0xc1,0x85,0xb8 0xd1,0xc1,0x85,0xb8
# CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), s1 ; encoding: [0x41,0x31,0x01,0xb9] # CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), s1 ; encoding: [0x41,0x31,0x01,0xb9]
0x41,0x31,0x01,0xb9 0x41,0x31,0x01,0xb9
# CHECK: s_setreg_b32 hwreg(17, 7, 25), s1 ; encoding: [0xd1,0xc1,0x01,0xb9] # CHECK: s_setreg_b32 hwreg(HW_REG_TBA_HI, 7, 25), s1 ; encoding: [0xd1,0xc1,0x01,0xb9]
0xd1,0xc1,0x01,0xb9 0xd1,0xc1,0x01,0xb9
# CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), s101 ; encoding: [0x41,0x31,0x65,0xb9] # CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), s101 ; encoding: [0x41,0x31,0x65,0xb9]
0x41,0x31,0x65,0xb9 0x41,0x31,0x65,0xb9
# CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), flat_scratch_lo ; encoding: [0x41,0x31,0x66,0xb9] # CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), flat_scratch_lo ; encoding: [0x41,0x31,0x66,0xb9]
0x41,0x31,0x66,0xb9 0x41,0x31,0x66,0xb9
Show All 13 Lines
0x41,0x31,0x7e,0xb9 0x41,0x31,0x7e,0xb9
# CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), exec_hi ; encoding: [0x41,0x31,0x7f,0xb9] # CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), exec_hi ; encoding: [0x41,0x31,0x7f,0xb9]
0x41,0x31,0x7f,0xb9 0x41,0x31,0x7f,0xb9
# CHECK: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 5, 7), 0x11213141 ; encoding: [0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11] # CHECK: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 5, 7), 0x11213141 ; encoding: [0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11]
0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11 0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11
# CHECK: s_setreg_imm32_b32 hwreg(17, 7, 25), 0x11213141 ; encoding: [0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11] # CHECK: s_setreg_imm32_b32 hwreg(HW_REG_TBA_HI, 7, 25), 0x11213141 ; encoding: [0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11]
0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11 0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11
# CHECK: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 5, 7), 0xa1b1c1d1 ; encoding: [0x41,0x31,0x00,0xba,0xd1,0xc1,0xb1,0xa1] # CHECK: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 5, 7), 0xa1b1c1d1 ; encoding: [0x41,0x31,0x00,0xba,0xd1,0xc1,0xb1,0xa1]
0x41,0x31,0x00,0xba,0xd1,0xc1,0xb1,0xa1 0x41,0x31,0x00,0xba,0xd1,0xc1,0xb1,0xa1
# CHECK: s_nop 0x3141 ; encoding: [0x41,0x31,0x80,0xbf] # CHECK: s_nop 0x3141 ; encoding: [0x41,0x31,0x80,0xbf]
0x41,0x31,0x80,0xbf 0x41,0x31,0x80,0xbf
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