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Differential D118123

[AMDGPU][MC][GFX9] Enabled TBA/TMA access via setreg/getreg
AbandonedPublic

Authored by dp on Jan 25 2022, 3:31 AM.

Details

Reviewers
foad
Summary

TBA and TMA are not accessible as assembler registers in GFX9, but they should be available via s_getreg and s_setreg instructions.

Diff Detail

Event Timeline

dp created this revision.Jan 25 2022, 3:31 AM
Herald added subscribers: kerbowa, hiraditya, t-tye and 7 others. · View Herald TranscriptJan 25 2022, 3:31 AM
dp requested review of this revision.Jan 25 2022, 3:31 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 25 2022, 3:31 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
foad added inline comments.Jan 25 2022, 3:41 AM
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
1036–1037

Did you mean to include this in this patch?

llvm/test/MC/AMDGPU/sopk.s
268

This is a strange example because TBA is read-only, but I guess the assembler does not know that. So OK.

dp added inline comments.Jan 25 2022, 5:23 AM
llvm/test/MC/AMDGPU/sopk.s
268

Yes, the tests are rather formal. The assembler does not currently validate such things.

foad added inline comments.Jan 25 2022, 5:34 AM
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
1036–1037

Oh, I see, adding the check for POPS_PACKER is NFC because the getLastSymbolicHwreg would exclude it for GFX9 and below anyway. I guess it is OK to leave it here for consistency if you prefer.

Harbormaster completed remote builds in B145448: Diff 402811.Jan 26 2022, 2:31 PM
dp updated this revision to Diff 403994.Jan 28 2022, 6:03 AM

Removed unnecessary code.

Harbormaster completed remote builds in B146268: Diff 403994.Jan 28 2022, 7:21 AM
dp mentioned this in D118860: [AMDGPU] HWRegs TMA and TBA also supported on gfx9.Feb 3 2022, 1:27 AM
dp abandoned this revision.Feb 3 2022, 10:30 AM

See D118860

Revision Contents

PathSize
llvm/
docs/
AMDGPU/
4 lines
lib/
Target/
AMDGPU/
Utils/
5 lines
test/
MC/
AMDGPU/
8 lines
24 lines
Disassembler/
AMDGPU/
6 lines

Diff 403994

llvm/docs/AMDGPU/gfx9_hwreg.rst

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 LinesDefined register *names* include:
HW_REG_MODE Shader writeable mode bits. HW_REG_MODE Shader writeable mode bits.
HW_REG_STATUS Shader read-only status. HW_REG_STATUS Shader read-only status.
HW_REG_TRAPSTS Trap status. HW_REG_TRAPSTS Trap status.
HW_REG_HW_ID Id of wave, simd, compute unit, etc. HW_REG_HW_ID Id of wave, simd, compute unit, etc.
HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation. HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
HW_REG_LDS_ALLOC Per-wave LDS allocation. HW_REG_LDS_ALLOC Per-wave LDS allocation.
HW_REG_IB_STS Counters of outstanding instructions. HW_REG_IB_STS Counters of outstanding instructions.
HW_REG_SH_MEM_BASES Memory aperture. HW_REG_SH_MEM_BASES Memory aperture.
HW_REG_TBA_LO tba_lo register.
HW_REG_TBA_HI tba_hi register.
HW_REG_TMA_LO tma_lo register.
HW_REG_TMA_HI tma_hi register.
=================== ========================================== =================== ==========================================
Examples: Examples:
.. parsed-literal:: .. parsed-literal::
reg = 1 reg = 1
offset = 2 offset = 2
Show All 11 Lines

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Show First 20 Lines • Show All 1,022 Lines • ▼ Show 20 Linesbool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI) {
switch (Id) { switch (Id) {
case ID_HW_ID: case ID_HW_ID:
return isSI(STI) || isCI(STI) || isVI(STI) || isGFX9(STI); return isSI(STI) || isCI(STI) || isVI(STI) || isGFX9(STI);
case ID_HW_ID1: case ID_HW_ID1:
case ID_HW_ID2: case ID_HW_ID2:
return isGFX10Plus(STI); return isGFX10Plus(STI);
case ID_XNACK_MASK: case ID_XNACK_MASK:
return isGFX10(STI) && !AMDGPU::isGFX10_BEncoding(STI); return isGFX10(STI) && !AMDGPU::isGFX10_BEncoding(STI);
case ID_TBA_LO:
case ID_TBA_HI:
case ID_TMA_LO:
case ID_TMA_HI:
return isGFX9Plus(STI);
default: default:
return ID_SYMBOLIC_FIRST_ <= Id && Id < getLastSymbolicHwreg(STI) && return ID_SYMBOLIC_FIRST_ <= Id && Id < getLastSymbolicHwreg(STI) &&
foadUnsubmitted
Not Done
ReplyInline Actions

Did you mean to include this in this patch?

foad: Did you mean to include this in this patch?
foadUnsubmitted
Not Done
ReplyInline Actions

Oh, I see, adding the check for POPS_PACKER is NFC because the getLastSymbolicHwreg would exclude it for GFX9 and below anyway. I guess it is OK to leave it here for consistency if you prefer.

foad: Oh, I see, adding the check for POPS_PACKER is NFC because the getLastSymbolicHwreg would…
IdSymbolic[Id]; IdSymbolic[Id];
} }
} }
bool isValidHwreg(int64_t Id) { bool isValidHwreg(int64_t Id) {
return 0 <= Id && isUInt<ID_WIDTH_>(Id); return 0 <= Id && isUInt<ID_WIDTH_>(Id);
} }
▲ Show 20 Lines • Show All 1,028 Lines • Show Last 20 Lines

llvm/test/MC/AMDGPU/sopk-err.s

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9]
// SICIVI-ERR: error: specified hardware register is not supported on this GPU // SICIVI-ERR: error: specified hardware register is not supported on this GPU
// GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8] // GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) s_getreg_b32 s2, hwreg(HW_REG_TBA_LO)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9]
// SICIVI-ERR: error: specified hardware register is not supported on this GPU // SICIVI-ERR: error: specified hardware register is not supported on this GPU
// GFX9-ERR: error: specified hardware register is not supported on this GPU // GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) s_getreg_b32 s2, hwreg(HW_REG_TBA_HI)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9]
// SICIVI-ERR: error: specified hardware register is not supported on this GPU // SICIVI-ERR: error: specified hardware register is not supported on this GPU
// GFX9-ERR: error: specified hardware register is not supported on this GPU // GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) s_getreg_b32 s2, hwreg(HW_REG_TMA_LO)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9]
// SICIVI-ERR: error: specified hardware register is not supported on this GPU // SICIVI-ERR: error: specified hardware register is not supported on this GPU
// GFX9-ERR: error: specified hardware register is not supported on this GPU // GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) s_getreg_b32 s2, hwreg(HW_REG_TMA_HI)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9]
// SICIVI-ERR: error: specified hardware register is not supported on this GPU // SICIVI-ERR: error: specified hardware register is not supported on this GPU
// GFX9-ERR: error: specified hardware register is not supported on this GPU // GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9]
// SICIVI-ERR: error: specified hardware register is not supported on this GPU // SICIVI-ERR: error: specified hardware register is not supported on this GPU
// GFX9-ERR: error: specified hardware register is not supported on this GPU // GFX9-ERR: error: specified hardware register is not supported on this GPU
s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI) s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI)
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI) ; encoding: [0x15,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI) ; encoding: [0x15,0xf8,0x02,0xb9]
Show All 27 Lines

llvm/test/MC/AMDGPU/sopk.s

Show First 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
// SICI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x02,0xb9]
// VI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x82,0xb8] // VI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x82,0xb8]
// GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8] // GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9]
// GFX10+ registers // GFX10+ registers
s_getreg_b32 s2, hwreg(16) s_getreg_b32 s2, hwreg(16)
// SICI: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9]
// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x82,0xb8]
// VI: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(17) s_getreg_b32 s2, hwreg(17)
// SICI: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9]
// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x82,0xb8]
// VI: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(18) s_getreg_b32 s2, hwreg(18)
// SICI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9]
// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x82,0xb8]
// VI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(19) s_getreg_b32 s2, hwreg(19)
// SICI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9]
// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x82,0xb8]
// VI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x82,0xb8]
s_getreg_b32 s2, hwreg(20) s_getreg_b32 s2, hwreg(20)
// SICI: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x82,0xb8] // VI9: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x82,0xb8]
// GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9] // GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9]
s_getreg_b32 s2, hwreg(21) s_getreg_b32 s2, hwreg(21)
// SICI: s_getreg_b32 s2, hwreg(21) ; encoding: [0x15,0xf8,0x02,0xb9] // SICI: s_getreg_b32 s2, hwreg(21) ; encoding: [0x15,0xf8,0x02,0xb9]
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
// SICI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x82,0xb9]
// VI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x02,0xb9] // VI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x02,0xb9]
// GFX9: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x02,0xb9] // GFX9: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x82,0xb9] // GFX10: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x82,0xb9]
// GFX10+ registers // GFX10+ registers
s_setreg_b32 hwreg(16), s2 s_setreg_b32 hwreg(16), s2
// SICI: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_TBA_LO), s2 ; encoding: [0x10,0xf8,0x82,0xb9] // GFX10: s_setreg_b32 hwreg(HW_REG_TBA_LO), s2 ; encoding: [0x10,0xf8,0x82,0xb9]
// GFX9: s_setreg_b32 hwreg(HW_REG_TBA_LO), s2 ; encoding: [0x10,0xf8,0x02,0xb9]
foadUnsubmitted
Not Done
ReplyInline Actions

This is a strange example because TBA is read-only, but I guess the assembler does not know that. So OK.

foad: This is a strange example because TBA is read-only, but I guess the assembler does not know…
dpAuthorUnsubmitted
Done
ReplyInline Actions

Yes, the tests are rather formal. The assembler does not currently validate such things.

dp: Yes, the tests are rather formal. The assembler does not currently validate such things.
// VI: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x02,0xb9]
s_setreg_b32 hwreg(17), s2 s_setreg_b32 hwreg(17), s2
// SICI: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x82,0xb9] // GFX10: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x82,0xb9]
// GFX9: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x02,0xb9]
// VI: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x02,0xb9]
s_setreg_b32 hwreg(18), s2 s_setreg_b32 hwreg(18), s2
// SICI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x82,0xb9] // GFX10: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x82,0xb9]
// GFX9: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x02,0xb9]
// VI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x02,0xb9]
s_setreg_b32 hwreg(19), s2 s_setreg_b32 hwreg(19), s2
// SICI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x82,0xb9] // GFX10: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x82,0xb9]
// GFX9: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x02,0xb9]
// VI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x02,0xb9]
s_setreg_b32 hwreg(20), s2 s_setreg_b32 hwreg(20), s2
// SICI: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x02,0xb9] // VI9: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x02,0xb9]
// GFX10: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; encoding: [0x14,0xf8,0x82,0xb9] // GFX10: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; encoding: [0x14,0xf8,0x82,0xb9]
s_setreg_b32 hwreg(21), s2 s_setreg_b32 hwreg(21), s2
// SICI: s_setreg_b32 hwreg(21), s2 ; encoding: [0x15,0xf8,0x82,0xb9] // SICI: s_setreg_b32 hwreg(21), s2 ; encoding: [0x15,0xf8,0x82,0xb9]
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llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt

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0x41,0x31,0xfc,0xb8 0x41,0x31,0xfc,0xb8
# CHECK: s_getreg_b32 exec_lo, hwreg(HW_REG_MODE, 5, 7) ; encoding: [0x41,0x31,0xfe,0xb8] # CHECK: s_getreg_b32 exec_lo, hwreg(HW_REG_MODE, 5, 7) ; encoding: [0x41,0x31,0xfe,0xb8]
0x41,0x31,0xfe,0xb8 0x41,0x31,0xfe,0xb8
# CHECK: s_getreg_b32 exec_hi, hwreg(HW_REG_MODE, 5, 7) ; encoding: [0x41,0x31,0xff,0xb8] # CHECK: s_getreg_b32 exec_hi, hwreg(HW_REG_MODE, 5, 7) ; encoding: [0x41,0x31,0xff,0xb8]
0x41,0x31,0xff,0xb8 0x41,0x31,0xff,0xb8
# CHECK: s_getreg_b32 s5, hwreg(17, 7, 25) ; encoding: [0xd1,0xc1,0x85,0xb8] # CHECK: s_getreg_b32 s5, hwreg(HW_REG_TBA_HI, 7, 25) ; encoding: [0xd1,0xc1,0x85,0xb8]
0xd1,0xc1,0x85,0xb8 0xd1,0xc1,0x85,0xb8
# CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), s1 ; encoding: [0x41,0x31,0x01,0xb9] # CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), s1 ; encoding: [0x41,0x31,0x01,0xb9]
0x41,0x31,0x01,0xb9 0x41,0x31,0x01,0xb9
# CHECK: s_setreg_b32 hwreg(17, 7, 25), s1 ; encoding: [0xd1,0xc1,0x01,0xb9] # CHECK: s_setreg_b32 hwreg(HW_REG_TBA_HI, 7, 25), s1 ; encoding: [0xd1,0xc1,0x01,0xb9]
0xd1,0xc1,0x01,0xb9 0xd1,0xc1,0x01,0xb9
# CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), s101 ; encoding: [0x41,0x31,0x65,0xb9] # CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), s101 ; encoding: [0x41,0x31,0x65,0xb9]
0x41,0x31,0x65,0xb9 0x41,0x31,0x65,0xb9
# CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), flat_scratch_lo ; encoding: [0x41,0x31,0x66,0xb9] # CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), flat_scratch_lo ; encoding: [0x41,0x31,0x66,0xb9]
0x41,0x31,0x66,0xb9 0x41,0x31,0x66,0xb9
Show All 13 Lines
0x41,0x31,0x7e,0xb9 0x41,0x31,0x7e,0xb9
# CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), exec_hi ; encoding: [0x41,0x31,0x7f,0xb9] # CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), exec_hi ; encoding: [0x41,0x31,0x7f,0xb9]
0x41,0x31,0x7f,0xb9 0x41,0x31,0x7f,0xb9
# CHECK: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 5, 7), 0x11213141 ; encoding: [0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11] # CHECK: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 5, 7), 0x11213141 ; encoding: [0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11]
0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11 0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11
# CHECK: s_setreg_imm32_b32 hwreg(17, 7, 25), 0x11213141 ; encoding: [0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11] # CHECK: s_setreg_imm32_b32 hwreg(HW_REG_TBA_HI, 7, 25), 0x11213141 ; encoding: [0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11]
0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11 0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11
# CHECK: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 5, 7), 0xa1b1c1d1 ; encoding: [0x41,0x31,0x00,0xba,0xd1,0xc1,0xb1,0xa1] # CHECK: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 5, 7), 0xa1b1c1d1 ; encoding: [0x41,0x31,0x00,0xba,0xd1,0xc1,0xb1,0xa1]
0x41,0x31,0x00,0xba,0xd1,0xc1,0xb1,0xa1 0x41,0x31,0x00,0xba,0xd1,0xc1,0xb1,0xa1
# CHECK: s_nop 0x3141 ; encoding: [0x41,0x31,0x80,0xbf] # CHECK: s_nop 0x3141 ; encoding: [0x41,0x31,0x80,0xbf]
0x41,0x31,0x80,0xbf 0x41,0x31,0x80,0xbf
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