[NVPTX] Remove fmin/fmax.NaN.f64 again

[csigg]

Summary

Added in https://reviews.llvm.org/D117204, but it does not exist.

[tra]

Is it fine to leave the change in llvm/lib/Target/NVPTX/NVPTXInstrInfo.td as is?

I'd add a comment around FMINNAN that f64 variants do not actually exist. As long as we never lower to it it's not worth the trouble of refactoring tablegen to deal with a minor exception.

llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

575–577

Shouldn't all these actions be Legal, given that we have instructions for them?

[csigg]

Add comment.

[csigg]

In D118398#3277316, @tra wrote:

Is it fine to leave the change in llvm/lib/Target/NVPTX/NVPTXInstrInfo.td as is?

I'd add a comment around FMINNAN that f64 variants do not actually exist. As long as we never lower to it it's not worth the trouble of refactoring tablegen to deal with a minor exception.

Makes sense. Thanks.

llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

575–577

They are Legal for sm_80+, see the GetMinMaxAction() implementation.
For f16 and v2f16, we additionally require that fp16 is not disabled (see setFP16OperationAction())

llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
   };
   for (const auto &Op : {ISD::FMINNUM, ISD::FMAXNUM}) {
     setFP16OperationAction(Op, MVT::f16, GetMinMaxAction(Promote), Promote);
     setOperationAction(Op, MVT::f32, Legal);
     setOperationAction(Op, MVT::f64, Legal);
     setFP16OperationAction(Op, MVT::v2f16, GetMinMaxAction(Expand), Expand);
   }
   for (const auto &Op : {ISD::FMINIMUM, ISD::FMAXIMUM}) {
     setFP16OperationAction(Op, MVT::f16, GetMinMaxAction(Expand), Expand);
     setOperationAction(Op, MVT::f32, GetMinMaxAction(Expand));
-    setOperationAction(Op, MVT::f64, GetMinMaxAction(Expand));
     setFP16OperationAction(Op, MVT::v2f16, GetMinMaxAction(Expand), Expand);
   }
 
   // No FEXP2, FLOG2.  The PTX ex2 and log2 functions are always approximate.
   // No FPOW or FREM in PTX.
 
   // Now deduce the information based on the above mentioned
   // actions
   computeRegisterProperties(STI.getRegisterInfo());

llvm/lib/Target/NVPTX/NVPTXInstrInfo.td

NVPTXInst<(outs Float16Regs:$dst), (ins f16imm:$a),
             "mov.b16 \t$dst, $a;", []>;
 
 defm FADD : F3_fma_component<"add", fadd>;
 defm FSUB : F3_fma_component<"sub", fsub>;
 defm FMUL : F3_fma_component<"mul", fmul>;
 
 defm FMIN : F3<"min", fminnum>;
 defm FMAX : F3<"max", fmaxnum>;
+// Note: min.NaN.f64 and max.NaN.f64 do not actually exist.
 defm FMINNAN : F3<"min.NaN", fminimum>;
 defm FMAXNAN : F3<"max.NaN", fmaximum>;
 
 defm FABS  : F2<"abs", fabs>;
 defm FNEG  : F2<"neg", fneg>;
 defm FSQRT : F2<"sqrt.rn", fsqrt>;
 
 //

llvm/test/CodeGen/NVPTX/fminimum-fmaximum.ll

define float @minimum_float(float %a) #0 {
   ; CHECK-NAN: min.NaN.f32
   %p = fcmp ult float %a, 0.0
   %x = select i1 %p, float %a, float 0.0
   ret float %x
 }
 
 ; CHECK-LABEL: minimum_double
 define double @minimum_double(double %a) #0 {
-  ; CHECK-NONAN: setp
-  ; CHECK-NONAN: selp.f64
-  ; CHECK-NAN: min.NaN.f64
+  ; CHECK: setp
+  ; CHECK: selp.f64
   %p = fcmp ult double %a, 0.0
   %x = select i1 %p, double %a, double 0.0
   ret double %x
 }
 
 ; CHECK-LABEL: minimum_v2half
 define <2 x half> @minimum_v2half(<2 x half> %a) #0 {
   ; CHECK-NONAN-DAG: setp
define float @maximum_float(float %a) #0 {
   ; CHECK-NAN: max.NaN.f32
   %p = fcmp ugt float %a, 0.0
   %x = select i1 %p, float %a, float 0.0
   ret float %x
 }
 
 ; CHECK-LABEL: maximum_double
 define double @maximum_double(double %a) #0 {
-  ; CHECK-NONAN: setp
-  ; CHECK-NONAN: selp.f64
-  ; CHECK-NAN: max.NaN.f64
+  ; CHECK: setp
+  ; CHECK: selp.f64
   %p = fcmp ugt double %a, 0.0
   %x = select i1 %p, double %a, double 0.0
   ret double %x
 }
 
 ; CHECK-LABEL: maximum_v2half
 define <2 x half> @maximum_v2half(<2 x half> %a) #0 {
   ; CHECK-NONAN-DAG: setp
   ; CHECK-NONAN-DAG: setp
   ; CHECK-NONAN-DAG: selp.b16
   ; CHECK-NONAN-DAG: selp.b16
   ; CHECK-NAN: max.NaN.f16x2
   %p = fcmp ugt <2 x half> %a, zeroinitializer
   %x = select <2 x i1> %p, <2 x half> %a, <2 x half> zeroinitializer
   ret <2 x half> %x
 }