[PowerPC] Remove the LDMX instruction.

[stefanp]

Summary

The LDMX instruction was to be potentially added in P9 but it was never added
in either ISA 3.0 or ISA 3.1. This patch removes that instruction as it is
currently still an invalid instruction.

[lei]

LGTM
Thx for the cleanup!

llvm/lib/Target/PowerPC/P10InstrResources.td

def : InstRW<[P10W_SX, P10W_DISP_ANY],
     DCBI,
     DCBZL,
     DCCCI,
     ICBLC,
     ICBLQ,
     ICBTLS,
     ICCCI,
     LA, LA8,
-    LDMX,
     MFDCR,
     MFPMR,
     MFSRIN,
     MSYNC,
     MTDCR,
     MTPMR,
     MTSRIN,
     NAP,

llvm/lib/Target/PowerPC/P9InstrResources.td

 // Consecutive Store and ALU instructions. The store is restricted and requires
 // three dispatches.
 def : InstRW<[P9_StoreAndALUOp_3C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
     (instregex "ST(B|H|W|D)CX$")
 )>;
 
-// Cracked Load Instruction.
-// Two consecutive load operations for a total of 8 cycles.
-def : InstRW<[P9_LoadAndLoadOp_8C, IP_AGEN_1C, IP_AGEN_1C,
-              DISP_1C, DISP_1C],
-      (instrs
-    LDMX
-)>;
-
 // Cracked Load instruction.
 // Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
 // operations cannot be done at the same time and so their latencies are added.
 def : InstRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C,
               DISP_1C, DISP_1C],
       (instrs
     (instregex "LHA(X)?(8)?$"),
     (instregex "CP_PASTE(8)?_rec$"),

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

def LDU  : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
                     []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
                     NoEncode<"$ea_result">;
 
 def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
                         (ins memrr:$addr),
                         "ldux $rD, $addr", IIC_LdStLDUX,
                         []>, RegConstraint<"$addr.ptrreg = $ea_result">,
                         NoEncode<"$ea_result">, isPPC64;
-
-def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src),
-                   "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64,
-                   Requires<[IsISA3_0]>;
 }
 
 let mayLoad = 1, hasNoSchedulingInfo = 1 in {
 // Full 16-byte load.
 // Early clobber $RTp to avoid assigned to the same register as RA.
 // TODO: Add scheduling info.
 def LQ   : DQForm_RTp5_RA17_MEM<56, 0,
                                 (outs g8prc:$RTp),

llvm/lib/Target/PowerPC/PPCScheduleP9.td

let SchedModel = P9Model in {
   // These are combinations of the resources listed above.
   // The idea is that some cracked instructions cannot be done in parallel and
   // so the latencies for their resources must be added.
   def P9_LoadAndALUOp_6C : WriteSequence<[P9_LS_4C, P9_ALU_2C]>;
   def P9_LoadAndALUOp_7C : WriteSequence<[P9_LS_5C, P9_ALU_2C]>;
   def P9_LoadAndALU2Op_7C : WriteSequence<[P9_LS_4C, P9_ALU_3C]>;
   def P9_LoadAndALU2Op_8C : WriteSequence<[P9_LS_5C, P9_ALU_3C]>;
   def P9_LoadAndPMOp_8C : WriteSequence<[P9_LS_5C, P9_PM_3C]>;
-  def P9_LoadAndLoadOp_8C : WriteSequence<[P9_LS_4C, P9_LS_4C]>;
   def P9_IntDivAndALUOp_18C_8 : WriteSequence<[P9_DIV_16C_8, P9_ALU_2C]>;
   def P9_IntDivAndALUOp_26C_8 : WriteSequence<[P9_DIV_24C_8, P9_ALU_2C]>;
   def P9_IntDivAndALUOp_42C_8 : WriteSequence<[P9_DIV_40C_8, P9_ALU_2C]>;
   def P9_StoreAndALUOp_3C : WriteSequence<[P9_LS_1C, P9_ALU_2C]>;
   def P9_ALUOpAndALUOp_4C : WriteSequence<[P9_ALU_2C, P9_ALU_2C]>;
   def P9_ALU2OpAndALU2Op_6C : WriteSequence<[P9_ALU_3C, P9_ALU_3C]>;
   def P9_ALUOpAndALUOpAndALUOp_6C :
     WriteSequence<[P9_ALU_2C, P9_ALU_2C, P9_ALU_2C]>;

llvm/lib/Target/PowerPC/README_P9.txt

 
 Atomic operations (l[dw]at, st[dw]at):
 - Provide custom lowering for common atomic operations to use these
   instructions with the correct Function Code
 - Ensure the operands are in the correct register (i.e. RT+1, RT+2)
 - Provide builtins since not all FC's necessarily have an existing LLVM
   atomic operation
 
-Load Doubleword Monitored (ldmx):
-- Investigate whether there are any uses for this. It seems to be related to
-  Garbage Collection so it isn't likely to be all that useful for most
-  languages we deal with.
-
 Move to CR from XER Extended (mcrxrx):
 - Is there a use for this in LLVM?
 
 Fixed Point Facility:
 
 - Copy-Paste Facility: copy copy_first cp_abort paste paste. paste_last
   . Use instrinstics:
     (int_ppc_copy_first i32:$rA, i32:$rB)

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt

 0x7c 0x43 0x20 0x2a
 
 # CHECK: ldu 2, 128(4)                   
 0xe8 0x44 0x00 0x81
 
 # CHECK: ldux 2, 3, 4                    
 0x7c 0x43 0x20 0x6a
 
-# CHECK: ldmx 2, 3, 4
-0x7c 0x43 0x22 0x6a
-
 # CHECK: lq 2, 128(4)
 0xe0 0x44 0x00 0x80
 
 # CHECK: lq 28, 128(30)
 0xe3 0x9e 0x00 0x80
 
 # CHECK: stb 2, 128(4)                   
 0x98 0x44 0x00 0x80

llvm/test/MC/PowerPC/ppc64-encoding.s

 # CHECK-LE: ldx 2, 3, 4                     # encoding: [0x2a,0x20,0x43,0x7c]
             ldx 2, 3, 4
 # CHECK-BE: ldu 2, 128(4)                   # encoding: [0xe8,0x44,0x00,0x81]
 # CHECK-LE: ldu 2, 128(4)                   # encoding: [0x81,0x00,0x44,0xe8]
             ldu 2, 128(4)
 # CHECK-BE: ldux 2, 3, 4                    # encoding: [0x7c,0x43,0x20,0x6a]
 # CHECK-LE: ldux 2, 3, 4                    # encoding: [0x6a,0x20,0x43,0x7c]
             ldux 2, 3, 4
-# CHECK-BE: ldmx 2, 3, 4                    # encoding: [0x7c,0x43,0x22,0x6a]
-# CHECK-LE: ldmx 2, 3, 4                    # encoding: [0x6a,0x22,0x43,0x7c]
-            ldmx 2, 3, 4
 # CHECK-BE: lq 2, 128(4)                    # encoding: [0xe0,0x44,0x00,0x80]
 # CHECK-LE: lq 2, 128(4)                    # encoding: [0x80,0x00,0x44,0xe0]
             lq 2, 128(4)
 # CHECK-BE: lq 28, 128(30)                  # encoding: [0xe3,0x9e,0x00,0x80]
 # CHECK-LE: lq 28, 128(30)                  # encoding: [0x80,0x00,0x9e,0xe3]
             lq 28, 128(30)
 
 # Fixed-point store instructions