[AVR] Remove regalloc workaround for LDDWRdPtrQ

[aykevl]

Summary

Background: https://github.com/avr-rust/rust-legacy-fork/issues/126

In short, this workaround was introduced to fix a "ran out of registers
during regalloc" issue. The root cause has since been fixed in
https://reviews.llvm.org/D54218 so this workaround can be removed.

There is one test that changes a little bit, removing a single
instruction. I also compiled compiler-rt before and after this patch but
didn't see a difference. So presumably the impact is very low. Still,
it's nice to be able to remove such a workaround.

[timwalls]

Hi Folks,

I hate to say this, but I fear rolling this back may have been premature :-/. I am not even in the same universe as a MRE at the moment, just trying to work out why "stuff that used to work stopped working" recently, and I am getting errors like this:

*** Bad machine code: Using an undefined physical register ***
- function:    _ZN93_$LT$avr_oxide..devices..button..Button$LT$S$GT$$u20$as$u20$avr_oxide..event..EventSource$GT$13process_event17hb980a9f4dd8ffea1E
- basic block: %bb.2  (0x106888698)
- instruction: early-clobber $r31r30 = LDDWRdPtrQ killed $r31r30, 2, debug-location !10410 :: (load (s16) from %ir.26, align 1, !alias.scope !10396); /Users/timwa/Development/rust-avr-nightly-builder/build/rust/build/aarch64-apple-darwin/stage2/lib/rustlib/src/rust/library/alloc/src/boxed.rs:1861:38 @[ /Users/timwa/Development/avr-oxide/src/devices/button.rs:214:9 ]
- operand 1:   killed $r31r30
LLVM ERROR: Found 1 machine code errors.

(And of course the faithful ran out of registers... error.)

Re-applying this workaround patch makes the error go away :/. I will endeavour to reduce to a smaller example of course, right now it's buried in the middle of a codebase, but just to flag it up early - :-(.

llvm/lib/Target/AVR/AVRInstrInfo.td

let Constraints = "@earlyclobber $reg" in def LDDRdPtrQ
       Requires<[HasSRAM]>;
 
   // LDDW Rd+1:Rd, P+q
   //
   // Expands to:
   // ldd Rd,   P+q
   // ldd Rd+1, P+q+1
   let Constraints = "@earlyclobber $dst" in def LDDWRdPtrQ
-      : Pseudo<(outs DREGS_WITHOUT_YZ_WORKAROUND
+      : Pseudo<(outs DREGS
                 : $dst),
                (ins memri
                 : $memri),
                "lddw\t$dst, $memri", [(set i16
                                        : $dst, (load addr
                                                 : $memri))]>,
       Requires<[HasSRAM]>;
 

llvm/lib/Target/AVR/AVRRegisterInfo.td

def DREGSMOVW : RegisterClass<"AVR", [i16], 8,
                                   // Return value and arguments.
                                   add R25R24, R19R18, R21R20, R23R22,
                                   // Scratch registers.
                                   R31R30, R27R26,
                                   // Callee saved registers.
                                   R29R28, R17R16, R15R14, R13R12, R11R10, R9R8,
                                   R7R6, R5R4, R3R2, R1R0)>;
 
-// The 16-bit DREGS register class, excluding the Z pointer register.
-//
-// This is used by instructions which cause high pointer register
-// contention which leads to an assertion in the register allocator.
-//
-// There is no technical reason why instructions that use this class
-// cannot use Z; it's simply a workaround a regalloc bug.
-//
-// More information can be found in PR39553.
-def DREGS_WITHOUT_YZ_WORKAROUND
-    : RegisterClass<"AVR", [i16], 8,
-                    (
-                        // Return value and arguments.
-                        add R25R24, R19R18, R21R20, R23R22,
-                        // Scratch registers.
-                        R27R26,
-                        // Callee saved registers.
-                        R17R16, R15R14, R13R12, R11R10, R9R8, R7R6, R5R4, R3R2,
-                        R1R0)>;
-
 // 16-bit register class for immediate instructions.
 def DLDREGS : RegisterClass<"AVR", [i16], 8,
                             (
                                 // Return value and arguments.
                                 add R25R24, R19R18, R21R20, R23R22,
                                 // Scratch registers.
                                 R31R30, R27R26,
                                 // Callee saved registers.

llvm/test/CodeGen/AVR/lpmx.ll

 ; CHECK-O0-NEXT:    sbiw r28, 2
 ; CHECK-O0-NEXT:    in r0, 63
 ; CHECK-O0-NEXT:    cli
 ; CHECK-O0-NEXT:    out 62, r29
 ; CHECK-O0-NEXT:    out 63, r0
 ; CHECK-O0-NEXT:    out 61, r28
 ; CHECK-O0-NEXT:    std Y+1, r24
 ; CHECK-O0-NEXT:    std Y+2, r25
-; CHECK-O0-NEXT:    ldd r24, Y+1
-; CHECK-O0-NEXT:    ldd r25, Y+2
-; CHECK-O0-NEXT:    lsl r24
-; CHECK-O0-NEXT:    rol r25
-; CHECK-O0-NEXT:    subi r24, -lo8(arr0)
-; CHECK-O0-NEXT:    sbci r25, -hi8(arr0)
-; CHECK-O0-NEXT:    movw r30, r24
+; CHECK-O0-NEXT:    ldd r30, Y+1
+; CHECK-O0-NEXT:    ldd r31, Y+2
+; CHECK-O0-NEXT:    lsl r30
+; CHECK-O0-NEXT:    rol r31
+; CHECK-O0-NEXT:    subi r30, -lo8(arr0)
+; CHECK-O0-NEXT:    sbci r31, -hi8(arr0)
 ; CHECK-O0-NEXT:    lpm r24, Z+
 ; CHECK-O0-NEXT:    lpm r25, Z
 ; CHECK-O0-NEXT:    adiw r28, 2
 ; CHECK-O0-NEXT:    in r0, 63
 ; CHECK-O0-NEXT:    cli
 ; CHECK-O0-NEXT:    out 62, r29
 ; CHECK-O0-NEXT:    out 63, r0
 ; CHECK-O0-NEXT:    out 61, r28

 ; CHECK-O0-NEXT:    sbiw r28, 2
 ; CHECK-O0-NEXT:    in r0, 63
 ; CHECK-O0-NEXT:    cli
 ; CHECK-O0-NEXT:    out 62, r29
 ; CHECK-O0-NEXT:    out 63, r0
 ; CHECK-O0-NEXT:    out 61, r28
 ; CHECK-O0-NEXT:    std Y+1, r24
 ; CHECK-O0-NEXT:    std Y+2, r25
-; CHECK-O0-NEXT:    ldd r24, Y+1
-; CHECK-O0-NEXT:    ldd r25, Y+2
-; CHECK-O0-NEXT:    subi r24, -lo8(arr1)
-; CHECK-O0-NEXT:    sbci r25, -hi8(arr1)
-; CHECK-O0-NEXT:    movw r30, r24
+; CHECK-O0-NEXT:    ldd r30, Y+1
+; CHECK-O0-NEXT:    ldd r31, Y+2
+; CHECK-O0-NEXT:    subi r30, -lo8(arr1)
+; CHECK-O0-NEXT:    sbci r31, -hi8(arr1)
 ; CHECK-O0-NEXT:    lpm r24, Z
 ; CHECK-O0-NEXT:    adiw r28, 2
 ; CHECK-O0-NEXT:    in r0, 63
 ; CHECK-O0-NEXT:    cli
 ; CHECK-O0-NEXT:    out 62, r29
 ; CHECK-O0-NEXT:    out 63, r0
 ; CHECK-O0-NEXT:    out 61, r28
 ; CHECK-O0-NEXT:    pop r29