AMDGPU/GlobalISel: Fix assert on invalid cond code for llvm.amdgcn.icmp

[foad]

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

1108

Why not just return false? Is failing to select not good enough?

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

1108

This reproduces the current behavior. A few lit tests also happen to use this to sneak an undef past the IR passes

[arsenm]

ping

[foad]

This reproduces the current behavior.

You mean SelectionDAG behaviour? I'm not a huge fan of reproducing weird corner case behaviour, but I guess this is OK.

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

1120

Can you either put the new code here, or assert that getV_CMPOpcode succeeded here?

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

1120

getV_CMPOpcode can still fail based on the type (although I guess illegal i16 compares should have failed the verifier already)

[arsenm]

aa88b653927814052cdcb0ca22de52b043034568

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

bool AMDGPUInstructionSelector::selectIntrinsicIcmp(MachineInstr &I) const {
 
   if (MRI->getType(Dst).getSizeInBits() != STI.getWavefrontSize())
     return false;
 
   MachineBasicBlock *BB = I.getParent();
   const DebugLoc &DL = I.getDebugLoc();
   Register SrcReg = I.getOperand(2).getReg();
   unsigned Size = RBI.getSizeInBits(SrcReg, *MRI, TRI);
+
   auto Pred = static_cast<CmpInst::Predicate>(I.getOperand(4).getImm());
+  if (!ICmpInst::isIntPredicate(static_cast<ICmpInst::Predicate>(Pred))) {
+    MachineInstr *ICmp =
+        BuildMI(*BB, &I, DL, TII.get(AMDGPU::IMPLICIT_DEF), Dst);
+
+    if (!RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(),
+                                      *TRI.getBoolRC(), *MRI))
+      return false;
+    I.eraseFromParent();
+    return true;
+  }
 
   int Opcode = getV_CMPOpcode(Pred, Size);
   if (Opcode == -1)
     return false;
 
   MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode), Dst)
                            .add(I.getOperand(2))
                            .add(I.getOperand(3));
   RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(), *TRI.getBoolRC(),
                                *MRI);
   bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI);
   I.eraseFromParent();

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.icmp.ll

 ; GCN-NEXT:    v_cmp_ne_u32_e64 s0, 0x64, v2
 ; GCN-NEXT:    v_mov_b32_e32 v2, s0
 ; GCN-NEXT:    global_store_dword v[0:1], v2, off
 ; GCN-NEXT:    s_endpgm
   %result = call i32 @llvm.amdgcn.icmp.i32.i32(i32 %src, i32 100, i32 33)
   store i32 %result, i32 addrspace(1)* %out
   ret void
 }
+
+define amdgpu_ps void @test_intr_icmp_i32_invalid_cc(i32 addrspace(1)* %out, i32 %src) #1 {
+; GCN-LABEL: test_intr_icmp_i32_invalid_cc:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    global_store_dword v[0:1], v0, off
+; GCN-NEXT:    s_endpgm
+  %result = call i32 @llvm.amdgcn.icmp.i32.i32(i32 %src, i32 100, i32 9999)
+  store i32 %result, i32 addrspace(1)* %out
+  ret void
+}
+
 declare i64 @llvm.amdgcn.icmp.i64.i32(i32, i32, i32)
 declare i32 @llvm.amdgcn.icmp.i32.i32(i32, i32, i32)
 attributes #0 = { "target-features"="+wavefrontsize64" }
 attributes #1 = { "target-features"="+wavefrontsize32" }