AMDGPU: Convert AMDGPUResourceUsageAnalysis to a Module pass

[arsenm]

Summary

This is more precise in the face of indirect calls and aliases, still
assuming the call target is defined somewhere in the current module.

This sometimes changes the order the functions are printed, and also
changes the point where context errors are printed relative to
stdout. This also likely has negative consequences for compile time
and memory usage.

[sebastian-ne]

Thanks for doing this.
The code looks good to me, though for some reason the llpc graphics frontend is now missing metadata or crashes when trying to read metadata from the generated elf. I’m still debugging.

[sebastian-ne]

I think I found the problem and I’m a little surprised it currently works.
In the llpc pipeline, a module pass (PipelineStateClearer) writes pal metadata into the amdgpu.pal.metadata.msgpack metadata.
This metadata is read by the AMDGPUAsmPrinter, extended as functions are emitted and finally written out in AMDGPUTarget[…]Streamer::finish.

The reading of the metadata happens in AMDGPUAsmPrinter::emitStartOfAsmFile, which is called from AsmPrinter::doInitialization, which in turn is called when the pass manager is initialized.
So, the metadata is read at pass manager initialization, but it’s only written afterwards when running a pass, resulting in missing metadata in the output.

[arsenm]

In D117504#3261571, @sebastian-ne wrote:

I think I found the problem and I’m a little surprised it currently works.
In the llpc pipeline, a module pass (PipelineStateClearer) writes pal metadata into the amdgpu.pal.metadata.msgpack metadata.
This metadata is read by the AMDGPUAsmPrinter, extended as functions are emitted and finally written out in AMDGPUTarget[…]Streamer::finish.

The reading of the metadata happens in AMDGPUAsmPrinter::emitStartOfAsmFile, which is called from AsmPrinter::doInitialization, which in turn is called when the pass manager is initialized.
So, the metadata is read at pass manager initialization, but it’s only written afterwards when running a pass, resulting in missing metadata in the output.

So what is the takeaway from this? My initial thought is this that metadata is not intended to be used to share information between passes this way. I think we need to get indirect/alias calls working correctly, so should I just push the first patch and wait for you to resolve this issue?

[arsenm]

4622afa94c014dff814952b34ba5c9447a7c48c6

llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.h

 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPURESOURCEUSAGEANALYSIS_H
 #define LLVM_LIB_TARGET_AMDGPU_AMDGPURESOURCEUSAGEANALYSIS_H
 
 #include "llvm/Analysis/CallGraphSCCPass.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 
 namespace llvm {
 
-class GCNTargetMachine;
 class GCNSubtarget;
 class MachineFunction;
 class TargetMachine;
 
-struct AMDGPUResourceUsageAnalysis : public CallGraphSCCPass {
+struct AMDGPUResourceUsageAnalysis : public ModulePass {
   static char ID;
 
 public:
   // Track resource usage for callee functions.
   struct SIFunctionResourceInfo {
     // Track the number of explicitly used VGPRs. Special registers reserved at
     // the end are tracked separately.
     int32_t NumVGPR = 0;
struct SIFunctionResourceInfo {
     int32_t getTotalNumSGPRs(const GCNSubtarget &ST) const;
     // Total number of VGPRs is actually a combination of AGPR and VGPR
     // depending on architecture - and some alignment constraints
     int32_t getTotalNumVGPRs(const GCNSubtarget &ST, int32_t NumAGPR,
                              int32_t NumVGPR) const;
     int32_t getTotalNumVGPRs(const GCNSubtarget &ST) const;
   };
 
-  AMDGPUResourceUsageAnalysis() : CallGraphSCCPass(ID) {}
+  AMDGPUResourceUsageAnalysis() : ModulePass(ID) {}
 
-  bool runOnSCC(CallGraphSCC &SCC) override;
-
-  bool doInitialization(CallGraph &CG) override {
+  bool doInitialization(Module &M) override {
     CallGraphResourceInfo.clear();
-    return CallGraphSCCPass::doInitialization(CG);
+    return ModulePass::doInitialization(M);
   }
 
+  bool runOnModule(Module &M) override;
+
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<MachineModuleInfoWrapperPass>();
     AU.setPreservesAll();
   }
 
   const SIFunctionResourceInfo &getResourceInfo(const Function *F) const {
     auto Info = CallGraphResourceInfo.find(F);
     assert(Info != CallGraphResourceInfo.end() &&
            "Failed to find resource info for function");
     return Info->getSecond();
   }
 
-  const SIFunctionResourceInfo &getWorstCaseResourceInfo(const Module &M);
-
 private:
-  void computeWorstCaseModuleRegisterUsage(const Module &M);
-
-  SIFunctionResourceInfo analyzeResourceUsage(const MachineFunction &MF);
+  SIFunctionResourceInfo analyzeResourceUsage(const MachineFunction &MF,
+                                              const TargetMachine &TM) const;
+  void propagateIndirectCallRegisterUsage();
 
-  const GCNTargetMachine *TM = nullptr;
   DenseMap<const Function *, SIFunctionResourceInfo> CallGraphResourceInfo;
-  Optional<SIFunctionResourceInfo> ModuleWorstCaseInfo;
 };
 } // namespace llvm
 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPURESOURCEUSAGEANALYSIS_H

llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp

 /// hardware-entrypoints. Therefore the register usage of functions with
 /// indirect calls is estimated as the maximum of all non-entrypoint functions
 /// in the module.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPUResourceUsageAnalysis.h"
 #include "AMDGPU.h"
-#include "AMDGPUTargetMachine.h"
 #include "GCNSubtarget.h"
 #include "SIMachineFunctionInfo.h"
 #include "llvm/Analysis/CallGraph.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/GlobalAlias.h"
 #include "llvm/IR/GlobalValue.h"
 #include "llvm/Target/TargetMachine.h"
 
int32_t AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo::getTotalNumVGPRs(
   return std::max(ArgNumVGPR, ArgNumAGPR);
 }
 
 int32_t AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo::getTotalNumVGPRs(
     const GCNSubtarget &ST) const {
   return getTotalNumVGPRs(ST, NumAGPR, NumVGPR);
 }
 
-bool AMDGPUResourceUsageAnalysis::runOnSCC(CallGraphSCC &SCC) {
+bool AMDGPUResourceUsageAnalysis::runOnModule(Module &M) {
   auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
   if (!TPC)
     return false;
 
-  TM = static_cast<const GCNTargetMachine *>(&TPC->getTM<TargetMachine>());
+  MachineModuleInfo &MMI = getAnalysis<MachineModuleInfoWrapperPass>().getMMI();
+  const TargetMachine &TM = TPC->getTM<TargetMachine>();
+  bool HasIndirectCall = false;
 
-  for (CallGraphNode *I : SCC) {
-    Function *F = I->getFunction();
-    if (!F || F->isDeclaration())
+  for (Function &F : M) {
+    if (F.isDeclaration())
       continue;
 
-    MachineModuleInfo &MMI =
-        getAnalysis<MachineModuleInfoWrapperPass>().getMMI();
-    MachineFunction &MF = MMI.getOrCreateMachineFunction(*F);
+    MachineFunction *MF = MMI.getMachineFunction(F);
+    assert(MF && "function must have been generated already");
 
     auto CI = CallGraphResourceInfo.insert(
-        std::make_pair(&MF.getFunction(), SIFunctionResourceInfo()));
+        std::make_pair(&F, SIFunctionResourceInfo()));
     SIFunctionResourceInfo &Info = CI.first->second;
     assert(CI.second && "should only be called once per function");
-    Info = analyzeResourceUsage(MF);
+    Info = analyzeResourceUsage(*MF, TM);
+    HasIndirectCall |= Info.HasIndirectCall;
   }
 
+  if (HasIndirectCall)
+    propagateIndirectCallRegisterUsage();
+
   return false;
 }
 
 AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo
-AMDGPUResourceUsageAnalysis::analyzeResourceUsage(const MachineFunction &MF) {
+AMDGPUResourceUsageAnalysis::analyzeResourceUsage(
+    const MachineFunction &MF, const TargetMachine &TM) const {
   SIFunctionResourceInfo Info;
 
   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
   const MachineRegisterInfo &MRI = MF.getRegInfo();
   const SIInstrInfo *TII = ST.getInstrInfo();
   const SIRegisterInfo &TRI = TII->getRegisterInfo();
for (const MachineInstr &MI : MBB) {
           }
         }
 
         if (IsIndirect || I == CallGraphResourceInfo.end()) {
           CalleeFrameSize =
               std::max(CalleeFrameSize,
                        static_cast<uint64_t>(AssumedStackSizeForExternalCall));
 
-          const SIFunctionResourceInfo &WorstCase =
-              getWorstCaseResourceInfo(*MF.getFunction().getParent());
-          MaxSGPR = std::max(WorstCase.NumExplicitSGPR - 1, MaxSGPR);
-          MaxVGPR = std::max(WorstCase.NumVGPR - 1, MaxVGPR);
-          MaxAGPR = std::max(WorstCase.NumAGPR - 1, MaxAGPR);
-
           // Register usage of indirect calls gets handled later
           Info.UsesVCC = true;
-          Info.UsesFlatScratch |=
-              WorstCase.UsesFlatScratch && ST.hasFlatAddressSpace();
+          Info.UsesFlatScratch = ST.hasFlatAddressSpace();
           Info.HasDynamicallySizedStack = true;
           Info.HasIndirectCall = true;
         } else {
           // We force CodeGen to run in SCC order, so the callee's register
           // usage etc. should be the cumulative usage of all callees.
           MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
           MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
           MaxAGPR = std::max(I->second.NumAGPR - 1, MaxAGPR);
AMDGPUResourceUsageAnalysis::analyzeResourceUsage(
   Info.NumExplicitSGPR = MaxSGPR + 1;
   Info.NumVGPR = MaxVGPR + 1;
   Info.NumAGPR = MaxAGPR + 1;
   Info.PrivateSegmentSize += CalleeFrameSize;
 
   return Info;
 }
 
-const AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo &
-AMDGPUResourceUsageAnalysis::getWorstCaseResourceInfo(const Module &M) {
-  if (ModuleWorstCaseInfo)
-    return *ModuleWorstCaseInfo;
-
-  computeWorstCaseModuleRegisterUsage(M);
-  return *ModuleWorstCaseInfo;
-}
-
-/// Find the worst case register usage for all callable functions in the module,
-/// assuming all reachable functions are defined in the current module.
-void AMDGPUResourceUsageAnalysis::computeWorstCaseModuleRegisterUsage(
-    const Module &M) {
-  assert(!ModuleWorstCaseInfo);
-  ModuleWorstCaseInfo = SIFunctionResourceInfo();
-  ModuleWorstCaseInfo->UsesVCC = true;
-  ModuleWorstCaseInfo->HasDynamicallySizedStack = true;
-  ModuleWorstCaseInfo->HasRecursion = true;
-  ModuleWorstCaseInfo->HasIndirectCall = true;
-
-  for (const Function &F : M) {
-    if (F.isIntrinsic())
-      continue;
-
-    if (AMDGPU::isEntryFunctionCC(F.getCallingConv()))
-      continue;
-
-    const GCNSubtarget &ST = TM->getSubtarget<GCNSubtarget>(F);
-    const int32_t MaxVGPR = ST.getMaxNumVGPRs(F);
-    const int32_t MaxSGPR = ST.getMaxNumSGPRs(F);
-
-    ModuleWorstCaseInfo->NumVGPR =
-        std::max(ModuleWorstCaseInfo->NumVGPR, MaxVGPR);
-
-    if (ST.hasMAIInsts()) {
-      const int32_t MaxAGPR = ST.getMaxNumAGPRs(F);
-      ModuleWorstCaseInfo->NumAGPR =
-          std::max(ModuleWorstCaseInfo->NumAGPR, MaxAGPR);
-    }
+void AMDGPUResourceUsageAnalysis::propagateIndirectCallRegisterUsage() {
+  // Collect the maximum number of registers from non-hardware-entrypoints.
+  // All these functions are potential targets for indirect calls.
+  int32_t NonKernelMaxSGPRs = 0;
+  int32_t NonKernelMaxVGPRs = 0;
+  int32_t NonKernelMaxAGPRs = 0;
+
+  for (const auto &I : CallGraphResourceInfo) {
+    if (!AMDGPU::isEntryFunctionCC(I.getFirst()->getCallingConv())) {
+      auto &Info = I.getSecond();
+      NonKernelMaxSGPRs = std::max(NonKernelMaxSGPRs, Info.NumExplicitSGPR);
+      NonKernelMaxVGPRs = std::max(NonKernelMaxVGPRs, Info.NumVGPR);
+      NonKernelMaxAGPRs = std::max(NonKernelMaxAGPRs, Info.NumAGPR);
+    }
 
-    ModuleWorstCaseInfo->NumExplicitSGPR =
-        std::max(ModuleWorstCaseInfo->NumExplicitSGPR, MaxSGPR);
-
-    ModuleWorstCaseInfo->UsesFlatScratch |= ST.hasFlatAddressSpace();
+  // Add register usage for functions with indirect calls.
+  // For calls to unknown functions, we assume the maximum register usage of
+  // all non-hardware-entrypoints in the current module.
+  for (auto &I : CallGraphResourceInfo) {
+    auto &Info = I.getSecond();
+    if (Info.HasIndirectCall) {
+      Info.NumExplicitSGPR = std::max(Info.NumExplicitSGPR, NonKernelMaxSGPRs);
+      Info.NumVGPR = std::max(Info.NumVGPR, NonKernelMaxVGPRs);
+      Info.NumAGPR = std::max(Info.NumAGPR, NonKernelMaxAGPRs);
+    }
   }
 }

llvm/test/CodeGen/AMDGPU/agpr-register-count.ll

 bb:
   call void @func_32_agprs() #0
   ret void
 }
 
 declare void @undef_func()
 
 ; GCN-LABEL: {{^}}kernel_call_undef_func:
-; GFX908: .amdhsa_next_free_vgpr 128
-; GFX90A: .amdhsa_next_free_vgpr 512
-; GFX90A: .amdhsa_accum_offset 256
+; GFX908: .amdhsa_next_free_vgpr 32
+; GFX90A: .amdhsa_next_free_vgpr 64
+; GFX90A: .amdhsa_accum_offset 32
 ; GCN908: NumVgprs: 128
 ; GCN908: NumAgprs: 128
 ; GCN90A: NumVgprs: 256
 ; GCN90A: NumAgprs: 256
-; GFX908: TotalNumVgprs: 128
-; GFX90A: TotalNumVgprs: 512
-; GFX908: VGPRBlocks: 31
-; GFX90A: VGPRBlocks: 63
-; GFX908: NumVGPRsForWavesPerEU: 128
-; GFX90A: NumVGPRsForWavesPerEU: 512
-; GFX90A: AccumOffset: 256
-; GFX908: Occupancy: 2
-; GFX90A: Occupancy: 1
-; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63
+; GFX908: TotalNumVgprs: 32
+; GFX90A: TotalNumVgprs: 64
+; GFX908: VGPRBlocks: 7
+; GFX90A: VGPRBlocks: 7
+; GFX908: NumVGPRsForWavesPerEU: 32
+; GFX90A: NumVGPRsForWavesPerEU: 64
+; GFX90A: AccumOffset: 32
+; GFX908: Occupancy: 8
+; GFX90A: Occupancy: 8
+; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 7
 define amdgpu_kernel void @kernel_call_undef_func() #0 {
 bb:
   call void @undef_func()
   ret void
 }
 
 attributes #0 = { nounwind noinline "amdgpu-flat-work-group-size"="1,512" }

llvm/test/CodeGen/AMDGPU/amdpal-callable.ll

define amdgpu_gfx float @simple_lds_recurse(float %arg0) #0 {
   %res = call amdgpu_gfx float @simple_lds_recurse(float %val)
   ret float %res
 }
 
 attributes #0 = { nounwind }
 
 ; GCN: amdpal.pipelines:
 ; GCN-NEXT:  - .registers:
-; SDAG-NEXT:      0x2e12 (COMPUTE_PGM_RSRC1): 0xaf03cf{{$}}
-; GISEL-NEXT:      0x2e12 (COMPUTE_PGM_RSRC1): 0xaf03cf{{$}}
+; SDAG-NEXT:      0x2e12 (COMPUTE_PGM_RSRC1): 0xaf01ca{{$}}
+; GISEL-NEXT:      0x2e12 (COMPUTE_PGM_RSRC1): 0xaf01ce{{$}}
 ; GCN-NEXT:      0x2e13 (COMPUTE_PGM_RSRC2): 0x8001{{$}}
 ; GCN-NEXT:    .shader_functions:
 ; GCN-NEXT:      dynamic_stack:
 ; GCN-NEXT:        .lds_size:       0{{$}}
 ; GCN-NEXT:        .sgpr_count:     0x28{{$}}
 ; GCN-NEXT:        .stack_frame_size_in_bytes: 0x10{{$}}
 ; SDAG-NEXT:        .vgpr_count:     0x2{{$}}
 ; GISEL-NEXT:        .vgpr_count:     0x3{{$}}

 ; GCN-NEXT:        .vgpr_count:     0x1{{$}}
 ; GCN-NEXT:      no_stack_call:
 ; GCN-NEXT:        .lds_size:       0{{$}}
 ; GCN-NEXT:        .sgpr_count:     0x26{{$}}
 ; GCN-NEXT:        .stack_frame_size_in_bytes: 0{{$}}
 ; GCN-NEXT:        .vgpr_count:     0x2{{$}}
 ; GCN-NEXT:      no_stack_extern_call:
 ; GCN-NEXT:        .lds_size:       0{{$}}
-; GFX8-NEXT:        .sgpr_count:     0x68{{$}}
-; GFX9-NEXT:        .sgpr_count:     0x6c{{$}}
+; GFX8-NEXT:        .sgpr_count:     0x28{{$}}
+; GFX9-NEXT:        .sgpr_count:     0x2c{{$}}
 ; GCN-NEXT:        .stack_frame_size_in_bytes: 0x10{{$}}
-; GCN-NEXT:        .vgpr_count:     0x40{{$}}
+; SDAG-NEXT:        .vgpr_count:     0x2b{{$}}
+; GISEL-NEXT:        .vgpr_count:    0x34{{$}}
 ; GCN-NEXT:      no_stack_extern_call_many_args:
 ; GCN-NEXT:        .lds_size:       0{{$}}
-; GFX8-NEXT:        .sgpr_count:     0x68{{$}}
-; GFX9-NEXT:        .sgpr_count:     0x6c{{$}}
+; GFX8-NEXT:        .sgpr_count:     0x28{{$}}
+; GFX9-NEXT:        .sgpr_count:     0x2c{{$}}
 ; GCN-NEXT:        .stack_frame_size_in_bytes: 0x90{{$}}
-; SDAG-NEXT:        .vgpr_count:     0x40{{$}}
-; GISEL-NEXT:        .vgpr_count:     0x40{{$}}
+; SDAG-NEXT:        .vgpr_count:     0x2b{{$}}
+; GISEL-NEXT:        .vgpr_count:     0x34{{$}}
 ; GCN-NEXT:      no_stack_indirect_call:
 ; GCN-NEXT:        .lds_size:       0{{$}}
-; GFX8-NEXT:        .sgpr_count:     0x68{{$}}
-; GFX9-NEXT:        .sgpr_count:     0x6c{{$}}
+; GFX8-NEXT:        .sgpr_count:     0x28{{$}}
+; GFX9-NEXT:        .sgpr_count:     0x2c{{$}}
 ; GCN-NEXT:        .stack_frame_size_in_bytes: 0x10{{$}}
-; SDAG-NEXT:        .vgpr_count:     0x40{{$}}
-; GISEL-NEXT:        .vgpr_count:     0x40{{$}}
+; SDAG-NEXT:        .vgpr_count:     0x2b{{$}}
+; GISEL-NEXT:        .vgpr_count:     0x34{{$}}
 ; GCN-NEXT:      simple_lds:
 ; GCN-NEXT:        .lds_size:       0x100{{$}}
 ; GCN-NEXT:        .sgpr_count:     0x20{{$}}
 ; GCN-NEXT:        .stack_frame_size_in_bytes: 0{{$}}
 ; GCN-NEXT:        .vgpr_count:     0x1{{$}}
 ; GCN-NEXT:      simple_lds_recurse:
 ; GCN-NEXT:        .lds_size:       0x100{{$}}
 ; GCN-NEXT:        .sgpr_count:     0x26{{$}}
 ; GCN-NEXT:        .stack_frame_size_in_bytes: 0x10{{$}}
 ; GCN-NEXT:        .vgpr_count:     0x29{{$}}
 ; GCN-NEXT:      simple_stack:
 ; GCN-NEXT:        .lds_size:       0{{$}}
 ; GCN-NEXT:        .sgpr_count:     0x21{{$}}
 ; GCN-NEXT:        .stack_frame_size_in_bytes: 0x14{{$}}
 ; GCN-NEXT:        .vgpr_count:     0x2{{$}}
 ; GCN-NEXT:      simple_stack_call:
 ; GCN-NEXT:        .lds_size:       0{{$}}
 ; GCN-NEXT:        .sgpr_count:     0x26{{$}}
 ; GCN-NEXT:        .stack_frame_size_in_bytes: 0x20{{$}}
 ; GCN-NEXT:        .vgpr_count:     0x3{{$}}
 ; GCN-NEXT:      simple_stack_extern_call:
 ; GCN-NEXT:        .lds_size:       0{{$}}
-; GFX8-NEXT:        .sgpr_count:     0x68{{$}}
-; GFX9-NEXT:        .sgpr_count:     0x6c{{$}}
+; GFX8-NEXT:        .sgpr_count:     0x28{{$}}
+; GFX9-NEXT:        .sgpr_count:     0x2c{{$}}
 ; GCN-NEXT:        .stack_frame_size_in_bytes: 0x20{{$}}
-; GCN-NEXT:        .vgpr_count:     0x40{{$}}
+; SDAG-NEXT:        .vgpr_count:     0x2b{{$}}
+; GISEL-NEXT:       .vgpr_count:     0x34{{$}}
 ; GCN-NEXT:      simple_stack_indirect_call:
 ; GCN-NEXT:        .lds_size:       0{{$}}
-; GFX8-NEXT:        .sgpr_count:     0x68{{$}}
-; GFX9-NEXT:        .sgpr_count:     0x6c{{$}}
+; GFX8-NEXT:        .sgpr_count:     0x28{{$}}
+; GFX9-NEXT:        .sgpr_count:     0x2c{{$}}
 ; GCN-NEXT:        .stack_frame_size_in_bytes: 0x20{{$}}
-; SDAG-NEXT:        .vgpr_count:     0x40{{$}}
-; GISEL-NEXT:        .vgpr_count:     0x40{{$}}
+; SDAG-NEXT:        .vgpr_count:     0x2b{{$}}
+; GISEL-NEXT:        .vgpr_count:     0x34{{$}}
 ; GCN-NEXT:      simple_stack_recurse:
 ; GCN-NEXT:        .lds_size:       0{{$}}
 ; GCN-NEXT:        .sgpr_count:     0x26{{$}}
 ; GCN-NEXT:        .stack_frame_size_in_bytes: 0x20{{$}}
 ; GCN-NEXT:        .vgpr_count:     0x2a{{$}}
 ; GCN-NEXT: ...

llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll

define amdgpu_kernel void @f512() #512 {
   call void @foo()
   call void @use256vgprs()
   ret void
 }
 attributes #512 = { nounwind "amdgpu-flat-work-group-size"="512,512" }
 
 ; GCN-LABEL: {{^}}f1024:
 ; GFX9: NumVgprs: 64
-; GFX90A: NumVgprs: 128
-; GFX90A: NumAgprs: 128
-; GFX90A: TotalNumVgprs: 256
+; GFX90A: NumAgprs: 64
+; GFX90A: TotalNumVgprs: 128
 ; GFX10WGP-WAVE32: NumVgprs: 128
 ; GFX10WGP-WAVE64: NumVgprs: 128
 ; GFX10CU-WAVE32: NumVgprs: 64
 ; GFX10CU-WAVE64: NumVgprs: 64
 define amdgpu_kernel void @f1024() #1024 {
   call void @foo()
   call void @use256vgprs()
   ret void
 }
 
 attributes #1024 = { nounwind "amdgpu-flat-work-group-size"="1024,1024" }
 
 declare void @foo()

llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll

 ; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefixes=ALL,GFX908 %s
 ; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=ALL,GFX90A %s
 
 ; CallGraphAnalysis, which CodeGenSCC order depends on, does not look
 ; through aliases. If GlobalOpt is never run, we do not see direct
 ; calls,
 
 @alias = hidden alias void (), void ()* @aliasee_default
 
 ; ALL-LABEL: {{^}}kernel:
-; GFX908: .amdhsa_next_free_vgpr 64
-; GFX908-NEXT: .amdhsa_next_free_sgpr 102
+; GFX908: .amdhsa_next_free_vgpr 41
+; GFX908-NEXT: .amdhsa_next_free_sgpr 33
 
-; GFX90A: .amdhsa_next_free_vgpr 256
-; GFX90A-NEXT: .amdhsa_next_free_sgpr 102
-; GFX90A-NEXT: .amdhsa_accum_offset 128
+; GFX90A: .amdhsa_next_free_vgpr 71
+; GFX90A-NEXT: .amdhsa_next_free_sgpr 33
+; GFX90A-NEXT: .amdhsa_accum_offset 44
 define amdgpu_kernel void @kernel() #0 {
 bb:
   call void @alias() #2
   ret void
 }
 
 define internal void @aliasee_default() #1 {
 bb:
   call void asm sideeffect "; clobber a26 ", "~{a26}"()
   ret void
 }
 
 attributes #0 = { noinline norecurse nounwind optnone }
 attributes #1 = { noinline norecurse nounwind readnone willreturn }
 attributes #2 = { nounwind readnone willreturn }

llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll

 ; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
 
 ; CallGraphAnalysis, which CodeGenSCC order depends on, does not look
 ; through aliases. If GlobalOpt is never run, we do not see direct
 ; calls,
 
 @alias0 = hidden alias void (), void ()* @aliasee_default_vgpr64_sgpr102
 
 ; CHECK-LABEL: {{^}}kernel0:
-; CHECK: .amdhsa_next_free_vgpr 64
-; CHECK-NEXT: .amdhsa_next_free_sgpr 102
+; CHECK: .amdhsa_next_free_vgpr 53
+; CHECK-NEXT: .amdhsa_next_free_sgpr 33
 define amdgpu_kernel void @kernel0() #0 {
 bb:
   call void @alias0() #2
   ret void
 }
 
 define internal void @aliasee_default_vgpr64_sgpr102() #1 {
 bb:
   call void asm sideeffect "; clobber v52 ", "~{v52}"()
   ret void
 }
 
 attributes #0 = { noinline norecurse nounwind optnone }
 attributes #1 = { noinline norecurse nounwind readnone willreturn }
 attributes #2 = { nounwind readnone willreturn }

llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll

 ; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
 
 ; CallGraphAnalysis, which CodeGenSCC order depends on, does not look
 ; through aliases. If GlobalOpt is never run, we do not see direct
 ; calls,
 
 @alias1 = hidden alias void (), void ()* @aliasee_vgpr32_sgpr76
 
 ; The parent kernel has a higher VGPR usage than the possible callees.
 
 ; CHECK-LABEL: {{^}}kernel1:
 ; CHECK: .amdhsa_next_free_vgpr 42
-; CHECK-NEXT: .amdhsa_next_free_sgpr 74
+; CHECK-NEXT: .amdhsa_next_free_sgpr 33
 define amdgpu_kernel void @kernel1() #0 {
 bb:
   call void asm sideeffect "; clobber v40 ", "~{v40}"()
   call void @alias1() #2
   ret void
 }
 
 define internal void @aliasee_vgpr32_sgpr76() #1 {
 bb:
   call void asm sideeffect "; clobber v26 ", "~{v26}"()
   ret void
 }
 
 attributes #0 = { noinline norecurse nounwind optnone }
 attributes #1 = { noinline norecurse nounwind readnone willreturn "amdgpu-waves-per-eu"="8,10" }
 attributes #2 = { nounwind readnone willreturn }

llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll

 ; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
 
 ; CallGraphAnalysis, which CodeGenSCC order depends on, does not look
 ; through aliases. If GlobalOpt is never run, we do not see direct
 ; calls,
 
 @alias2 = hidden alias void (), void()* @aliasee_vgpr64_sgpr102
 
 ; CHECK-LABEL: {{^}}kernel2:
-; CHECK: .amdhsa_next_free_vgpr 64
-; CHECK-NEXT: .amdhsa_next_free_sgpr 102
+; CHECK: .amdhsa_next_free_vgpr 53
+; CHECK-NEXT: .amdhsa_next_free_sgpr 33
 define amdgpu_kernel void @kernel2() #0 {
 bb:
   call void @alias2() #2
   ret void
 }
 
 define internal void @aliasee_vgpr64_sgpr102() #1 {
 bb:
   call void asm sideeffect "; clobber v52 ", "~{v52}"()
   ret void
 }
 
 attributes #0 = { noinline norecurse nounwind optnone }
 attributes #1 = { noinline norecurse nounwind readnone willreturn "amdgpu-waves-per-eu"="4,10" }
 attributes #2 = { nounwind readnone willreturn }

llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll

 ; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
 
 ; CallGraphAnalysis, which CodeGenSCC order depends on, does not look
 ; through aliases. If GlobalOpt is never run, we do not see direct
 ; calls,
 
 @alias3 = hidden alias void (), void ()* @aliasee_vgpr256_sgpr102
 
 ; CHECK-LABEL: {{^}}kernel3:
-; CHECK: .amdhsa_next_free_vgpr 256
-; CHECK-NEXT: .amdhsa_next_free_sgpr 102
+; CHECK: .amdhsa_next_free_vgpr 253
+; CHECK-NEXT: .amdhsa_next_free_sgpr 33
 define amdgpu_kernel void @kernel3() #0 {
 bb:
   call void @alias3() #2
   ret void
 }
 
 define internal void @aliasee_vgpr256_sgpr102() #1 {
 bb:
   call void asm sideeffect "; clobber v252 ", "~{v252}"()
   ret void
 }
 
 attributes #0 = { noinline norecurse nounwind optnone }
 attributes #1 = { noinline norecurse nounwind readnone willreturn "amdgpu-flat-work-group-size"="1,256" "amdgpu-waves-per-eu"="1,1" }
 attributes #2 = { nounwind readnone willreturn }

llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll

 define amdgpu_kernel void @usage_direct_recursion(i32 %n) #0 {
   call void @direct_recursion_use_stack(i32 %n)
   ret void
 }
 
 ; Make sure there's no assert when a sgpr96 is used.
 ; GCN-LABEL: {{^}}count_use_sgpr96_external_call
 ; GCN: ; sgpr96 s[{{[0-9]+}}:{{[0-9]+}}]
-; CI: NumSgprs: 104
-; VI-NOBUG: NumSgprs: 108
+; CI: NumSgprs: 84
+; VI-NOBUG: NumSgprs: 86
 ; VI-BUG: NumSgprs: 96
-; GCN: NumVgprs: 64
+; GCN: NumVgprs: 50
 define amdgpu_kernel void @count_use_sgpr96_external_call()  {
 entry:
   tail call void asm sideeffect "; sgpr96 $0", "s"(<3 x i32> <i32 10, i32 11, i32 12>) #1
   call void @external()
   ret void
 }
 
 ; Make sure there's no assert when a sgpr160 is used.
 ; GCN-LABEL: {{^}}count_use_sgpr160_external_call
 ; GCN: ; sgpr160 s[{{[0-9]+}}:{{[0-9]+}}]
-; CI: NumSgprs: 104
-; VI-NOBUG: NumSgprs: 108
+; CI: NumSgprs: 84
+; VI-NOBUG: NumSgprs: 86
 ; VI-BUG: NumSgprs: 96
-; GCN: NumVgprs: 64
+; GCN: NumVgprs: 50
 define amdgpu_kernel void @count_use_sgpr160_external_call()  {
 entry:
   tail call void asm sideeffect "; sgpr160 $0", "s"(<5 x i32> <i32 10, i32 11, i32 12, i32 13, i32 14>) #1
   call void @external()
   ret void
 }
 
 ; Make sure there's no assert when a vgpr160 is used.
 ; GCN-LABEL: {{^}}count_use_vgpr160_external_call
 ; GCN: ; vgpr160 v[{{[0-9]+}}:{{[0-9]+}}]
-; CI: NumSgprs: 104
-; VI-NOBUG: NumSgprs: 108
+; CI: NumSgprs: 84
+; VI-NOBUG: NumSgprs: 86
 ; VI-BUG: NumSgprs: 96
-; GCN: NumVgprs: 64
+; GCN: NumVgprs: 50
 define amdgpu_kernel void @count_use_vgpr160_external_call()  {
 entry:
   tail call void asm sideeffect "; vgpr160 $0", "v"(<5 x i32> <i32 10, i32 11, i32 12, i32 13, i32 14>) #1
   call void @external()
   ret void
 }
 
 attributes #0 = { nounwind noinline norecurse }
 attributes #1 = { nounwind noinline norecurse }
 attributes #2 = { nounwind noinline }

llvm/test/CodeGen/AMDGPU/indirect-call.ll

 ; GCN-NEXT:     amd_code_version_major = 1
 ; GCN-NEXT:     amd_code_version_minor = 2
 ; GCN-NEXT:     amd_machine_kind = 1
 ; GCN-NEXT:     amd_machine_version_major = 7
 ; GCN-NEXT:     amd_machine_version_minor = 0
 ; GCN-NEXT:     amd_machine_version_stepping = 0
 ; GCN-NEXT:     kernel_code_entry_byte_offset = 256
 ; GCN-NEXT:     kernel_code_prefetch_byte_size = 0
-; GCN-NEXT:     granulated_workitem_vgpr_count = 15
-; GCN-NEXT:     granulated_wavefront_sgpr_count = 12
+; GCN-NEXT:     granulated_workitem_vgpr_count = 10
+; GCN-NEXT:     granulated_wavefront_sgpr_count = 8
 ; GCN-NEXT:     priority = 0
 ; GCN-NEXT:     float_mode = 240
 ; GCN-NEXT:     priv = 0
 ; GCN-NEXT:     enable_dx10_clamp = 1
 ; GCN-NEXT:     debug_mode = 0
 ; GCN-NEXT:     enable_ieee_mode = 1
 ; GCN-NEXT:     enable_wgp_mode = 0
 ; GCN-NEXT:     enable_mem_ordered = 0

 ; GCN-NEXT:     is_dynamic_callstack = 1
 ; GCN-NEXT:     is_debug_enabled = 0
 ; GCN-NEXT:     is_xnack_enabled = 0
 ; GCN-NEXT:     workitem_private_segment_byte_size = 16384
 ; GCN-NEXT:     workgroup_group_segment_byte_size = 0
 ; GCN-NEXT:     gds_segment_byte_size = 0
 ; GCN-NEXT:     kernarg_segment_byte_size = 64
 ; GCN-NEXT:     workgroup_fbarrier_count = 0
-; GCN-NEXT:     wavefront_sgpr_count = 104
-; GCN-NEXT:     workitem_vgpr_count = 64
+; GCN-NEXT:     wavefront_sgpr_count = 68
+; GCN-NEXT:     workitem_vgpr_count = 42
 ; GCN-NEXT:     reserved_vgpr_first = 0
 ; GCN-NEXT:     reserved_vgpr_count = 0
 ; GCN-NEXT:     reserved_sgpr_first = 0
 ; GCN-NEXT:     reserved_sgpr_count = 0
 ; GCN-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
 ; GCN-NEXT:     debug_private_segment_buffer_sgpr = 0
 ; GCN-NEXT:     kernarg_segment_alignment = 4
 ; GCN-NEXT:     group_segment_alignment = 4

 ; GISEL-NEXT:     amd_code_version_major = 1
 ; GISEL-NEXT:     amd_code_version_minor = 2
 ; GISEL-NEXT:     amd_machine_kind = 1
 ; GISEL-NEXT:     amd_machine_version_major = 7
 ; GISEL-NEXT:     amd_machine_version_minor = 0
 ; GISEL-NEXT:     amd_machine_version_stepping = 0
 ; GISEL-NEXT:     kernel_code_entry_byte_offset = 256
 ; GISEL-NEXT:     kernel_code_prefetch_byte_size = 0
-; GISEL-NEXT:     granulated_workitem_vgpr_count = 15
-; GISEL-NEXT:     granulated_wavefront_sgpr_count = 12
+; GISEL-NEXT:     granulated_workitem_vgpr_count = 10
+; GISEL-NEXT:     granulated_wavefront_sgpr_count = 8
 ; GISEL-NEXT:     priority = 0
 ; GISEL-NEXT:     float_mode = 240
 ; GISEL-NEXT:     priv = 0
 ; GISEL-NEXT:     enable_dx10_clamp = 1
 ; GISEL-NEXT:     debug_mode = 0
 ; GISEL-NEXT:     enable_ieee_mode = 1
 ; GISEL-NEXT:     enable_wgp_mode = 0
 ; GISEL-NEXT:     enable_mem_ordered = 0

 ; GISEL-NEXT:     is_dynamic_callstack = 1
 ; GISEL-NEXT:     is_debug_enabled = 0
 ; GISEL-NEXT:     is_xnack_enabled = 0
 ; GISEL-NEXT:     workitem_private_segment_byte_size = 16384
 ; GISEL-NEXT:     workgroup_group_segment_byte_size = 0
 ; GISEL-NEXT:     gds_segment_byte_size = 0
 ; GISEL-NEXT:     kernarg_segment_byte_size = 64
 ; GISEL-NEXT:     workgroup_fbarrier_count = 0
-; GISEL-NEXT:     wavefront_sgpr_count = 104
-; GISEL-NEXT:     workitem_vgpr_count = 64
+; GISEL-NEXT:     wavefront_sgpr_count = 68
+; GISEL-NEXT:     workitem_vgpr_count = 42
 ; GISEL-NEXT:     reserved_vgpr_first = 0
 ; GISEL-NEXT:     reserved_vgpr_count = 0
 ; GISEL-NEXT:     reserved_sgpr_first = 0
 ; GISEL-NEXT:     reserved_sgpr_count = 0
 ; GISEL-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
 ; GISEL-NEXT:     debug_private_segment_buffer_sgpr = 0
 ; GISEL-NEXT:     kernarg_segment_alignment = 4
 ; GISEL-NEXT:     group_segment_alignment = 4

 ; GCN-NEXT:     amd_code_version_major = 1
 ; GCN-NEXT:     amd_code_version_minor = 2
 ; GCN-NEXT:     amd_machine_kind = 1
 ; GCN-NEXT:     amd_machine_version_major = 7
 ; GCN-NEXT:     amd_machine_version_minor = 0
 ; GCN-NEXT:     amd_machine_version_stepping = 0
 ; GCN-NEXT:     kernel_code_entry_byte_offset = 256
 ; GCN-NEXT:     kernel_code_prefetch_byte_size = 0
-; GCN-NEXT:     granulated_workitem_vgpr_count = 15
-; GCN-NEXT:     granulated_wavefront_sgpr_count = 12
+; GCN-NEXT:     granulated_workitem_vgpr_count = 10
+; GCN-NEXT:     granulated_wavefront_sgpr_count = 8
 ; GCN-NEXT:     priority = 0
 ; GCN-NEXT:     float_mode = 240
 ; GCN-NEXT:     priv = 0
 ; GCN-NEXT:     enable_dx10_clamp = 1
 ; GCN-NEXT:     debug_mode = 0
 ; GCN-NEXT:     enable_ieee_mode = 1
 ; GCN-NEXT:     enable_wgp_mode = 0
 ; GCN-NEXT:     enable_mem_ordered = 0

 ; GCN-NEXT:     is_dynamic_callstack = 1
 ; GCN-NEXT:     is_debug_enabled = 0
 ; GCN-NEXT:     is_xnack_enabled = 0
 ; GCN-NEXT:     workitem_private_segment_byte_size = 16384
 ; GCN-NEXT:     workgroup_group_segment_byte_size = 0
 ; GCN-NEXT:     gds_segment_byte_size = 0
 ; GCN-NEXT:     kernarg_segment_byte_size = 64
 ; GCN-NEXT:     workgroup_fbarrier_count = 0
-; GCN-NEXT:     wavefront_sgpr_count = 104
-; GCN-NEXT:     workitem_vgpr_count = 64
+; GCN-NEXT:     wavefront_sgpr_count = 68
+; GCN-NEXT:     workitem_vgpr_count = 42
 ; GCN-NEXT:     reserved_vgpr_first = 0
 ; GCN-NEXT:     reserved_vgpr_count = 0
 ; GCN-NEXT:     reserved_sgpr_first = 0
 ; GCN-NEXT:     reserved_sgpr_count = 0
 ; GCN-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
 ; GCN-NEXT:     debug_private_segment_buffer_sgpr = 0
 ; GCN-NEXT:     kernarg_segment_alignment = 4
 ; GCN-NEXT:     group_segment_alignment = 4

 ; GISEL-NEXT:     amd_code_version_major = 1
 ; GISEL-NEXT:     amd_code_version_minor = 2
 ; GISEL-NEXT:     amd_machine_kind = 1
 ; GISEL-NEXT:     amd_machine_version_major = 7
 ; GISEL-NEXT:     amd_machine_version_minor = 0
 ; GISEL-NEXT:     amd_machine_version_stepping = 0
 ; GISEL-NEXT:     kernel_code_entry_byte_offset = 256
 ; GISEL-NEXT:     kernel_code_prefetch_byte_size = 0
-; GISEL-NEXT:     granulated_workitem_vgpr_count = 15
-; GISEL-NEXT:     granulated_wavefront_sgpr_count = 12
+; GISEL-NEXT:     granulated_workitem_vgpr_count = 10
+; GISEL-NEXT:     granulated_wavefront_sgpr_count = 8
 ; GISEL-NEXT:     priority = 0
 ; GISEL-NEXT:     float_mode = 240
 ; GISEL-NEXT:     priv = 0
 ; GISEL-NEXT:     enable_dx10_clamp = 1
 ; GISEL-NEXT:     debug_mode = 0
 ; GISEL-NEXT:     enable_ieee_mode = 1
 ; GISEL-NEXT:     enable_wgp_mode = 0
 ; GISEL-NEXT:     enable_mem_ordered = 0

 ; GISEL-NEXT:     is_dynamic_callstack = 1
 ; GISEL-NEXT:     is_debug_enabled = 0
 ; GISEL-NEXT:     is_xnack_enabled = 0
 ; GISEL-NEXT:     workitem_private_segment_byte_size = 16384
 ; GISEL-NEXT:     workgroup_group_segment_byte_size = 0
 ; GISEL-NEXT:     gds_segment_byte_size = 0
 ; GISEL-NEXT:     kernarg_segment_byte_size = 64
 ; GISEL-NEXT:     workgroup_fbarrier_count = 0
-; GISEL-NEXT:     wavefront_sgpr_count = 104
-; GISEL-NEXT:     workitem_vgpr_count = 64
+; GISEL-NEXT:     wavefront_sgpr_count = 68
+; GISEL-NEXT:     workitem_vgpr_count = 42
 ; GISEL-NEXT:     reserved_vgpr_first = 0
 ; GISEL-NEXT:     reserved_vgpr_count = 0
 ; GISEL-NEXT:     reserved_sgpr_first = 0
 ; GISEL-NEXT:     reserved_sgpr_count = 0
 ; GISEL-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
 ; GISEL-NEXT:     debug_private_segment_buffer_sgpr = 0
 ; GISEL-NEXT:     kernarg_segment_alignment = 4
 ; GISEL-NEXT:     group_segment_alignment = 4

llvm/test/CodeGen/AMDGPU/ipra.ll

 define void @func_call_tail_call() #1 {
   %vgpr = load volatile i32, i32 addrspace(1)* undef
   tail call void @func()
   store volatile i32 %vgpr, i32 addrspace(1)* undef
   tail call void @func()
   ret void
 }
 
+; GCN-LABEL: {{^}}void_func_void:
 define void @void_func_void() noinline {
   ret void
 }
 
 ; Make sure we don't get save/restore of FP between calls.
 ; GCN-LABEL: {{^}}test_funcx2:
 ; GCN-NOT: s5
 ; GCN-NOT: s32
 define void @test_funcx2() #0 {
   call void @void_func_void()
   call void @void_func_void()
   ret void
 }
 
+; GCN-LABEL: {{^}}wombat:
 define weak amdgpu_kernel void @wombat(i32* %arg, i32* %arg2) {
 bb:
   call void @hoge() #0
   ret void
 }
 
 ; Make sure we save/restore the return address around the call.
 ; Function Attrs: norecurse

llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

 ; GCN-O0-NEXT:        SI insert wait instructions
 ; GCN-O0-NEXT:        Insert required mode register values
 ; GCN-O0-NEXT:        MachineDominator Tree Construction
 ; GCN-O0-NEXT:        SI Final Branch Preparation
 ; GCN-O0-NEXT:        Post RA hazard recognizer
 ; GCN-O0-NEXT:        Branch relaxation pass
 ; GCN-O0-NEXT:        Register Usage Information Collector Pass
 ; GCN-O0-NEXT:        Live DEBUG_VALUE analysis
-; GCN-O0-NEXT:      Function register usage analysis
-; GCN-O0-NEXT:      FunctionPass Manager
-; GCN-O0-NEXT:        Lazy Machine Block Frequency Analysis
-; GCN-O0-NEXT:        Machine Optimization Remark Emitter
-; GCN-O0-NEXT:        AMDGPU Assembly Printer
-; GCN-O0-NEXT:        Free MachineFunction
+; GCN-O0-NEXT:    Function register usage analysis
+; GCN-O0-NEXT:    FunctionPass Manager
+; GCN-O0-NEXT:      Lazy Machine Block Frequency Analysis
+; GCN-O0-NEXT:      Machine Optimization Remark Emitter
+; GCN-O0-NEXT:      AMDGPU Assembly Printer
+; GCN-O0-NEXT:      Free MachineFunction
 ; GCN-O0-NEXT:Pass Arguments:  -domtree
 ; GCN-O0-NEXT:  FunctionPass Manager
 ; GCN-O0-NEXT:    Dominator Tree Construction
 
 ; GCN-O1:Target Library Information
 ; GCN-O1-NEXT:Target Pass Configuration
 ; GCN-O1-NEXT:Machine Module Information
 ; GCN-O1-NEXT:Target Transform Information

 ; GCN-O1-NEXT:        SI Insert Hard Clauses
 ; GCN-O1-NEXT:        MachineDominator Tree Construction
 ; GCN-O1-NEXT:        SI Final Branch Preparation
 ; GCN-O1-NEXT:        SI peephole optimizations
 ; GCN-O1-NEXT:        Post RA hazard recognizer
 ; GCN-O1-NEXT:        Branch relaxation pass
 ; GCN-O1-NEXT:        Register Usage Information Collector Pass
 ; GCN-O1-NEXT:        Live DEBUG_VALUE analysis
-; GCN-O1-NEXT:      Function register usage analysis
-; GCN-O1-NEXT:      FunctionPass Manager
-; GCN-O1-NEXT:        Lazy Machine Block Frequency Analysis
-; GCN-O1-NEXT:        Machine Optimization Remark Emitter
-; GCN-O1-NEXT:        AMDGPU Assembly Printer
-; GCN-O1-NEXT:        Free MachineFunction
+; GCN-O1-NEXT:    Function register usage analysis
+; GCN-O1-NEXT:    FunctionPass Manager
+; GCN-O1-NEXT:      Lazy Machine Block Frequency Analysis
+; GCN-O1-NEXT:      Machine Optimization Remark Emitter
+; GCN-O1-NEXT:      AMDGPU Assembly Printer
+; GCN-O1-NEXT:      Free MachineFunction
 ; GCN-O1-NEXT:Pass Arguments:  -domtree
 ; GCN-O1-NEXT:  FunctionPass Manager
 ; GCN-O1-NEXT:    Dominator Tree Construction
 
 ; GCN-O1-OPTS:Target Library Information
 ; GCN-O1-OPTS-NEXT:Target Pass Configuration
 ; GCN-O1-OPTS-NEXT:Machine Module Information
 ; GCN-O1-OPTS-NEXT:Target Transform Information

 ; GCN-O1-OPTS-NEXT:        SI Insert Hard Clauses
 ; GCN-O1-OPTS-NEXT:        MachineDominator Tree Construction
 ; GCN-O1-OPTS-NEXT:        SI Final Branch Preparation
 ; GCN-O1-OPTS-NEXT:        SI peephole optimizations
 ; GCN-O1-OPTS-NEXT:        Post RA hazard recognizer
 ; GCN-O1-OPTS-NEXT:        Branch relaxation pass
 ; GCN-O1-OPTS-NEXT:        Register Usage Information Collector Pass
 ; GCN-O1-OPTS-NEXT:        Live DEBUG_VALUE analysis
-; GCN-O1-OPTS-NEXT:      Function register usage analysis
-; GCN-O1-OPTS-NEXT:      FunctionPass Manager
-; GCN-O1-OPTS-NEXT:        Lazy Machine Block Frequency Analysis
-; GCN-O1-OPTS-NEXT:        Machine Optimization Remark Emitter
-; GCN-O1-OPTS-NEXT:        AMDGPU Assembly Printer
-; GCN-O1-OPTS-NEXT:        Free MachineFunction
+; GCN-O1-OPTS-NEXT:    Function register usage analysis
+; GCN-O1-OPTS-NEXT:    FunctionPass Manager
+; GCN-O1-OPTS-NEXT:      Lazy Machine Block Frequency Analysis
+; GCN-O1-OPTS-NEXT:      Machine Optimization Remark Emitter
+; GCN-O1-OPTS-NEXT:      AMDGPU Assembly Printer
+; GCN-O1-OPTS-NEXT:      Free MachineFunction
 ; GCN-O1-OPTS-NEXT:Pass Arguments:  -domtree
 ; GCN-O1-OPTS-NEXT:  FunctionPass Manager
 ; GCN-O1-OPTS-NEXT:    Dominator Tree Construction
 
 ; GCN-O2:Target Library Information
 ; GCN-O2-NEXT:Target Pass Configuration
 ; GCN-O2-NEXT:Machine Module Information
 ; GCN-O2-NEXT:Target Transform Information

 ; GCN-O2-NEXT:        SI Insert Hard Clauses
 ; GCN-O2-NEXT:        MachineDominator Tree Construction
 ; GCN-O2-NEXT:        SI Final Branch Preparation
 ; GCN-O2-NEXT:        SI peephole optimizations
 ; GCN-O2-NEXT:        Post RA hazard recognizer
 ; GCN-O2-NEXT:        Branch relaxation pass
 ; GCN-O2-NEXT:        Register Usage Information Collector Pass
 ; GCN-O2-NEXT:        Live DEBUG_VALUE analysis
-; GCN-O2-NEXT:      Function register usage analysis
-; GCN-O2-NEXT:      FunctionPass Manager
-; GCN-O2-NEXT:        Lazy Machine Block Frequency Analysis
-; GCN-O2-NEXT:        Machine Optimization Remark Emitter
-; GCN-O2-NEXT:        AMDGPU Assembly Printer
-; GCN-O2-NEXT:        Free MachineFunction
+; GCN-O2-NEXT:    Function register usage analysis
+; GCN-O2-NEXT:    FunctionPass Manager
+; GCN-O2-NEXT:      Lazy Machine Block Frequency Analysis
+; GCN-O2-NEXT:      Machine Optimization Remark Emitter
+; GCN-O2-NEXT:      AMDGPU Assembly Printer
+; GCN-O2-NEXT:      Free MachineFunction
 ; GCN-O2-NEXT:Pass Arguments:  -domtree
 ; GCN-O2-NEXT:  FunctionPass Manager
 ; GCN-O2-NEXT:    Dominator Tree Construction
 
 ; GCN-O3:Target Library Information
 ; GCN-O3-NEXT:Target Pass Configuration
 ; GCN-O3-NEXT:Machine Module Information
 ; GCN-O3-NEXT:Target Transform Information

 ; GCN-O3-NEXT:        SI Insert Hard Clauses
 ; GCN-O3-NEXT:        MachineDominator Tree Construction
 ; GCN-O3-NEXT:        SI Final Branch Preparation
 ; GCN-O3-NEXT:        SI peephole optimizations
 ; GCN-O3-NEXT:        Post RA hazard recognizer
 ; GCN-O3-NEXT:        Branch relaxation pass
 ; GCN-O3-NEXT:        Register Usage Information Collector Pass
 ; GCN-O3-NEXT:        Live DEBUG_VALUE analysis
-; GCN-O3-NEXT:      Function register usage analysis
-; GCN-O3-NEXT:      FunctionPass Manager
-; GCN-O3-NEXT:        Lazy Machine Block Frequency Analysis
-; GCN-O3-NEXT:        Machine Optimization Remark Emitter
-; GCN-O3-NEXT:        AMDGPU Assembly Printer
-; GCN-O3-NEXT:        Free MachineFunction
+; GCN-O3-NEXT:    Function register usage analysis
+; GCN-O3-NEXT:    FunctionPass Manager
+; GCN-O3-NEXT:      Lazy Machine Block Frequency Analysis
+; GCN-O3-NEXT:      Machine Optimization Remark Emitter
+; GCN-O3-NEXT:      AMDGPU Assembly Printer
+; GCN-O3-NEXT:      Free MachineFunction
 ; GCN-O3-NEXT:Pass Arguments:  -domtree
 ; GCN-O3-NEXT:  FunctionPass Manager
 ; GCN-O3-NEXT:    Dominator Tree Construction
 
 define void @empty() {
   ret void
 }

llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll

 ; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX908 %s
 ; RUN: not llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefixes=GCN,GFX900 %s
 
+; GFX900:     couldn't allocate input reg for constraint 'a'
+
+
 ; GCN-LABEL: {{^}}max_10_vgprs:
 ; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
 ; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
 ; GFX908-NOT: SCRATCH_RSRC
 ; GFX908-DAG: v_accvgpr_write_b32 [[A_REG:a[0-9]+]], v{{[0-9]}}
 ; GFX900:     buffer_store_dword v{{[0-9]}},
 ; GFX900:     buffer_store_dword v{{[0-9]}},
 ; GFX900:     buffer_load_dword v{{[0-9]}},

 ; GFX908-NOT: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
 ; GFX908-DAG: v_accvgpr_write_b32 [[A_REG:a[0-9]+]], v{{[0-9]}}
 ; GFX908-NOT: buffer_store_dword v{{[0-9]}},
 ; GFX908-NOT: buffer_
 ; GFX908:     v_mov_b32_e32 v{{[0-9]}}, [[V_REG:v[0-9]+]]
 ; GFX908:     v_accvgpr_read_b32 [[V_REG]], [[A_REG]]
 ; GFX908-NOT: buffer_
 
-; GFX900:     couldn't allocate input reg for constraint 'a'
-
 ; GFX908: NumVgprs: 10
 ; GFX908: ScratchSize: 0
 ; GFX908: VGPRBlocks: 2
 ; GFX908: NumVGPRsForWavesPerEU: 10
 define amdgpu_kernel void @max_10_vgprs_used_9a(i32 addrspace(1)* %p) #0 {
   %tid = load volatile i32, i32 addrspace(1)* undef
   call void asm sideeffect "", "a,a,a,a,a,a,a,a,a"(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9)
   %p1 = getelementptr inbounds i32, i32 addrspace(1)* %p, i32 %tid

llvm/test/CodeGen/AMDGPU/trap.ll

 ; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
 
 ; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
 ; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s
 ; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
 
 ; enable trap handler feature
 ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s
 ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s
 
 ; disable trap handler feature
 ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s
 ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s
 
 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
 
+; GCN-WARNING: warning: <unknown>:0:0: in function hsa_debugtrap void (i32 addrspace(1)*): debugtrap handler not supported
+
+
 declare void @llvm.trap() #0
 declare void @llvm.debugtrap() #1
 
 ; MESA-TRAP: .section .AMDGPU.config
 ; MESA-TRAP:  .long   47180
 ; MESA-TRAP-NEXT: .long   208
 
 ; NOMESA-TRAP: .section .AMDGPU.config

 ; MESA-TRAP: .section .AMDGPU.config
 ; MESA-TRAP:  .long   47180
 ; MESA-TRAP-NEXT: .long   208
 
 ; NOMESA-TRAP: .section .AMDGPU.config
 ; NOMESA-TRAP:  .long   47180
 ; NOMESA-TRAP-NEXT: .long   144
 
-; GCN-WARNING: warning: <unknown>:0:0: in function hsa_debugtrap void (i32 addrspace(1)*): debugtrap handler not supported
 ; GCN-LABEL: {{^}}hsa_debugtrap:
 ; HSA-TRAP: enable_trap_handler = 0
 ; HSA-TRAP: s_trap 3
 ; HSA-TRAP: flat_store_dword v[0:1], v3
 
 ; for llvm.debugtrap in non-hsa path without ABI, generate a warning and a s_endpgm instruction
 ; NO-HSA-TRAP: enable_trap_handler = 0
 ; NO-HSA-TRAP: s_endpgm