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Differential D117280

[AMDGPU] Pre-commit test for D116469. NFC
ClosedPublic

Authored by craig.topper on Jan 13 2022, 10:30 PM.

Details

Reviewers
foad
arsenm
Commits
rGfc7af123ddba: [AMDGPU] Pre-commit test for D116469. NFC
Summary

The multiply in this test is miscompiled to 0.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 13 2022, 10:30 PM
Herald added subscribers: kerbowa, t-tye, tpr and 5 others. · View Herald TranscriptJan 13 2022, 10:30 PM
craig.topper requested review of this revision.Jan 13 2022, 10:30 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 13 2022, 10:30 PM
Herald added a subscriber: wdng. · View Herald Transcript
craig.topper added a child revision: D116469: [AMDGPU] Correct the known bits calculation for MUL_I24..Jan 13 2022, 10:30 PM
Harbormaster completed remote builds in B143319: Diff 399898.Jan 13 2022, 11:52 PM
foad accepted this revision.Jan 14 2022, 1:00 AM

Looks obviously fine, thanks!

This revision is now accepted and ready to land.Jan 14 2022, 1:00 AM
Closed by commit rGfc7af123ddba: [AMDGPU] Pre-commit test for D116469. NFC (authored by craig.topper). · Explain WhyJan 14 2022, 8:55 AM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGfc7af123ddba: [AMDGPU] Pre-commit test for D116469. NFC.

Revision Contents

PathSize
llvm/
test/
CodeGen/
AMDGPU/
13 lines

Diff 399898

llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll

Show All 23 Linesentry:
%1 = mul nsw i32 %tid, -5 %1 = mul nsw i32 %tid, -5
%v1 = and i32 %1, -32 %v1 = and i32 %1, -32
%v2 = sext i32 %v1 to i64 %v2 = sext i32 %v1 to i64
%v3 = getelementptr inbounds float, float addrspace(1)* %p, i64 %v2 %v3 = getelementptr inbounds float, float addrspace(1)* %p, i64 %v2
store float 0.000, float addrspace(1)* %v3, align 4 store float 0.000, float addrspace(1)* %v3, align 4
ret void ret void
} }
define i32 @f(i32 %x, i32 %y) {
; GCN-LABEL: f:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_setpc_b64 s[30:31]
%xx = or i32 %x, -128 ; 0xffffff80
%yy = or i32 %y, -128 ; 0xffffff80
%r = mul i32 %xx, %yy
%rr = lshr i32 %r, 14
ret i32 %rr
}
; Function Attrs: nounwind readnone speculatable ; Function Attrs: nounwind readnone speculatable
declare i32 @llvm.amdgcn.workitem.id.x() #20 declare i32 @llvm.amdgcn.workitem.id.x() #20
!4 = !{i32 0, i32 1024} !4 = !{i32 0, i32 1024}