[AArch64] Add native CPU detection for Ampere1

[philipp.tomsich]

Summary

Map the IMPLEMENTOR ID 0xc0 (Ampere Computing) and CPU ID 0xac3
(Ampere1) to "ampere1".

[kristof.beyls]

I'm afraid I don't know if it's possible to check anywhere in public documentation that the values 0xc0 and 0xac3 are correct.
I'm assuming you verified those are the correct.
The code looks good, apart from one place where clang-format suggests different indentation.
With that indentation adapted, this looks good to me.

llvm/lib/Support/Host.cpp

300–302

Please adjust the formatting to be in line with what clang-format suggests.

[philipp.tomsich]

Update formatting as requested.

[kristof.beyls]

LGTM

llvm/lib/Support/Host.cpp

default:
       LLVM_FALLTHROUGH;
     case 0x1002:
       return "exynos-m3";
     case 0x1003:
       return "exynos-m4";
     }
   }
 
+  if (Implementer == "0xc0") { // Ampere Computing
+    return StringSwitch<const char *>(Part)
+        .Case("0xac3", "ampere1")
+        .Default("generic");
+  }
+
   return "generic";
 }
 
 namespace {
 StringRef getCPUNameFromS390Model(unsigned int Id, bool HaveVectorSupport) {
   switch (Id) {
     case 2064:  // z900 not supported by LLVM
     case 2066:

llvm/unittests/Support/Host.cpp

EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
             "cortex-a73");
   EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
                                               "CPU part        : 0xc00"),
             "falkor");
   EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
                                               "CPU part        : 0xc01"),
             "saphira");
 
+  EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
+                                              "CPU part        : 0xac3"),
+            "ampere1");
+
   // MSM8992/4 weirdness
   StringRef MSM8992ProcCpuInfo = R"(
 Processor       : AArch64 Processor rev 3 (aarch64)
 processor       : 0
 processor       : 1
 processor       : 2
 processor       : 3
 processor       : 4