[PowerPC] Update P10 vector insert patterns to use refactored load/stores, and update handling of v4f32 vector insert.

[amyk]

Summary

This patch updates the P10 patterns with a load feeding into an insertelt to utilize the
refactored load and store infrastructure, as well as updating any tests that exhibit any
codegen changes. Furthermore, custom legalization is added for v4f32 on Power9 and
above to not only assist with adjusting the refactored load/stores for P10 vector insert,
but also it enables the utilization of direct moves.

[amyk]

Ping.

[amyk]

Ping.

[nemanjai]

A minor nit about the description - you talk about implementing a DAG combine but you implement a custom legalization.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10786–10792

This does a very good job explaining *what* is being done, which I don't think is particularly useful because the code is rather nicely self-documenting. What is missing is *why* this is being done.
We only do this with ISA 3.1 because on previous architectures, it is cheaper to do an lxsiwzx + a permute.

Note, this is also useful on Power9 because direct moves are cheaper than the alternative. So please pull this out and guard with Subtarget.hasP9Vector() (and of course change the respective tests).

10796

This isn't necessary. Let the DAG handle this for you.

• Bitcast the vector
• Bitcast the scalar
• Produce a v4i32 insert
• Bitcast and return the result

10799

It is not a good idea to insert an i32 into a v4f32 vector. You should bitcast V1 as well.

[amyk]

Address Nemanja's comments:

• Pulling out the code and guarding it for P9 and above
• Update test cases affected by the change
• Update the handling to:
  • Bitcast the vector
  • Bitcast the scalar
  • Produce the v4i32 vector insert
  • Bitcast and return the result

[nemanjai]

LGTM other than the change to the comment.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10766–10771

Please note that your description re. Power10 is temporal in nature. The "refactored load and store infrastructure..." is newly refactored now. In the future, it will just be how we select loads and stores (i.e. code has no memory of how it looked before). I think it would suffice to add something like this as a comment:

// On targets with inexpensive direct moves (Power9 and up), a
// (insert_vector_elt v4f32:$vec, (f32 load)) is always better as an
// integer load since a single precision load will involve conversion
// to double precision on the load followed by another conversion
// to single precision.

[nemanjai]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2818–2819

I think that you should be able to remove all of the patterns for load+insert with f32 since they will not make it to instruction selection (i.e. they're all being converted to i32).

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (Subtarget.hasAltivec()) {
     }
 
     if (Subtarget.hasP9Altivec()) {
       if (Subtarget.isISA3_1()) {
         setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
         setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Legal);
         setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Legal);
         setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
-        setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Legal);
       } else {
         setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
         setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
       }
       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8,  Legal);
       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8,  Legal);
SDValue PPCTargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
   EVT VT = Op.getValueType();
   SDLoc dl(Op);
   SDValue V1 = Op.getOperand(0);
   SDValue V2 = Op.getOperand(1);
 
   if (VT == MVT::v2f64 && C)
     return Op;
 
+  if (Subtarget.hasP9Vector()) {
+    // A f32 load feeding into a v4f32 insert_vector_elt is handled in this way
+    // because on P10, it allows this specific insert_vector_elt load pattern to
+    // utilize the refactored load and store infrastructure in order to exploit
+    // prefixed loads.
+    // On targets with inexpensive direct moves (Power9 and up), a
+    // (insert_vector_elt v4f32:$vec, (f32 load)) is always better as an integer
+    // load since a single precision load will involve conversion to double
+    // precision on the load followed by another conversion to single precision.
+    if ((VT == MVT::v4f32) && (V2.getValueType() == MVT::f32) &&
+        (isa<LoadSDNode>(V2))) {
+      SDValue BitcastVector = DAG.getBitcast(MVT::v4i32, V1);
+      SDValue BitcastLoad = DAG.getBitcast(MVT::i32, V2);
+      SDValue InsVecElt =
+          DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v4i32, BitcastVector,
+                      BitcastLoad, Op.getOperand(2));
+      return DAG.getBitcast(MVT::v4f32, InsVecElt);
+    }
+  }
+
   if (Subtarget.isISA3_1()) {
     if ((VT == MVT::v2i64 || VT == MVT::v2f64) && !Subtarget.isPPC64())
       return SDValue();
     // On P10, we have legal lowering for constant and variable indices for
     // all vectors.
     if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
         VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
       return Op;
   }
 
   // Before P10, we have legal lowering for constant indices but not for
   // variable ones.
   if (!C)
     return SDValue();
 
   // We can use MTVSRZ + VECINSERT for v8i16 and v16i8 types.
   if (VT == MVT::v8i16 || VT == MVT::v16i8) {
     SDValue Mtvsrz = DAG.getNode(PPCISD::MTVSRZ, dl, VT, V2);
     unsigned BytesInEachElement = VT.getVectorElementType().getSizeInBits() / 8;
     unsigned InsertAtElement = C->getZExtValue();
     unsigned InsertAtByte = InsertAtElement * BytesInEachElement;
     if (Subtarget.isLittleEndian()) {
       InsertAtByte = (16 - BytesInEachElement) - InsertAtByte;

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

let Predicates = [IsISA3_1, HasVSX, IsLittleEndian] in {
   def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)),
             (VINSHRX $vDi, InsertEltShift.Sub32Left1, $rA)>;
   def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)),
             (VINSWRX $vDi, InsertEltShift.Sub32Left2, $rA)>;
   def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)),
             (VINSDRX $vDi, InsertEltShift.Left3, $rA)>;
 
   def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i64:$rB)),
             (VINSWVRX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>;
-  def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load iaddr:$rA)), i64:$rB)),
-            (VINSWRX $vDi, InsertEltShift.Sub32Left2, (LWZ memri:$rA))>;
-  def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load iaddrX34:$rA)), i64:$rB)),
-            (VINSWRX $vDi, InsertEltShift.Sub32Left2, (PLWZ memri34:$rA))>;
-  def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load xaddr:$rA)), i64:$rB)),
-            (VINSWRX $vDi, InsertEltShift.Sub32Left2, (LWZX memrr:$rA))>;
 
   def : Pat<(v2f64 (insertelt v2f64:$vDi,  f64:$A, i64:$rB)),
             (VINSDRX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>;
-  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load iaddrX4:$rA)), i64:$rB)),
+  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)),
             (VINSDRX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>;
-  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load iaddrX34:$rA)), i64:$rB)),
+  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)),
             (VINSDRX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>;
-  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load xaddrX4:$rA)), i64:$rB)),
+  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)),
             (VINSDRX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>;
   let AddedComplexity = 400 in {
     // Immediate vector insert element
     foreach Idx = [0, 1, 2, 3] in {
       def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, Idx)),
                 (VINSW $vDi, !mul(!sub(3, Idx), 4), $rA)>;
-      def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load iaddr:$rA)), Idx)),
-                (VINSW $vDi, !mul(!sub(3, Idx), 4), (LWZ memri:$rA))>;
-      def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load iaddrX34:$rA)), Idx)),
-                (VINSW $vDi, !mul(!sub(3, Idx), 4), (PLWZ memri34:$rA))>;
-      def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load xaddr:$rA)), Idx)),
-                (VINSW $vDi, !mul(!sub(3, Idx), 4), (LWZX memrr:$rA))>;
     }
     foreach i = [0, 1] in
      def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, (i64 i))),
                (VINSD $vDi, !mul(!sub(1, i), 8), $rA)>;
   }
 }
 
 let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC32] in {
   // Indexed vector insert element
   def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i32:$rB)),
             (VINSBLX $vDi, $rB, $rA)>;
   def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i32:$rB)),
             (VINSHLX $vDi, InsertEltShift.Left1, $rA)>;
   def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i32:$rB)),
             (VINSWLX $vDi, InsertEltShift.Left2, $rA)>;
 
   def : Pat<(v4f32 (insertelt v4f32:$vDi,  f32:$rA, i32:$rB)),
             (VINSWVLX $vDi, InsertEltShift.Left2, (XSCVDPSPN $rA))>;
-  def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load iaddr:$rA)), i32:$rB)),
-            (VINSWLX v4f32:$vDi, InsertEltShift.Left2, (LWZ memri:$rA))>;
-  def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load iaddrX34:$rA)), i32:$rB)),
-            (VINSWLX v4f32:$vDi, InsertEltShift.Left2, (PLWZ memri34:$rA))>;
-  def: Pat<(v4f32(insertelt v4f32 : $vDi, (f32(load xaddr : $rA)), i32 : $rB)),
-           (VINSWLX v4f32 : $vDi, InsertEltShift.Left2, (LWZX memrr : $rA))>;
 }
 
 let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC64] in {
   // Indexed vector insert element
   def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)),
             (VINSBLX $vDi, InsertEltShift.Sub32, $rA)>;
   def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)),
             (VINSHLX $vDi, InsertEltShift.Sub32Left1, $rA)>;
   def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)),
             (VINSWLX $vDi, InsertEltShift.Sub32Left2, $rA)>;
   def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)),
             (VINSDLX $vDi, InsertEltShift.Left3, $rA)>;
 
   def : Pat<(v4f32 (insertelt v4f32:$vDi,  f32:$rA, i64:$rB)),
             (VINSWVLX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>;
-  def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load iaddr:$rA)), i64:$rB)),
-            (VINSWLX $vDi, InsertEltShift.Sub32Left2, (LWZ memri:$rA))>;
-  def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load iaddrX34:$rA)), i64:$rB)),
-            (VINSWLX $vDi, InsertEltShift.Sub32Left2, (PLWZ memri34:$rA))>;
-  def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load xaddr:$rA)), i64:$rB)),
-            (VINSWLX $vDi, InsertEltShift.Sub32Left2, (LWZX memrr:$rA))>;
 
   def : Pat<(v2f64 (insertelt v2f64:$vDi,  f64:$A, i64:$rB)),
             (VINSDLX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>;
-  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load iaddrX4:$rA)), i64:$rB)),
+  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)),
             (VINSDLX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>;
-  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load iaddrX34:$rA)), i64:$rB)),
+  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)),
             (VINSDLX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>;
-  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load xaddrX4:$rA)), i64:$rB)),
+  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)),
             (VINSDLX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>;
 }
 
 let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX, IsBigEndian] in {
   // Immediate vector insert element
   foreach Ty = [i32, i64] in {
     foreach Idx = [0, 1, 2, 3] in {
       def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, (Ty Idx))),
                (VINSW $vDi, !mul(Idx, 4), $rA)>;
-      def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load iaddr:$rA)),
-                                  (Ty Idx))),
-               (VINSW $vDi, !mul(Idx, 4), (LWZ memri:$rA))>;
-      def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load iaddrX34:$rA)),
-                                  (Ty Idx))),
-               (VINSW $vDi, !mul(Idx, 4), (PLWZ memri34:$rA))>;
-      def : Pat<(v4f32 (insertelt v4f32:$vDi, (f32 (load xaddr:$rA)),
-                                  (Ty Idx))),
-               (VINSW $vDi, !mul(Idx, 4), (LWZX memrr:$rA))>;
     }
   }
 
   foreach Idx = [0, 1] in
     def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, Idx)),
               (VINSD $vDi, !mul(Idx, 8), $rA)>;
 }

llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll

entry:
   ret <4 x float> %vecins
 }
 
 define <4 x float> @testFloat2(<4 x float> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
 ; CHECK-64-LABEL: testFloat2:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lwz 6, 0(3)
 ; CHECK-64-DAG:     rlwinm 4, 4, 2, 28, 29
-; CHECK-64-DAG:     addi 7, 1, -32
-; CHECK-64-NEXT:    stxv 34, -32(1)
+; CHECK-64-DAG:     addi 7, 1, -16
+; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stwx 6, 7, 4
 ; CHECK-64-NEXT:    rlwinm 4, 5, 2, 28, 29
-; CHECK-64-NEXT:    addi 5, 1, -16
-; CHECK-64-NEXT:    lxv 0, -32(1)
+; CHECK-64-NEXT:    addi 5, 1, -32
+; CHECK-64-NEXT:    lxv 0, -16(1)
 ; CHECK-64-NEXT:    lwz 3, 1(3)
-; CHECK-64-NEXT:    stxv 0, -16(1)
+; CHECK-64-NEXT:    stxv 0, -32(1)
 ; CHECK-64-NEXT:    stwx 3, 5, 4
-; CHECK-64-NEXT:    lxv 34, -16(1)
+; CHECK-64-NEXT:    lxv 34, -32(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testFloat2:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lwz 6, 0(3)
-; CHECK-32-NEXT:    addi 7, 1, -32
+; CHECK-32-NEXT:    addi 7, 1, -16
 ; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
-; CHECK-32-NEXT:    stxv 34, -32(1)
+; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    rlwinm 5, 5, 2, 28, 29
 ; CHECK-32-NEXT:    stwx 6, 7, 4
-; CHECK-32-NEXT:    addi 4, 1, -16
-; CHECK-32-NEXT:    lxv 0, -32(1)
+; CHECK-32-NEXT:    addi 4, 1, -48
+; CHECK-32-NEXT:    lxv 0, -16(1)
 ; CHECK-32-NEXT:    lwz 3, 1(3)
-; CHECK-32-NEXT:    stxv 0, -16(1)
+; CHECK-32-NEXT:    stxv 0, -48(1)
 ; CHECK-32-NEXT:    stwx 3, 4, 5
-; CHECK-32-NEXT:    lxv 34, -16(1)
+; CHECK-32-NEXT:    lxv 34, -48(1)
 ; CHECK-32-NEXT:    blr
 ;
 ; CHECK-64-P10-LABEL: testFloat2:
 ; CHECK-64-P10:       # %bb.0: # %entry
 ; CHECK-64-P10-NEXT:    lwz 6, 0(3)
 ; CHECK-64-P10-NEXT:    extsw 4, 4
 ; CHECK-64-P10-NEXT:    lwz 3, 1(3)
 ; CHECK-64-P10-NEXT:    slwi 4, 4, 2
entry:
   ret <4 x float> %vecins2
 }
 
 define <4 x float> @testFloat3(<4 x float> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
 ; CHECK-64-LABEL: testFloat3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lis 6, 1
 ; CHECK-64-DAG:         rlwinm 4, 4, 2, 28, 29
-; CHECK-64-DAG:    addi 7, 1, -32
+; CHECK-64-DAG:    addi 7, 1, -16
 ; CHECK-64-NEXT:    lwzx 6, 3, 6
-; CHECK-64-NEXT:    stxv 34, -32(1)
+; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stwx 6, 7, 4
 ; CHECK-64-NEXT:    li 4, 1
-; CHECK-64-NEXT:    lxv 0, -32(1)
+; CHECK-64-NEXT:    lxv 0, -16(1)
 ; CHECK-64-NEXT:    rldic 4, 4, 36, 27
 ; CHECK-64-NEXT:    lwzx 3, 3, 4
 ; CHECK-64-NEXT:    rlwinm 4, 5, 2, 28, 29
-; CHECK-64-NEXT:    addi 5, 1, -16
-; CHECK-64-NEXT:    stxv 0, -16(1)
+; CHECK-64-NEXT:    addi 5, 1, -32
+; CHECK-64-NEXT:    stxv 0, -32(1)
 ; CHECK-64-NEXT:    stwx 3, 5, 4
-; CHECK-64-NEXT:    lxv 34, -16(1)
+; CHECK-64-NEXT:    lxv 34, -32(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testFloat3:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lis 6, 1
-; CHECK-32-NEXT:    addi 7, 1, -32
+; CHECK-32-NEXT:    addi 7, 1, -16
 ; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
 ; CHECK-32-NEXT:    rlwinm 5, 5, 2, 28, 29
 ; CHECK-32-NEXT:    lwzx 6, 3, 6
-; CHECK-32-NEXT:    stxv 34, -32(1)
+; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    stwx 6, 7, 4
-; CHECK-32-NEXT:    addi 4, 1, -16
-; CHECK-32-NEXT:    lxv 0, -32(1)
+; CHECK-32-NEXT:    addi 4, 1, -48
+; CHECK-32-NEXT:    lxv 0, -16(1)
 ; CHECK-32-NEXT:    lwz 3, 0(3)
-; CHECK-32-NEXT:    stxv 0, -16(1)
+; CHECK-32-NEXT:    stxv 0, -48(1)
 ; CHECK-32-NEXT:    stwx 3, 4, 5
-; CHECK-32-NEXT:    lxv 34, -16(1)
+; CHECK-32-NEXT:    lxv 34, -48(1)
 ; CHECK-32-NEXT:    blr
 ;
 ; CHECK-64-P10-LABEL: testFloat3:
 ; CHECK-64-P10:       # %bb.0: # %entry
 ; CHECK-64-P10-NEXT:    plwz 6, 65536(3), 0
 ; CHECK-64-P10-NEXT:    extsw 4, 4
 ; CHECK-64-P10-NEXT:    slwi 4, 4, 2
 ; CHECK-64-P10-NEXT:    vinswlx 2, 4, 6
 ; CHECK-64-P10-NEXT:    li 4, 1
 ; CHECK-64-P10-NEXT:    rldic 4, 4, 36, 27
 ; CHECK-64-P10-NEXT:    lwzx 3, 3, 4
 ; CHECK-64-P10-NEXT:    extsw 4, 5
 ; CHECK-64-P10-NEXT:    slwi 4, 4, 2
 ; CHECK-64-P10-NEXT:    vinswlx 2, 4, 3
 ; CHECK-64-P10-NEXT:    blr
 ;
 ; CHECK-32-P10-LABEL: testFloat3:
 ; CHECK-32-P10:       # %bb.0: # %entry
-; CHECK-32-P10-NEXT:    lis 6, 1
-; CHECK-32-P10-NEXT:    slwi 4, 4, 2
-; CHECK-32-P10-NEXT:    lwzx 6, 3, 6
+; CHECK-32-P10-NEXT:    plwz 6, 65536(3), 0
 ; CHECK-32-P10-NEXT:    lwz 3, 0(3)
+; CHECK-32-P10-NEXT:    slwi 4, 4, 2
 ; CHECK-32-P10-NEXT:    vinswlx 2, 4, 6
 ; CHECK-32-P10-NEXT:    slwi 4, 5, 2
 ; CHECK-32-P10-NEXT:    vinswlx 2, 4, 3
 ; CHECK-32-P10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %b, i64 65536
   %0 = bitcast i8* %add.ptr to float*
   %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 68719476736
entry:
   %vecins = insertelement <4 x float> %a, float %b, i32 0
   %vecins1 = insertelement <4 x float> %vecins, float %b, i32 2
   ret <4 x float> %vecins1
 }
 
 define <4 x float> @testFloatImm2(<4 x float> %a, i32* %b) {
 ; CHECK-64-LABEL: testFloatImm2:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    lfs 0, 0(3)
-; CHECK-64-NEXT:    xscvdpspn 0, 0
+; CHECK-64-NEXT:    lwz 4, 0(3)
+; CHECK-64-NEXT:    lwz 3, 4(3)
+; CHECK-64-NEXT:    mtfprwz 0, 4
 ; CHECK-64-NEXT:    xxinsertw 34, 0, 0
-; CHECK-64-NEXT:    lfs 0, 4(3)
-; CHECK-64-NEXT:    xscvdpspn 0, 0
+; CHECK-64-NEXT:    mtfprwz 0, 3
 ; CHECK-64-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testFloatImm2:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lfs 0, 0(3)
-; CHECK-32-NEXT:    xscvdpspn 0, 0
+; CHECK-32-NEXT:    lwz 4, 0(3)
+; CHECK-32-NEXT:    lwz 3, 4(3)
+; CHECK-32-NEXT:    mtfprwz 0, 4
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 0
-; CHECK-32-NEXT:    lfs 0, 4(3)
-; CHECK-32-NEXT:    xscvdpspn 0, 0
+; CHECK-32-NEXT:    mtfprwz 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-32-NEXT:    blr
 ;
 ; CHECK-64-P10-LABEL: testFloatImm2:
 ; CHECK-64-P10:       # %bb.0: # %entry
 ; CHECK-64-P10-NEXT:    lwz 4, 0(3)
 ; CHECK-64-P10-NEXT:    lwz 3, 4(3)
 ; CHECK-64-P10-NEXT:    vinsw 2, 4, 0
entry:
   %vecins2 = insertelement <4 x float> %vecins, float %3, i32 2
   ret <4 x float> %vecins2
 }
 
 define <4 x float> @testFloatImm3(<4 x float> %a, i32* %b) {
 ; CHECK-64-LABEL: testFloatImm3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lis 4, 4
-; CHECK-64-NEXT:    lfsx 0, 3, 4
+; CHECK-64-NEXT:    lwzx 4, 3, 4
+; CHECK-64-NEXT:    mtfprwz 0, 4
 ; CHECK-64-NEXT:    li 4, 1
 ; CHECK-64-NEXT:    rldic 4, 4, 38, 25
-; CHECK-64-NEXT:    xscvdpspn 0, 0
 ; CHECK-64-NEXT:    xxinsertw 34, 0, 0
-; CHECK-64-NEXT:    lfsx 0, 3, 4
-; CHECK-64-NEXT:    xscvdpspn 0, 0
+; CHECK-64-NEXT:    lwzx 3, 3, 4
+; CHECK-64-NEXT:    mtfprwz 0, 3
 ; CHECK-64-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testFloatImm3:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lis 4, 4
-; CHECK-32-NEXT:    lfsx 0, 3, 4
-; CHECK-32-NEXT:    xscvdpspn 0, 0
+; CHECK-32-NEXT:    lwzx 4, 3, 4
+; CHECK-32-NEXT:    lwz 3, 0(3)
+; CHECK-32-NEXT:    mtfprwz 0, 4
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 0
-; CHECK-32-NEXT:    lfs 0, 0(3)
-; CHECK-32-NEXT:    xscvdpspn 0, 0
+; CHECK-32-NEXT:    mtfprwz 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-32-NEXT:    blr
 ;
 ; CHECK-64-P10-LABEL: testFloatImm3:
 ; CHECK-64-P10:       # %bb.0: # %entry
 ; CHECK-64-P10-NEXT:    plwz 4, 262144(3), 0
 ; CHECK-64-P10-NEXT:    vinsw 2, 4, 0
 ; CHECK-64-P10-NEXT:    li 4, 1
 ; CHECK-64-P10-NEXT:    rldic 4, 4, 38, 25
 ; CHECK-64-P10-NEXT:    lwzx 3, 3, 4
 ; CHECK-64-P10-NEXT:    vinsw 2, 3, 8
 ; CHECK-64-P10-NEXT:    blr
 ;
 ; CHECK-32-P10-LABEL: testFloatImm3:
 ; CHECK-32-P10:       # %bb.0: # %entry
-; CHECK-32-P10-NEXT:    lis 4, 4
-; CHECK-32-P10-NEXT:    lwzx 4, 3, 4
+; CHECK-32-P10-NEXT:    plwz 4, 262144(3), 0
 ; CHECK-32-P10-NEXT:    lwz 3, 0(3)
 ; CHECK-32-P10-NEXT:    vinsw 2, 4, 0
 ; CHECK-32-P10-NEXT:    vinsw 2, 3, 8
 ; CHECK-32-P10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i32, i32* %b, i64 65536
   %0 = bitcast i32* %add.ptr to float*
   %add.ptr1 = getelementptr inbounds i32, i32* %b, i64 68719476736

llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll

entry:
   %vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
   ret <4 x i32> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <4 x float> @s2v_test_f1(float* nocapture readonly %f64, <4 x float> %vec)  {
 ; P9LE-LABEL: s2v_test_f1:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    lfs f0, 0(r3)
-; P9LE-NEXT:    xscvdpspn vs0, f0
+; P9LE-NEXT:    lwz r3, 0(r3)
+; P9LE-NEXT:    mtfprwz f0, r3
 ; P9LE-NEXT:    xxinsertw v2, vs0, 12
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: s2v_test_f1:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    lfs f0, 0(r3)
-; P9BE-NEXT:    xscvdpspn vs0, f0
+; P9BE-NEXT:    lwz r3, 0(r3)
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    xxinsertw v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: s2v_test_f1:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
 ; P8LE-NEXT:    lxsiwzx v4, 0, r3
 ; P8LE-NEXT:    addi r4, r4, .LCPI5_0@toc@l

llvm/test/CodeGen/PowerPC/vec_insert_elt.ll

 ; CHECK-BE-NEXT:    slwi r4, r4, 2
 ; CHECK-BE-NEXT:    vinswlx v2, r4, r3
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testFloat2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lwz r3, 0(r5)
 ; CHECK-P9-NEXT:    rlwinm r4, r6, 2, 28, 29
-; CHECK-P9-NEXT:    addi r6, r1, -32
-; CHECK-P9-NEXT:    stxv v2, -32(r1)
+; CHECK-P9-NEXT:    addi r6, r1, -16
+; CHECK-P9-NEXT:    stxv v2, -16(r1)
 ; CHECK-P9-NEXT:    stwx r3, r6, r4
 ; CHECK-P9-NEXT:    rlwinm r4, r7, 2, 28, 29
-; CHECK-P9-NEXT:    lxv vs0, -32(r1)
+; CHECK-P9-NEXT:    lxv vs0, -16(r1)
 ; CHECK-P9-NEXT:    lwz r3, 1(r5)
-; CHECK-P9-NEXT:    addi r5, r1, -16
-; CHECK-P9-NEXT:    stxv vs0, -16(r1)
+; CHECK-P9-NEXT:    addi r5, r1, -32
+; CHECK-P9-NEXT:    stxv vs0, -32(r1)
 ; CHECK-P9-NEXT:    stwx r3, r5, r4
-; CHECK-P9-NEXT:    lxv v2, -16(r1)
+; CHECK-P9-NEXT:    lxv v2, -32(r1)
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = bitcast i8* %b to float*
   %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 1
   %1 = bitcast i8* %add.ptr1 to float*
   %2 = load float, float* %0, align 4
   %vecins = insertelement <4 x float> %a, float %2, i32 %idx1
   %3 = load float, float* %1, align 4

 ; CHECK-BE-NEXT:    lwzx r3, r5, r3
 ; CHECK-BE-NEXT:    vinswlx v2, r4, r3
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testFloat3:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r3, 1
 ; CHECK-P9-NEXT:    rlwinm r4, r6, 2, 28, 29
-; CHECK-P9-NEXT:    addi r6, r1, -32
+; CHECK-P9-NEXT:    addi r6, r1, -16
 ; CHECK-P9-NEXT:    lwzx r3, r5, r3
-; CHECK-P9-NEXT:    stxv v2, -32(r1)
+; CHECK-P9-NEXT:    stxv v2, -16(r1)
 ; CHECK-P9-NEXT:    stwx r3, r6, r4
 ; CHECK-P9-NEXT:    li r3, 1
 ; CHECK-P9-NEXT:    rlwinm r4, r7, 2, 28, 29
-; CHECK-P9-NEXT:    lxv vs0, -32(r1)
+; CHECK-P9-NEXT:    lxv vs0, -16(r1)
 ; CHECK-P9-NEXT:    rldic r3, r3, 36, 27
 ; CHECK-P9-NEXT:    lwzx r3, r5, r3
-; CHECK-P9-NEXT:    addi r5, r1, -16
-; CHECK-P9-NEXT:    stxv vs0, -16(r1)
+; CHECK-P9-NEXT:    addi r5, r1, -32
+; CHECK-P9-NEXT:    stxv vs0, -32(r1)
 ; CHECK-P9-NEXT:    stwx r3, r5, r4
-; CHECK-P9-NEXT:    lxv v2, -16(r1)
+; CHECK-P9-NEXT:    lxv v2, -32(r1)
 ; CHECK-P9-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %b, i64 65536
   %0 = bitcast i8* %add.ptr to float*
   %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 68719476736
   %1 = bitcast i8* %add.ptr1 to float*
   %2 = load float, float* %0, align 4
   %vecins = insertelement <4 x float> %a, float %2, i32 %idx1

 ; CHECK-BE-NEXT:    lwz r3, 0(r5)
 ; CHECK-BE-NEXT:    vinsw v2, r3, 0
 ; CHECK-BE-NEXT:    lwz r3, 4(r5)
 ; CHECK-BE-NEXT:    vinsw v2, r3, 8
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testFloatImm2:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    lfs f0, 0(r5)
-; CHECK-P9-NEXT:    xscvdpspn vs0, f0
+; CHECK-P9-NEXT:    lwz r3, 0(r5)
+; CHECK-P9-NEXT:    mtfprwz f0, r3
+; CHECK-P9-NEXT:    lwz r3, 4(r5)
 ; CHECK-P9-NEXT:    xxinsertw v2, vs0, 0
-; CHECK-P9-NEXT:    lfs f0, 4(r5)
-; CHECK-P9-NEXT:    xscvdpspn vs0, f0
+; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    xxinsertw v2, vs0, 8
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = bitcast i32* %b to float*
   %add.ptr1 = getelementptr inbounds i32, i32* %b, i64 1
   %1 = bitcast i32* %add.ptr1 to float*
   %2 = load float, float* %0, align 4
   %vecins = insertelement <4 x float> %a, float %2, i32 0

 ; CHECK-BE-NEXT:    rldic r3, r3, 38, 25
 ; CHECK-BE-NEXT:    lwzx r3, r5, r3
 ; CHECK-BE-NEXT:    vinsw v2, r3, 8
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testFloatImm3:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r3, 4
-; CHECK-P9-NEXT:    lfsx f0, r5, r3
+; CHECK-P9-NEXT:    lwzx r3, r5, r3
+; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    li r3, 1
 ; CHECK-P9-NEXT:    rldic r3, r3, 38, 25
-; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxinsertw v2, vs0, 0
-; CHECK-P9-NEXT:    lfsx f0, r5, r3
-; CHECK-P9-NEXT:    xscvdpspn vs0, f0
+; CHECK-P9-NEXT:    lwzx r3, r5, r3
+; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    xxinsertw v2, vs0, 8
 ; CHECK-P9-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i32, i32* %b, i64 65536
   %0 = bitcast i32* %add.ptr to float*
   %add.ptr1 = getelementptr inbounds i32, i32* %b, i64 68719476736
   %1 = bitcast i32* %add.ptr1 to float*
   %2 = load float, float* %0, align 4