This is an archive of the discontinued LLVM Phabricator instance.

Differential D115450

[GlobalISel] Fix IRTranslator for constexpr fcmp
ClosedPublic

Authored by kschwarz on Dec 9 2021, 8:32 AM.

Details

Reviewers
arsenm
foad
paquette
Commits
rGa34465372507: [GlobalISel] Fix IRTranslator for constexpr fcmp
Summary

The existing code assumed fcmp to always be an Instruction, but it can also be a ConstExpr.

Diff Detail

Event Timeline

kschwarz created this revision.Dec 9 2021, 8:32 AM
Herald added subscribers: kerbowa, hiraditya, rovka and 2 others. · View Herald TranscriptDec 9 2021, 8:32 AM
kschwarz requested review of this revision.Dec 9 2021, 8:32 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 9 2021, 8:32 AM
Herald added a subscriber: wdng. · View Herald Transcript
arsenm accepted this revision.Dec 9 2021, 8:33 AM
This revision is now accepted and ready to land.Dec 9 2021, 8:33 AM
Harbormaster completed remote builds in B138462: Diff 393179.Dec 9 2021, 9:41 AM
Closed by commit rGa34465372507: [GlobalISel] Fix IRTranslator for constexpr fcmp (authored by kschwarz). · Explain WhyDec 9 2021, 11:49 PM
This revision was automatically updated to reflect the committed changes.
kschwarz added a commit: rGa34465372507: [GlobalISel] Fix IRTranslator for constexpr fcmp.

Revision Contents

PathSize
llvm/
lib/
CodeGen/
GlobalISel/
7 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
23 lines

Diff 393384

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Show First 20 Lines • Show All 332 Lines • ▼ Show 20 Lines if (CmpInst::isIntPredicate(Pred))
MIRBuilder.buildICmp(Pred, Res, Op0, Op1); MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
else if (Pred == CmpInst::FCMP_FALSE) else if (Pred == CmpInst::FCMP_FALSE)
MIRBuilder.buildCopy( MIRBuilder.buildCopy(
Res, getOrCreateVReg(*Constant::getNullValue(U.getType()))); Res, getOrCreateVReg(*Constant::getNullValue(U.getType())));
else if (Pred == CmpInst::FCMP_TRUE) else if (Pred == CmpInst::FCMP_TRUE)
MIRBuilder.buildCopy( MIRBuilder.buildCopy(
Res, getOrCreateVReg(*Constant::getAllOnesValue(U.getType()))); Res, getOrCreateVReg(*Constant::getAllOnesValue(U.getType())));
else { else {
assert(CI && "Instruction should be CmpInst"); uint16_t Flags = 0;
MIRBuilder.buildFCmp(Pred, Res, Op0, Op1, if (CI)
MachineInstr::copyFlagsFromInstruction(*CI)); Flags = MachineInstr::copyFlagsFromInstruction(*CI);
MIRBuilder.buildFCmp(Pred, Res, Op0, Op1, Flags);
} }
return true; return true;
} }
bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) { bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
const ReturnInst &RI = cast<ReturnInst>(U); const ReturnInst &RI = cast<ReturnInst>(U);
const Value *Ret = RI.getReturnValue(); const Value *Ret = RI.getReturnValue();
▲ Show 20 Lines • Show All 3,164 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @constantexpr_select_1() {
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]] ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: G_STORE [[SELECT]](s32), [[DEF]](p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[SELECT]](s32), [[DEF]](p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; CHECK: S_ENDPGM 0 ; CHECK: S_ENDPGM 0
store i32 select (i1 icmp eq (i8 addrspace(1)* @gint, i8 addrspace(1)* inttoptr (i64 1024 to i8 addrspace(1)*)), i32 1, i32 0), i32 addrspace(1)* undef, align 4 store i32 select (i1 icmp eq (i8 addrspace(1)* @gint, i8 addrspace(1)* inttoptr (i64 1024 to i8 addrspace(1)*)), i32 1, i32 0), i32 addrspace(1)* undef, align 4
ret void ret void
} }
@a = external global [2 x i32], align 4
define i32 @test_fcmp_constexpr() {
; CHECK-LABEL: name: test_fcmp_constexpr
; CHECK: bb.1.entry:
; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[C]](s64)
; CHECK: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[PTR_ADD]](p0), [[GV1]]
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[ICMP]](s1)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[UITOFP]](s32), [[C1]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FCMP]](s1)
; CHECK: $vgpr0 = COPY [[ZEXT]](s32)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
entry:
ret i32 zext (i1 fcmp oeq (float uitofp (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @a, i64 0, i64 1), i32* @var) to float), float 0.000000e+00) to i32)
}