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[AMDGPU] Add AV class spill pseudo instructions
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Authored by cdevadas on Dec 9 2021, 3:50 AM.

Details

Summary

While enabling vector superclasses with D109301,
the AV spills are converted into VGPR spills by
introducing appropriate copies. The whole thing
ended up adding two instructions per spill (a copy
+ vgpr spill pseudo) and caused an incorrect
liverange update during inline spiller.

This patch adds the pseudo instructions for all
AV spills from 32b to 1024b and handles them in
in the way all other spills are lowered.

Diff Detail

Event Timeline

cdevadas created this revision.Dec 9 2021, 3:50 AM
cdevadas requested review of this revision.Dec 9 2021, 3:50 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 9 2021, 3:50 AM
arsenm accepted this revision.Dec 9 2021, 7:40 AM

LGTM with the pseudo code size fix. I'm surprised this didn't require any changes for the expansion

llvm/lib/Target/AMDGPU/SIInstructions.td
764

Needs to set 1 parameter like the AGPR cases?

This revision is now accepted and ready to land.Dec 9 2021, 7:40 AM
cdevadas updated this revision to Diff 393180.Dec 9 2021, 8:36 AM

Considered the max size for AV spills the same as AGPRs.

arsenm accepted this revision.Dec 9 2021, 8:47 AM
This revision was automatically updated to reflect the committed changes.
llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll