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Differential D115396

[ASan] Replace IR based callbacks with shared assembly code callbacks.
ClosedPublic

Authored by kstoimenov on Dec 8 2021, 1:43 PM.

Details

Reviewers
vitalybuka
morehouse
Commits
rG89577be8958f: [ASan] Replace IR based callbacks with shared assembly code callbacks.
rGdb124df49506: [ASan] Replace IR based callbacks with shared assembly code callbacks.
Summary

This change moves optimized callbacks from each .o file to compiler-rt.

Diff Detail

Unit TestsFailed

TimeTest
70 msx64 debian > LLVM.Bindings/Go::go.test

Event Timeline

kstoimenov created this revision.Dec 8 2021, 1:43 PM
Herald added subscribers: pengfei, hiraditya. · View Herald TranscriptDec 8 2021, 1:43 PM
kstoimenov requested review of this revision.Dec 8 2021, 1:43 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 8 2021, 1:43 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
kstoimenov retitled this revision from [ASan] Replace IR optimzied callbacks with shared direct assebly code callbacks. to [ASan] Replace IR based callbacks with shared assembly code callbacks..Dec 8 2021, 1:44 PM
kstoimenov added a parent revision: D114558: [ASan] Shared optimized callbacks implementation..
kstoimenov added a reviewer: vitalybuka.Dec 8 2021, 1:51 PM
kstoimenov added a reviewer: morehouse.Dec 8 2021, 2:26 PM
Harbormaster completed remote builds in B138276: Diff 392921.Dec 8 2021, 6:24 PM
morehouse added inline comments.Dec 9 2021, 9:03 AM
llvm/lib/Target/X86/X86MCInstLower.cpp
1351–1357

We didn't implement OR callbacks, did we? Probably we should not emit calls to them.

kstoimenov updated this revision to Diff 393338.Dec 9 2021, 5:00 PM

Added llvm_unreachable for or.

llvm/lib/Target/X86/X86MCInstLower.cpp
1351–1357

Added llvm_unreachable.

Harbormaster completed remote builds in B138565: Diff 393338.Dec 9 2021, 5:59 PM
morehouse accepted this revision.Dec 10 2021, 7:32 AM
morehouse added inline comments.
llvm/lib/Target/X86/X86MCInstLower.cpp
1351–1357

Let's move this CHECK to right after the call to getAddressSanitizerParams. And let's hard code Op as "add".

1351–1358
This revision is now accepted and ready to land.Dec 10 2021, 7:32 AM
vitalybuka accepted this revision.Dec 10 2021, 3:07 PM
kstoimenov updated this revision to Diff 393608.Dec 10 2021, 3:34 PM

After pull.

kstoimenov updated this revision to Diff 393610.Dec 10 2021, 3:36 PM

Removed or test.

kstoimenov updated this revision to Diff 393617.Dec 10 2021, 3:53 PM

Added the test for or back.

This revision was landed with ongoing or failed builds.Dec 10 2021, 4:03 PM
Closed by commit rGdb124df49506: [ASan] Replace IR based callbacks with shared assembly code callbacks. (authored by kstoimenov). · Explain Why
This revision was automatically updated to reflect the committed changes.
kstoimenov added a commit: rGdb124df49506: [ASan] Replace IR based callbacks with shared assembly code callbacks..
kstoimenov added a reverting change: D115564: Revert "[ASan] Replace IR based callbacks with shared assembly code callbacks.".Dec 10 2021, 4:40 PM
Harbormaster completed remote builds in B138753: Diff 393617.Dec 10 2021, 4:40 PM
kstoimenov added a reverting change: rGa55e51f9a64c: Revert "[ASan] Replace IR based callbacks with shared assembly code callbacks.".Dec 10 2021, 4:42 PM
kstoimenov reopened this revision.Dec 10 2021, 4:43 PM
This revision is now accepted and ready to land.Dec 10 2021, 4:43 PM
kstoimenov updated this revision to Diff 393906.Dec 13 2021, 8:18 AM

Used report_fatal_error.

This revision was landed with ongoing or failed builds.Dec 13 2021, 8:33 AM
Closed by commit rG89577be8958f: [ASan] Replace IR based callbacks with shared assembly code callbacks. (authored by kstoimenov). · Explain Why
This revision was automatically updated to reflect the committed changes.
kstoimenov added a commit: rG89577be8958f: [ASan] Replace IR based callbacks with shared assembly code callbacks..
Harbormaster completed remote builds in B138978: Diff 393906.Dec 13 2021, 9:10 AM
kstoimenov reopened this revision.Dec 13 2021, 4:35 PM
This revision is now accepted and ready to land.Dec 13 2021, 4:35 PM
kstoimenov closed this revision.Dec 14 2021, 2:10 PM

Revision Contents

PathSize
llvm/
lib/
Target/
X86/
14 lines
2 lines
237 lines
test/
CodeGen/
X86/
194 lines
249 lines

Diff 393906

llvm/lib/Target/X86/X86AsmPrinter.h

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Linesclass LLVM_LIBRARY_VISIBILITY X86AsmPrinter : public AsmPrinter {
void LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI, X86MCInstLower &MCIL); void LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
void LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI, void LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI,
X86MCInstLower &MCIL); X86MCInstLower &MCIL);
void LowerFENTRY_CALL(const MachineInstr &MI, X86MCInstLower &MCIL); void LowerFENTRY_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
// Address sanitizer specific lowering for X86. // Address sanitizer specific lowering for X86.
void LowerASAN_CHECK_MEMACCESS(const MachineInstr &MI); void LowerASAN_CHECK_MEMACCESS(const MachineInstr &MI);
void emitAsanMemaccessSymbols(Module &M);
void emitAsanMemaccessPartial(Module &M, unsigned Reg,
const ASanAccessInfo &AccessInfo,
MCSubtargetInfo &STI);
void emitAsanMemaccessFull(Module &M, unsigned Reg,
const ASanAccessInfo &AccessInfo,
MCSubtargetInfo &STI);
void emitAsanReportError(Module &M, unsigned Reg,
const ASanAccessInfo &AccessInfo,
MCSubtargetInfo &STI);
typedef std::tuple<unsigned /*Reg*/, uint32_t /*AccessInfo*/>
AsanMemaccessTuple;
std::map<AsanMemaccessTuple, MCSymbol *> AsanMemaccessSymbols;
// Choose between emitting .seh_ directives and .cv_fpo_ directives. // Choose between emitting .seh_ directives and .cv_fpo_ directives.
void EmitSEHInstruction(const MachineInstr *MI); void EmitSEHInstruction(const MachineInstr *MI);
void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override; void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override;
void PrintOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O); void PrintOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
void PrintModifiedOperand(const MachineInstr *MI, unsigned OpNo, void PrintModifiedOperand(const MachineInstr *MI, unsigned OpNo,
raw_ostream &O, const char *Modifier); raw_ostream &O, const char *Modifier);
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86AsmPrinter.cpp

Show First 20 Lines • Show All 748 Lines • ▼ Show 20 Lines if (!Stubs.empty()) {
Stubs.clear(); Stubs.clear();
OutStreamer.AddBlankLine(); OutStreamer.AddBlankLine();
} }
} }
void X86AsmPrinter::emitEndOfAsmFile(Module &M) { void X86AsmPrinter::emitEndOfAsmFile(Module &M) {
const Triple &TT = TM.getTargetTriple(); const Triple &TT = TM.getTargetTriple();
emitAsanMemaccessSymbols(M);
if (TT.isOSBinFormatMachO()) { if (TT.isOSBinFormatMachO()) {
// Mach-O uses non-lazy symbol stubs to encode per-TU information into // Mach-O uses non-lazy symbol stubs to encode per-TU information into
// global table for symbol lookup. // global table for symbol lookup.
emitNonLazyStubs(MMI, *OutStreamer); emitNonLazyStubs(MMI, *OutStreamer);
// Emit stack and fault map information. // Emit stack and fault map information.
emitStackMaps(SM); emitStackMaps(SM);
FM.serializeToFaultMapSection(); FM.serializeToFaultMapSection();
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86MCInstLower.cpp

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
#include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCSymbolELF.h" #include "llvm/MC/MCSymbolELF.h"
#include "llvm/MC/TargetRegistry.h" #include "llvm/MC/TargetRegistry.h"
#include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Transforms/Instrumentation/AddressSanitizer.h" #include "llvm/Transforms/Instrumentation/AddressSanitizer.h"
#include "llvm/Transforms/Instrumentation/AddressSanitizerCommon.h" #include "llvm/Transforms/Instrumentation/AddressSanitizerCommon.h"
#include <string>
using namespace llvm; using namespace llvm;
namespace { namespace {
/// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst. /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
class X86MCInstLower { class X86MCInstLower {
MCContext &Ctx; MCContext &Ctx;
▲ Show 20 Lines • Show All 1,272 Lines • ▼ Show 20 Lines
void X86AsmPrinter::LowerASAN_CHECK_MEMACCESS(const MachineInstr &MI) { void X86AsmPrinter::LowerASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
// FIXME: Make this work on non-ELF. // FIXME: Make this work on non-ELF.
if (!TM.getTargetTriple().isOSBinFormatELF()) { if (!TM.getTargetTriple().isOSBinFormatELF()) {
report_fatal_error("llvm.asan.check.memaccess only supported on ELF"); report_fatal_error("llvm.asan.check.memaccess only supported on ELF");
return; return;
} }
unsigned Reg = MI.getOperand(0).getReg().id(); const auto &Reg = MI.getOperand(0).getReg();
ASanAccessInfo AccessInfo(MI.getOperand(1).getImm()); ASanAccessInfo AccessInfo(MI.getOperand(1).getImm());
MCSymbol *&Sym =
AsanMemaccessSymbols[AsanMemaccessTuple(Reg, AccessInfo.Packed)];
if (!Sym) {
std::string Name = AccessInfo.IsWrite ? "store" : "load";
std::string SymName = "__asan_check_" + Name +
utostr(1ULL << AccessInfo.AccessSizeIndex) + "_rn" +
utostr(Reg);
Sym = OutContext.getOrCreateSymbol(SymName);
}
EmitAndCountInstruction(
MCInstBuilder(X86::CALL64pcrel32)
.addExpr(MCSymbolRefExpr::create(Sym, OutContext)));
}
void X86AsmPrinter::emitAsanMemaccessPartial(Module &M, unsigned Reg,
const ASanAccessInfo &AccessInfo,
MCSubtargetInfo &STI) {
assert(AccessInfo.AccessSizeIndex == 0 || AccessInfo.AccessSizeIndex == 1 ||
AccessInfo.AccessSizeIndex == 2);
assert(Reg != X86::R10);
assert(Reg != X86::R11);
uint64_t ShadowBase;
int MappingScale;
bool OrShadowOffset;
getAddressSanitizerParams(
Triple(M.getTargetTriple()), M.getDataLayout().getPointerSizeInBits(),
AccessInfo.CompileKernel, &ShadowBase, &MappingScale, &OrShadowOffset);
OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr)
.addReg(X86::R10)
.addReg(X86::NoRegister + Reg),
STI);
OutStreamer->emitInstruction(MCInstBuilder(X86::SHR64ri)
.addReg(X86::R10)
.addReg(X86::R10)
.addImm(MappingScale),
STI);
if (OrShadowOffset) {
OutStreamer->emitInstruction(MCInstBuilder(X86::OR64ri32)
.addReg(X86::R10)
.addReg(X86::R10)
.addImm(ShadowBase),
STI);
OutStreamer->emitInstruction(MCInstBuilder(X86::MOV8rm)
.addReg(X86::R10B)
.addReg(X86::R10)
.addImm(1)
.addReg(X86::NoRegister)
.addImm(0)
.addReg(X86::NoRegister),
STI);
OutStreamer->emitInstruction(
MCInstBuilder(X86::TEST8rr).addReg(X86::R10B).addReg(X86::R10B), STI);
} else {
OutStreamer->emitInstruction(MCInstBuilder(X86::MOVSX32rm8)
.addReg(X86::R10D)
.addReg(X86::R10)
.addImm(1)
.addReg(X86::NoRegister)
.addImm(ShadowBase)
.addReg(X86::NoRegister),
STI);
OutStreamer->emitInstruction(
MCInstBuilder(X86::TEST32rr).addReg(X86::R10D).addReg(X86::R10D), STI);
}
MCSymbol *AdditionalCheck = OutContext.createTempSymbol();
OutStreamer->emitInstruction(
MCInstBuilder(X86::JCC_1)
.addExpr(MCSymbolRefExpr::create(AdditionalCheck, OutContext))
.addImm(X86::COND_NE),
STI);
MCSymbol *ReturnSym = OutContext.createTempSymbol();
OutStreamer->emitLabel(ReturnSym);
OutStreamer->emitInstruction(MCInstBuilder(getRetOpcode(*Subtarget)), STI);
// Shadow byte is non-zero so we need to perform additional checks.
OutStreamer->emitLabel(AdditionalCheck);
OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr)
.addReg(X86::R11)
.addReg(X86::NoRegister + Reg),
STI);
const size_t Granularity = 1ULL << MappingScale;
OutStreamer->emitInstruction(MCInstBuilder(X86::AND32ri8)
.addReg(X86::NoRegister)
.addReg(X86::R11D)
.addImm(Granularity - 1),
STI);
if (AccessInfo.AccessSizeIndex == 1) {
OutStreamer->emitInstruction(MCInstBuilder(X86::ADD32ri8)
.addReg(X86::NoRegister)
.addReg(X86::R11D)
.addImm(1),
STI);
} else if (AccessInfo.AccessSizeIndex == 2) {
OutStreamer->emitInstruction(MCInstBuilder(X86::ADD32ri8)
.addReg(X86::NoRegister)
.addReg(X86::R11D)
.addImm(3),
STI);
}
OutStreamer->emitInstruction(
MCInstBuilder(X86::CMP32rr).addReg(X86::R11D).addReg(X86::R10D).addImm(1),
STI);
OutStreamer->emitInstruction(
MCInstBuilder(X86::JCC_1)
.addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext))
.addImm(X86::COND_L),
STI);
emitAsanReportError(M, Reg, AccessInfo, STI);
}
void X86AsmPrinter::emitAsanMemaccessFull(Module &M, unsigned Reg,
const ASanAccessInfo &AccessInfo,
MCSubtargetInfo &STI) {
assert(AccessInfo.AccessSizeIndex == 3 || AccessInfo.AccessSizeIndex == 4);
assert(Reg != X86::R10);
assert(Reg != X86::R11);
uint64_t ShadowBase; uint64_t ShadowBase;
int MappingScale; int MappingScale;
bool OrShadowOffset; bool OrShadowOffset;
getAddressSanitizerParams( getAddressSanitizerParams(Triple(TM.getTargetTriple()), 64,
Triple(M.getTargetTriple()), M.getDataLayout().getPointerSizeInBits(), AccessInfo.CompileKernel, &ShadowBase,
AccessInfo.CompileKernel, &ShadowBase, &MappingScale, &OrShadowOffset); &MappingScale, &OrShadowOffset);
OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr)
.addReg(X86::R10)
.addReg(X86::NoRegister + Reg),
STI);
OutStreamer->emitInstruction(MCInstBuilder(X86::SHR64ri)
.addReg(X86::R10)
.addReg(X86::R10)
.addImm(MappingScale),
STI);
if (OrShadowOffset) {
OutStreamer->emitInstruction(MCInstBuilder(X86::OR64ri32)
.addReg(X86::R10)
.addReg(X86::R10)
.addImm(ShadowBase),
STI);
auto OpCode = AccessInfo.AccessSizeIndex == 3 ? X86::CMP8mi : X86::CMP16mi8;
OutStreamer->emitInstruction(MCInstBuilder(OpCode)
.addReg(X86::R10)
.addImm(1)
.addReg(X86::NoRegister)
.addImm(0)
.addReg(X86::NoRegister)
.addImm(0),
STI);
} else {
auto OpCode = AccessInfo.AccessSizeIndex == 3 ? X86::CMP8mi : X86::CMP16mi8;
OutStreamer->emitInstruction(MCInstBuilder(OpCode)
.addReg(X86::R10)
.addImm(1)
.addReg(X86::NoRegister)
.addImm(ShadowBase)
.addReg(X86::NoRegister)
.addImm(0),
STI);
}
MCSymbol *ReportCode = OutContext.createTempSymbol();
OutStreamer->emitInstruction(
MCInstBuilder(X86::JCC_1)
.addExpr(MCSymbolRefExpr::create(ReportCode, OutContext))
.addImm(X86::COND_NE),
STI);
MCSymbol *ReturnSym = OutContext.createTempSymbol();
OutStreamer->emitLabel(ReturnSym);
OutStreamer->emitInstruction(MCInstBuilder(getRetOpcode(*Subtarget)), STI);
OutStreamer->emitLabel(ReportCode);
emitAsanReportError(M, Reg, AccessInfo, STI);
}
void X86AsmPrinter::emitAsanReportError(Module &M, unsigned Reg,
const ASanAccessInfo &AccessInfo,
MCSubtargetInfo &STI) {
std::string Name = AccessInfo.IsWrite ? "store" : "load"; std::string Name = AccessInfo.IsWrite ? "store" : "load";
MCSymbol *ReportError = OutContext.getOrCreateSymbol( std::string Op = OrShadowOffset ? "or" : "add";
"__asan_report_" + Name + utostr(1ULL << AccessInfo.AccessSizeIndex)); std::string SymName = "__asan_check_" + Name + "_" + Op + "_" +
OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr) utostr(1ULL << AccessInfo.AccessSizeIndex) + "_" +
.addReg(X86::RDI) TM.getMCRegisterInfo()->getName(Reg.asMCReg());
.addReg(X86::NoRegister + Reg), if (OrShadowOffset)
STI); report_fatal_error(
OutStreamer->emitInstruction( "OrShadowOffset is not supported with optimized callbacks");
morehouseUnsubmitted
Not Done
ReplyInline Actions

We didn't implement OR callbacks, did we? Probably we should not emit calls to them.

morehouse: We didn't implement OR callbacks, did we? Probably we should not emit calls to them.
kstoimenovAuthorUnsubmitted
Done
ReplyInline Actions

Added llvm_unreachable.

kstoimenov: Added llvm_unreachable.
morehouseUnsubmitted
Not Done
ReplyInline Actions

Let's move this CHECK to right after the call to getAddressSanitizerParams. And let's hard code Op as "add".

morehouse: Let's move this CHECK to right after the call to `getAddressSanitizerParams`. And let's hard…
MCInstBuilder(X86::JMP_4)
.addExpr(MCSymbolRefExpr::create(ReportError, MCSymbolRefExpr::VK_PLT,
OutContext)),
STI);
}
void X86AsmPrinter::emitAsanMemaccessSymbols(Module &M) {
if (AsanMemaccessSymbols.empty())
return;
const Triple &TT = TM.getTargetTriple();
assert(TT.isOSBinFormatELF());
std::unique_ptr<MCSubtargetInfo> STI(
TM.getTarget().createMCSubtargetInfo(TT.str(), "", ""));
assert(STI && "Unable to create subtarget info");
for (auto &P : AsanMemaccessSymbols) {
MCSymbol *Sym = P.second;
OutStreamer->SwitchSection(OutContext.getELFSection(
".text.hot", ELF::SHT_PROGBITS,
ELF::SHF_EXECINSTR | ELF::SHF_ALLOC | ELF::SHF_GROUP, 0, Sym->getName(),
/*IsComdat=*/true));
OutStreamer->emitSymbolAttribute(Sym, MCSA_ELF_TypeFunction);
OutStreamer->emitSymbolAttribute(Sym, MCSA_Weak);
OutStreamer->emitSymbolAttribute(Sym, MCSA_Hidden);
OutStreamer->emitLabel(Sym);
unsigned Reg = std::get<0>(P.first);
ASanAccessInfo AccessInfo(std::get<1>(P.first));
morehouseUnsubmitted
Not Done
ReplyInline Actions
std::string Name = AccessInfo.IsWrite ? "store" : "load";
- std::string Op = OrShadowOffset ? "or" : "add";
- std::string SymName = "__asan_check_" + Name + "_" + Op + "_" +
+ std::string SymName = "__asan_check_" + Name + "_add_" +
utostr(1ULL << AccessInfo.AccessSizeIndex) + "_" +
morehouse:
if (AccessInfo.AccessSizeIndex < 3) { EmitAndCountInstruction(
emitAsanMemaccessPartial(M, Reg, AccessInfo, *STI); MCInstBuilder(X86::CALL64pcrel32)
} else { .addExpr(MCSymbolRefExpr::create(
emitAsanMemaccessFull(M, Reg, AccessInfo, *STI); OutContext.getOrCreateSymbol(SymName), OutContext)));
}
}
} }
void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI, void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
X86MCInstLower &MCIL) { X86MCInstLower &MCIL) {
// PATCHABLE_OP minsize, opcode, operands // PATCHABLE_OP minsize, opcode, operands
NoAutoPaddingScope NoPadScope(*OutStreamer); NoAutoPaddingScope NoPadScope(*OutStreamer);
▲ Show 20 Lines • Show All 1,303 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/asan-check-memaccess-add.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define void @load1(i8* nocapture readonly %x) { define void @load1(i8* nocapture readonly %x) {
; CHECK: pushq %rax ; CHECK: pushq %rax
; CHECK-NOT: push %rbp ; CHECK-NOT: push %rbp
; CHECK: callq __asan_check_load1_rn[[RN1:.*]] ; CHECK: callq __asan_check_load_add_1_[[REG1:.*]]
; CHECK: callq __asan_check_store1_rn[[RN1]] ; CHECK: callq __asan_check_store_add_1_[[REG1]]
; CHECK-NOT: pop %rbp ; CHECK-NOT: pop %rbp
; CHECK: popq %rax ; CHECK: popq %rax
call void @llvm.asan.check.memaccess(i8* %x, i32 0) call void @llvm.asan.check.memaccess(i8* %x, i32 0)
call void @llvm.asan.check.memaccess(i8* %x, i32 32) call void @llvm.asan.check.memaccess(i8* %x, i32 32)
ret void ret void
} }
define void @load2(i16* nocapture readonly %x) { define void @load2(i16* nocapture readonly %x) {
; CHECK: pushq %rax ; CHECK: pushq %rax
; CHECK-NOT: push %rbp ; CHECK-NOT: push %rbp
; CHECK: callq __asan_check_load2_rn[[RN2:.*]] ; CHECK: callq __asan_check_load_add_2_[[REG2:.*]]
; CHECK: callq __asan_check_store2_rn[[RN2]] ; CHECK: callq __asan_check_store_add_2_[[REG2]]
; CHECK-NOT: pop %rbp ; CHECK-NOT: pop %rbp
; CHECK: popq %rax ; CHECK: popq %rax
%1 = ptrtoint i16* %x to i64 %1 = ptrtoint i16* %x to i64
%2 = bitcast i16* %x to i8* %2 = bitcast i16* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 2) call void @llvm.asan.check.memaccess(i8* %2, i32 2)
call void @llvm.asan.check.memaccess(i8* %2, i32 34) call void @llvm.asan.check.memaccess(i8* %2, i32 34)
ret void ret void
} }
define void @load4(i32* nocapture readonly %x) { define void @load4(i32* nocapture readonly %x) {
; CHECK: pushq %rax ; CHECK: pushq %rax
; CHECK-NOT: push %rbp ; CHECK-NOT: push %rbp
; CHECK: callq __asan_check_load4_rn[[RN4:.*]] ; CHECK: callq __asan_check_load_add_4_[[REG4:.*]]
; CHECK: callq __asan_check_store4_rn[[RN4]] ; CHECK: callq __asan_check_store_add_4_[[REG4]]
; CHECK-NOT: pop %rbp ; CHECK-NOT: pop %rbp
; CHECK: popq %rax ; CHECK: popq %rax
%1 = ptrtoint i32* %x to i64 %1 = ptrtoint i32* %x to i64
%2 = bitcast i32* %x to i8* %2 = bitcast i32* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 4) call void @llvm.asan.check.memaccess(i8* %2, i32 4)
call void @llvm.asan.check.memaccess(i8* %2, i32 36) call void @llvm.asan.check.memaccess(i8* %2, i32 36)
ret void ret void
} }
define void @load8(i64* nocapture readonly %x) { define void @load8(i64* nocapture readonly %x) {
; CHECK: pushq %rax ; CHECK: pushq %rax
; CHECK-NOT: push %rbp ; CHECK-NOT: push %rbp
; CHECK: callq __asan_check_load8_rn[[RN8:.*]] ; CHECK: callq __asan_check_load_add_8_[[REG8:.*]]
; CHECK: callq __asan_check_store8_rn[[RN8]] ; CHECK: callq __asan_check_store_add_8_[[REG8]]
; CHECK-NOT: pop %rbp ; CHECK-NOT: pop %rbp
; CHECK: popq %rax ; CHECK: popq %rax
%1 = ptrtoint i64* %x to i64 %1 = ptrtoint i64* %x to i64
%2 = bitcast i64* %x to i8* %2 = bitcast i64* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 6) call void @llvm.asan.check.memaccess(i8* %2, i32 6)
call void @llvm.asan.check.memaccess(i8* %2, i32 38) call void @llvm.asan.check.memaccess(i8* %2, i32 38)
ret void ret void
} }
define void @load16(i128* nocapture readonly %x) { define void @load16(i128* nocapture readonly %x) {
; CHECK: pushq %rax ; CHECK: pushq %rax
; CHECK-NOT: push %rbp ; CHECK-NOT: push %rbp
; CHECK: callq __asan_check_load16_rn[[RN16:.*]] ; CHECK: callq __asan_check_load_add_16_[[REG16:.*]]
; CHECK: callq __asan_check_store16_rn[[RN16]] ; CHECK: callq __asan_check_store_add_16_[[REG16]]
; CHECK-NOT: pop %rbp ; CHECK-NOT: pop %rbp
; CHECK: popq %rax ; CHECK: popq %rax
%1 = ptrtoint i128* %x to i64 %1 = ptrtoint i128* %x to i64
%2 = bitcast i128* %x to i8* %2 = bitcast i128* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 8) call void @llvm.asan.check.memaccess(i8* %2, i32 8)
call void @llvm.asan.check.memaccess(i8* %2, i32 40) call void @llvm.asan.check.memaccess(i8* %2, i32 40)
ret void ret void
} }
; CHECK: .type __asan_check_load1_rn[[RN1]],@function
; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]]
; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]]
; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: movsbl 2147450880(%r10), %r10d
; CHECK-NEXT: testl %r10d, %r10d
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: movq [[REG]], %r11
; CHECK-NEXT: andl $7, %r11d
; CHECK-NEXT: cmpl %r10d, %r11d
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load1
; CHECK: .type __asan_check_load2_rn[[RN2]],@function
; CHECK-NEXT: .weak __asan_check_load2_rn[[RN2]]
; CHECK-NEXT: .hidden __asan_check_load2_rn[[RN2]]
; CHECK-NEXT: __asan_check_load2_rn[[RN2]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: movsbl 2147450880(%r10), %r10d
; CHECK-NEXT: testl %r10d, %r10d
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: movq [[REG]], %r11
; CHECK-NEXT: andl $7, %r11d
; CHECK-NEXT: addl $1, %r11d
; CHECK-NEXT: cmpl %r10d, %r11d
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load2
; CHECK: .type __asan_check_load4_rn[[RN4]],@function
; CHECK-NEXT: .weak __asan_check_load4_rn[[RN4]]
; CHECK-NEXT: .hidden __asan_check_load4_rn[[RN4]]
; CHECK-NEXT: __asan_check_load4_rn[[RN4]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: movsbl 2147450880(%r10), %r10d
; CHECK-NEXT: testl %r10d, %r10d
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: movq [[REG]], %r11
; CHECK-NEXT: andl $7, %r11d
; CHECK-NEXT: addl $3, %r11d
; CHECK-NEXT: cmpl %r10d, %r11d
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load4
; CHECK: .type __asan_check_load8_rn[[RN8]],@function
; CHECK-NEXT: .weak __asan_check_load8_rn[[RN8]]
; CHECK-NEXT: .hidden __asan_check_load8_rn[[RN8]]
; CHECK-NEXT: __asan_check_load8_rn[[RN8]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: cmpb $0, 2147450880(%r10)
; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load8
; CHECK: .type __asan_check_load16_rn[[RN16]],@function
; CHECK-NEXT: .weak __asan_check_load16_rn[[RN16]]
; CHECK-NEXT: .hidden __asan_check_load16_rn[[RN16]]
; CHECK-NEXT: __asan_check_load16_rn[[RN16]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: cmpw $0, 2147450880(%r10)
; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load16
; CHECK: .type __asan_check_store1_rn[[RN1]],@function
; CHECK-NEXT: .weak __asan_check_store1_rn[[RN1]]
; CHECK-NEXT: .hidden __asan_check_store1_rn[[RN1]]
; CHECK-NEXT: __asan_check_store1_rn[[RN1]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: movsbl 2147450880(%r10), %r10d
; CHECK-NEXT: testl %r10d, %r10d
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: movq [[REG]], %r11
; CHECK-NEXT: andl $7, %r11d
; CHECK-NEXT: cmpl %r10d, %r11d
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store1@PLT
; CHECK: .type __asan_check_store2_rn[[RN2]],@function
; CHECK-NEXT: .weak __asan_check_store2_rn[[RN2]]
; CHECK-NEXT: .hidden __asan_check_store2_rn[[RN2]]
; CHECK-NEXT: __asan_check_store2_rn[[RN2]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: movsbl 2147450880(%r10), %r10d
; CHECK-NEXT: testl %r10d, %r10d
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: movq [[REG]], %r11
; CHECK-NEXT: andl $7, %r11d
; CHECK-NEXT: addl $1, %r11d
; CHECK-NEXT: cmpl %r10d, %r11d
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store2@PLT
; CHECK: .type __asan_check_store4_rn[[RN4]],@function
; CHECK-NEXT: .weak __asan_check_store4_rn[[RN4]]
; CHECK-NEXT: .hidden __asan_check_store4_rn[[RN4]]
; CHECK-NEXT: __asan_check_store4_rn[[RN4]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: movsbl 2147450880(%r10), %r10d
; CHECK-NEXT: testl %r10d, %r10d
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: movq [[REG]], %r11
; CHECK-NEXT: andl $7, %r11d
; CHECK-NEXT: addl $3, %r11d
; CHECK-NEXT: cmpl %r10d, %r11d
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store4@PLT
; CHECK: .type __asan_check_store8_rn[[RN8]],@function
; CHECK-NEXT: .weak __asan_check_store8_rn[[RN8]]
; CHECK-NEXT: .hidden __asan_check_store8_rn[[RN8]]
; CHECK-NEXT: __asan_check_store8_rn[[RN8]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: cmpb $0, 2147450880(%r10)
; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store8@PLT
; CHECK: .type __asan_check_store16_rn[[RN16]],@function
; CHECK-NEXT: .weak __asan_check_store16_rn[[RN16]]
; CHECK-NEXT: .hidden __asan_check_store16_rn[[RN16]]
; CHECK-NEXT: __asan_check_store16_rn[[RN16]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: cmpw $0, 2147450880(%r10)
; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store16@PLT
declare void @llvm.asan.check.memaccess(i8*, i32 immarg) declare void @llvm.asan.check.memaccess(i8*, i32 immarg)

llvm/test/CodeGen/X86/asan-check-memaccess-or.ll

; RUN: llc < %s | FileCheck %s ; XFAIL: *
; RUN: llc < %s
target triple = "x86_64-pc-win" target triple = "x86_64-pc-win"
define void @load1(i8* nocapture readonly %x) { define void @load1(i8* nocapture readonly %x) {
; CHECK: pushq %rax
; CHECK-NOT: push %rbp
; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
; CHECK: callq __asan_check_store1_rn[[RN1]]
; CHECK-NOT: pop %rbp
; CHECK: popq %rax
call void @llvm.asan.check.memaccess(i8* %x, i32 0) call void @llvm.asan.check.memaccess(i8* %x, i32 0)
call void @llvm.asan.check.memaccess(i8* %x, i32 32)
ret void ret void
} }
define void @load2(i16* nocapture readonly %x) {
; CHECK: pushq %rax
; CHECK-NOT: push %rbp
; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
; CHECK: callq __asan_check_store2_rn[[RN2]]
; CHECK-NOT: pop %rbp
; CHECK: popq %rax
%1 = ptrtoint i16* %x to i64
%2 = bitcast i16* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 2)
call void @llvm.asan.check.memaccess(i8* %2, i32 34)
ret void
}
define void @load4(i32* nocapture readonly %x) {
; CHECK: pushq %rax
; CHECK-NOT: push %rbp
; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
; CHECK: callq __asan_check_store4_rn[[RN4]]
; CHECK-NOT: pop %rbp
; CHECK: popq %rax
%1 = ptrtoint i32* %x to i64
%2 = bitcast i32* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 4)
call void @llvm.asan.check.memaccess(i8* %2, i32 36)
ret void
}
define void @load8(i64* nocapture readonly %x) {
; CHECK: pushq %rax
; CHECK-NOT: push %rbp
; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
; CHECK: callq __asan_check_store8_rn[[RN8]]
; CHECK-NOT: pop %rbp
; CHECK: popq %rax
%1 = ptrtoint i64* %x to i64
%2 = bitcast i64* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 6)
call void @llvm.asan.check.memaccess(i8* %2, i32 38)
ret void
}
define void @load16(i128* nocapture readonly %x) {
; CHECK: pushq %rax
; CHECK-NOT: push %rbp
; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
; CHECK: callq __asan_check_store16_rn[[RN16]]
; CHECK-NOT: pop %rbp
; CHECK: popq %rax
%1 = ptrtoint i128* %x to i64
%2 = bitcast i128* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 8)
call void @llvm.asan.check.memaccess(i8* %2, i32 40)
ret void
}
; CHECK: .type __asan_check_load1_rn[[RN1]],@function
; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]]
; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]]
; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: orq $17592186044416, %r10{{.*}}
; CHECK-NEXT: movb (%r10), %r10b
; CHECK-NEXT: testb %r10b, %r10b
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: movq [[REG]], %r11
; CHECK-NEXT: andl $7, %r11d
; CHECK-NEXT: cmpl %r10d, %r11d
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load1
; CHECK: .type __asan_check_load2_rn[[RN2]],@function
; CHECK-NEXT: .weak __asan_check_load2_rn[[RN2]]
; CHECK-NEXT: .hidden __asan_check_load2_rn[[RN2]]
; CHECK-NEXT: __asan_check_load2_rn[[RN2]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: orq $17592186044416, %r10{{.*}}
; CHECK-NEXT: movb (%r10), %r10b
; CHECK-NEXT: testb %r10b, %r10b
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: movq [[REG]], %r11
; CHECK-NEXT: andl $7, %r11d
; CHECK-NEXT: addl $1, %r11d
; CHECK-NEXT: cmpl %r10d, %r11d
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load2
; CHECK: .type __asan_check_load4_rn[[RN4]],@function
; CHECK-NEXT: .weak __asan_check_load4_rn[[RN4]]
; CHECK-NEXT: .hidden __asan_check_load4_rn[[RN4]]
; CHECK-NEXT: __asan_check_load4_rn[[RN4]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: orq $17592186044416, %r10{{.*}}
; CHECK-NEXT: movb (%r10), %r10b
; CHECK-NEXT: testb %r10b, %r10b
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: movq [[REG]], %r11
; CHECK-NEXT: andl $7, %r11d
; CHECK-NEXT: addl $3, %r11d
; CHECK-NEXT: cmpl %r10d, %r11d
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load4
; CHECK: .type __asan_check_load8_rn[[RN8]],@function
; CHECK-NEXT: .weak __asan_check_load8_rn[[RN8]]
; CHECK-NEXT: .hidden __asan_check_load8_rn[[RN8]]
; CHECK-NEXT: __asan_check_load8_rn[[RN8]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: orq $17592186044416, %r10{{.*}}
; CHECK-NEXT: cmpb $0, (%r10)
; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load8
; CHECK: .type __asan_check_load16_rn[[RN16]],@function
; CHECK-NEXT: .weak __asan_check_load16_rn[[RN16]]
; CHECK-NEXT: .hidden __asan_check_load16_rn[[RN16]]
; CHECK-NEXT: __asan_check_load16_rn[[RN16]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: orq $17592186044416, %r10{{.*}}
; CHECK-NEXT: cmpw $0, (%r10)
; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_load16
; CHECK: .type __asan_check_store1_rn[[RN1]],@function
; CHECK-NEXT: .weak __asan_check_store1_rn[[RN1]]
; CHECK-NEXT: .hidden __asan_check_store1_rn[[RN1]]
; CHECK-NEXT: __asan_check_store1_rn[[RN1]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: orq $17592186044416, %r10
; CHECK-NEXT: movb (%r10), %r10b
; CHECK-NEXT: testb %r10b, %r10b
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: movq [[REG]], %r11
; CHECK-NEXT: andl $7, %r11d
; CHECK-NEXT: cmpl %r10d, %r11d
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store1@PLT
; CHECK: .type __asan_check_store2_rn[[RN2]],@function
; CHECK-NEXT: .weak __asan_check_store2_rn[[RN2]]
; CHECK-NEXT: .hidden __asan_check_store2_rn[[RN2]]
; CHECK-NEXT: __asan_check_store2_rn[[RN2]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: orq $17592186044416, %r10
; CHECK-NEXT: movb (%r10), %r10b
; CHECK-NEXT: testb %r10b, %r10b
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: movq [[REG]], %r11
; CHECK-NEXT: andl $7, %r11d
; CHECK-NEXT: addl $1, %r11d
; CHECK-NEXT: cmpl %r10d, %r11d
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store2@PLT
; CHECK: .type __asan_check_store4_rn[[RN4]],@function
; CHECK-NEXT: .weak __asan_check_store4_rn[[RN4]]
; CHECK-NEXT: .hidden __asan_check_store4_rn[[RN4]]
; CHECK-NEXT: __asan_check_store4_rn[[RN4]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: orq $17592186044416, %r10
; CHECK-NEXT: movb (%r10), %r10b
; CHECK-NEXT: testb %r10b, %r10b
; CHECK-NEXT: jne [[EXTRA:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[EXTRA]]:
; CHECK-NEXT: movq [[REG]], %r11
; CHECK-NEXT: andl $7, %r11d
; CHECK-NEXT: addl $3, %r11d
; CHECK-NEXT: cmpl %r10d, %r11d
; CHECK-NEXT: jl [[RET]]
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store4@PLT
; CHECK: .type __asan_check_store8_rn[[RN8]],@function
; CHECK-NEXT: .weak __asan_check_store8_rn[[RN8]]
; CHECK-NEXT: .hidden __asan_check_store8_rn[[RN8]]
; CHECK-NEXT: __asan_check_store8_rn[[RN8]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: orq $17592186044416, %r10{{.*}}
; CHECK-NEXT: cmpb $0, (%r10)
; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store8@PLT
; CHECK: .type __asan_check_store16_rn[[RN16]],@function
; CHECK-NEXT: .weak __asan_check_store16_rn[[RN16]]
; CHECK-NEXT: .hidden __asan_check_store16_rn[[RN16]]
; CHECK-NEXT: __asan_check_store16_rn[[RN16]]:
; CHECK-NEXT: movq [[REG:.*]], %r10
; CHECK-NEXT: shrq $3, %r10
; CHECK-NEXT: orq $17592186044416, %r10{{.*}}
; CHECK-NEXT: cmpw $0, (%r10)
; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store16@PLT
declare void @llvm.asan.check.memaccess(i8*, i32 immarg) declare void @llvm.asan.check.memaccess(i8*, i32 immarg)