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Differential D115376

[AArch64][GlobalISel] Add regbankselect support for G_FMAXIMUM/G_FMINIMUM
ClosedPublic

Authored by paquette on Dec 8 2021, 12:31 PM.

Details

Reviewers
jroelofs
aemerson
Commits
rGafdec434d494: [AArch64][GlobalISel] Add regbankselect support for G_FMAXIMUM/G_FMINIMUM
Summary

These always use FPRs only.

Diff Detail

Unit TestsFailed

TimeTest
210 msx64 debian > LLVM.CodeGen/AArch64/GlobalISel::regbank-fmaximum.mir
210 msx64 debian > LLVM.CodeGen/AArch64/GlobalISel::regbank-fminimum.mir

Event Timeline

paquette created this revision.Dec 8 2021, 12:31 PM
Herald added subscribers: hiraditya, kristof.beyls, rovka. · View Herald TranscriptDec 8 2021, 12:31 PM
paquette requested review of this revision.Dec 8 2021, 12:31 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 8 2021, 12:31 PM
paquette added a parent revision: D115372: [AArch64][GlobalISel] Legalize scalar G_FMAXIMUM + G_FMINIMUM.Dec 8 2021, 12:31 PM
jroelofs accepted this revision.Dec 8 2021, 12:33 PM

LGTM

This revision is now accepted and ready to land.Dec 8 2021, 12:33 PM
paquette added a child revision: D115381: [AArch64][GlobalISel] Select scalar G_FMAXIMUM + G_FMINIMUM.Dec 8 2021, 12:45 PM
Harbormaster completed remote builds in B138240: Diff 392873.Dec 8 2021, 1:56 PM
This revision was landed with ongoing or failed builds.Dec 9 2021, 12:58 PM
Closed by commit rGafdec434d494: [AArch64][GlobalISel] Add regbankselect support for G_FMAXIMUM/G_FMINIMUM (authored by paquette). · Explain Why
This revision was automatically updated to reflect the committed changes.
paquette added a commit: rGafdec434d494: [AArch64][GlobalISel] Add regbankselect support for G_FMAXIMUM/G_FMINIMUM.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
GISel/
4 lines
test/
CodeGen/
AArch64/
GlobalISel/
64 lines
64 lines

Diff 392873

llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

Show First 20 Lines • Show All 424 Lines • ▼ Show 20 Linesstatic bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
case TargetOpcode::G_FSQRT: case TargetOpcode::G_FSQRT:
case TargetOpcode::G_FABS: case TargetOpcode::G_FABS:
case TargetOpcode::G_FEXP: case TargetOpcode::G_FEXP:
case TargetOpcode::G_FRINT: case TargetOpcode::G_FRINT:
case TargetOpcode::G_INTRINSIC_TRUNC: case TargetOpcode::G_INTRINSIC_TRUNC:
case TargetOpcode::G_INTRINSIC_ROUND: case TargetOpcode::G_INTRINSIC_ROUND:
case TargetOpcode::G_FMAXNUM: case TargetOpcode::G_FMAXNUM:
case TargetOpcode::G_FMINNUM: case TargetOpcode::G_FMINNUM:
case TargetOpcode::G_FMAXIMUM:
case TargetOpcode::G_FMINIMUM:
return true; return true;
} }
return false; return false;
} }
const RegisterBankInfo::InstructionMapping & const RegisterBankInfo::InstructionMapping &
AArch64RegisterBankInfo::getSameKindOfOperandsMapping( AArch64RegisterBankInfo::getSameKindOfOperandsMapping(
const MachineInstr &MI) const { const MachineInstr &MI) const {
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 LinesAArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_AND: case TargetOpcode::G_AND:
case TargetOpcode::G_OR: case TargetOpcode::G_OR:
case TargetOpcode::G_XOR: case TargetOpcode::G_XOR:
// Floating point ops. // Floating point ops.
case TargetOpcode::G_FADD: case TargetOpcode::G_FADD:
case TargetOpcode::G_FSUB: case TargetOpcode::G_FSUB:
case TargetOpcode::G_FMUL: case TargetOpcode::G_FMUL:
case TargetOpcode::G_FDIV: case TargetOpcode::G_FDIV:
case TargetOpcode::G_FMAXIMUM:
case TargetOpcode::G_FMINIMUM:
return getSameKindOfOperandsMapping(MI); return getSameKindOfOperandsMapping(MI);
case TargetOpcode::G_FPEXT: { case TargetOpcode::G_FPEXT: {
LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
return getInstructionMapping( return getInstructionMapping(
DefaultMappingID, /*Cost*/ 1, DefaultMappingID, /*Cost*/ 1,
getFPExtMapping(DstTy.getSizeInBits(), SrcTy.getSizeInBits()), getFPExtMapping(DstTy.getSizeInBits(), SrcTy.getSizeInBits()),
/*NumOperands*/ 2); /*NumOperands*/ 2);
▲ Show 20 Lines • Show All 389 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/regbank-fmaximum.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
...
---
name: direct
alignment: 4
legalized: true
body: |
bb.0:
; CHECK-LABEL: name: direct
; CHECK: %a:fpr(s32) = COPY $s0
; CHECK-NEXT: %b:fpr(s32) = COPY $s1
; CHECK-NEXT: %needs_fpr:fpr(s32) = G_FMAXIMUM %a, %b
; CHECK-NEXT: $s0 = COPY %needs_fpr(s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%a:_(s32) = COPY $s0
%b:_(s32) = COPY $s1
%needs_fpr:_(s32) = G_FMAXIMUM %a, %b
$s0 = COPY %needs_fpr(s32)
RET_ReallyLR implicit $s0
...
---
name: fed_by_load
alignment: 4
legalized: true
body: |
bb.0:
; CHECK-LABEL: name: fed_by_load
; CHECK: %ptr_a:gpr(p0) = COPY $x0
; CHECK-NEXT: %ptr_b:gpr(p0) = COPY $x1
; CHECK-NEXT: %a:fpr(s32) = G_LOAD %ptr_a(p0) :: (load (s32))
; CHECK-NEXT: %b:fpr(s32) = G_LOAD %ptr_a(p0) :: (load (s32))
; CHECK-NEXT: %needs_fpr:fpr(s32) = G_FMAXIMUM %a, %b
; CHECK-NEXT: $s0 = COPY %needs_fpr(s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%ptr_a:_(p0) = COPY $x0
%ptr_b:_(p0) = COPY $x1
%a:_(s32) = G_LOAD %ptr_a(p0) :: (load (s32))
%b:_(s32) = G_LOAD %ptr_a(p0) :: (load (s32))
%needs_fpr:_(s32) = G_FMAXIMUM %a, %b
$s0 = COPY %needs_fpr(s32)
RET_ReallyLR implicit $s0
...
---
name: create_copy
alignment: 4
legalized: true
body: |
bb.0:
; CHECK-LABEL: name: create_copy
; CHECK: %a:gpr(s32) = COPY $w0
; CHECK-NEXT: %b:gpr(s32) = COPY $w1
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY %a(s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s32) = COPY %b(s32)
; CHECK-NEXT: %needs_fpr:fpr(s32) = G_FMAXIMUM [[COPY]], [[COPY1]]
; CHECK-NEXT: $s0 = COPY %needs_fpr(s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%a:_(s32) = COPY $w0
%b:_(s32) = COPY $w1
%needs_fpr:_(s32) = G_FMAXIMUM %a, %b
$s0 = COPY %needs_fpr(s32)
RET_ReallyLR implicit $s0

llvm/test/CodeGen/AArch64/GlobalISel/regbank-fminimum.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
...
---
name: direct
alignment: 4
legalized: true
body: |
bb.0:
; CHECK-LABEL: name: direct
; CHECK: %a:fpr(s32) = COPY $s0
; CHECK-NEXT: %b:fpr(s32) = COPY $s1
; CHECK-NEXT: %needs_fpr:fpr(s32) = G_FMINIMUM %a, %b
; CHECK-NEXT: $s0 = COPY %needs_fpr(s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%a:_(s32) = COPY $s0
%b:_(s32) = COPY $s1
%needs_fpr:_(s32) = G_FMINIMUM %a, %b
$s0 = COPY %needs_fpr(s32)
RET_ReallyLR implicit $s0
...
---
name: fed_by_load
alignment: 4
legalized: true
body: |
bb.0:
; CHECK-LABEL: name: fed_by_load
; CHECK: %ptr_a:gpr(p0) = COPY $x0
; CHECK-NEXT: %ptr_b:gpr(p0) = COPY $x1
; CHECK-NEXT: %a:fpr(s32) = G_LOAD %ptr_a(p0) :: (load (s32))
; CHECK-NEXT: %b:fpr(s32) = G_LOAD %ptr_a(p0) :: (load (s32))
; CHECK-NEXT: %needs_fpr:fpr(s32) = G_FMINIMUM %a, %b
; CHECK-NEXT: $s0 = COPY %needs_fpr(s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%ptr_a:_(p0) = COPY $x0
%ptr_b:_(p0) = COPY $x1
%a:_(s32) = G_LOAD %ptr_a(p0) :: (load (s32))
%b:_(s32) = G_LOAD %ptr_a(p0) :: (load (s32))
%needs_fpr:_(s32) = G_FMINIMUM %a, %b
$s0 = COPY %needs_fpr(s32)
RET_ReallyLR implicit $s0
...
---
name: create_copy
alignment: 4
legalized: true
body: |
bb.0:
; CHECK-LABEL: name: create_copy
; CHECK: %a:gpr(s32) = COPY $w0
; CHECK-NEXT: %b:gpr(s32) = COPY $w1
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY %a(s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s32) = COPY %b(s32)
; CHECK-NEXT: %needs_fpr:fpr(s32) = G_FMINIMUM [[COPY]], [[COPY1]]
; CHECK-NEXT: $s0 = COPY %needs_fpr(s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%a:_(s32) = COPY $w0
%b:_(s32) = COPY $w1
%needs_fpr:_(s32) = G_FMINIMUM %a, %b
$s0 = COPY %needs_fpr(s32)
RET_ReallyLR implicit $s0