[NFC][llvm][Hexagon] Inclusive Terms remove uses of sanity in Hexagon taget

[ZarkoCA]

Summary

Most changes are rewording comments but there are some assertions that I rephrased.

[kparzysz]

Could you change the verification/validation to "basic correctness"? That would better reflect the intended meaning.

[ZarkoCA]

• Change verification/validation to basic correctness.

llvm/lib/Target/Hexagon/BitTracker.cpp

bool BT::RegisterCell::meet(const RegisterCell &RC, Register SelfR) {
   }
   return Changed;
 }
 
 // Insert the entire cell RC into the current cell at position given by M.
 BT::RegisterCell &BT::RegisterCell::insert(const BT::RegisterCell &RC,
       const BitMask &M) {
   uint16_t B = M.first(), E = M.last(), W = width();
-  // Sanity: M must be a valid mask for *this.
+  // M must be a valid mask for *this.
   assert(B < W && E < W);
-  // Sanity: the masked part of *this must have the same number of bits
+  // The masked part of *this must have the same number of bits
   // as the source.
   assert(B > E || E-B+1 == RC.width());      // B <= E  =>  E-B+1 = |RC|.
   assert(B <= E || E+(W-B)+1 == RC.width()); // E < B   =>  E+(W-B)+1 = |RC|.
   if (B <= E) {
     for (uint16_t i = 0; i <= E-B; ++i)
       Bits[i+B] = RC[i];
   } else {
     for (uint16_t i = 0; i < W-B; ++i)

llvm/lib/Target/Hexagon/HexagonBitTracker.cpp

 
 bool HexagonEvaluator::evaluate(const MachineInstr &MI,
                                 const CellMapType &Inputs,
                                 CellMapType &Outputs) const {
   using namespace Hexagon;
 
   unsigned NumDefs = 0;
 
-  // Sanity verification: there should not be any defs with subregisters.
+  // Verification check: there should not be any defs with subregisters.
   for (const MachineOperand &MO : MI.operands()) {
     if (!MO.isReg() || !MO.isDef())
       continue;
     NumDefs++;
     assert(MO.getSubReg() == 0);
   }
 
   if (NumDefs == 0)

llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp

if (MBB.getNumber() == -1)
       continue;
     for (MachineInstr &MI : MBB)
       collectInstr(MI);
   }
 }
 
 void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End,
       AssignmentMap &IMap) {
-  // Sanity check: make sure that all extenders in the range [Begin..End)
+  // Validation check: make sure that all extenders in the range [Begin..End)
   // share the same root ER.
   for (unsigned I = Begin; I != End; ++I)
     assert(ER == ExtRoot(Extenders[I].getOp()));
 
   // Construct the list of ranges, such that for each P in Ranges[I],
   // a register Reg = ER+P can be used in place of Extender[I]. If the
   // instruction allows, uses in the form of Reg+Off are considered
   // (here, Off = required_value - P).

llvm/lib/Target/Hexagon/HexagonGenInsert.cpp

 
 bool HexagonGenInsert::runOnMachineFunction(MachineFunction &MF) {
   if (skipFunction(MF.getFunction()))
     return false;
 
   bool Timing = OptTiming, TimingDetail = Timing && OptTimingDetail;
   bool Changed = false;
 
-  // Sanity check: one, but not both.
+  // Verify: one, but not both.
   assert(!OptSelectAll0 || !OptSelectHas0);
 
   IFMap.clear();
   BaseOrd.clear();
   CellOrd.clear();
 
   const auto &ST = MF.getSubtarget<HexagonSubtarget>();
   HII = ST.getInstrInfo();

llvm/lib/Target/Hexagon/HexagonGenMux.cpp

for (MachineInstr &MI : llvm::make_early_inc_range(B)) {
     MachineBasicBlock::iterator At = CanDown ? Def2 : Def1;
     ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2));
   }
 
   for (MuxInfo &MX : ML) {
     unsigned MxOpc = getMuxOpcode(*MX.SrcT, *MX.SrcF);
     if (!MxOpc)
       continue;
-    // Basic sanity check: since we are deleting instructions, validate the
+    // Basic validation check: since we are deleting instructions, validate the
     // iterators. There is a possibility that one of Def1 or Def2 is translated
     // to "mux" and being considered for other "mux" instructions.
     if (!MX.At->getParent() || !MX.Def1->getParent() || !MX.Def2->getParent())
       continue;
 
     MachineBasicBlock &B = *MX.At->getParent();
     const DebugLoc &DL = B.findDebugLoc(MX.At);
     auto NewMux = BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR)

llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp

if (NewOpc == 0) {
     RegisterSubReg PR = getPredRegFor(MI->getOperand(1));
     if (!isScalarPred(PR))
       return false;
     // This will skip the immediate argument when creating the predicate
     // version instruction.
     NumOps = 2;
   }
 
-  // Some sanity: check that def is in operand #0.
+  // Check that def is in operand #0.
   MachineOperand &Op0 = MI->getOperand(0);
   assert(Op0.isDef());
   RegisterSubReg OutR(Op0);
 
   // Don't use getPredRegFor, since it will create an association between
   // the argument and a created predicate register (i.e. it will insert a
   // copy if a new predicate register is created).
   const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;

llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp

 /// This function works on innermost loops first.  A loop can be converted
 /// if it is a counting loop; either a register value or an immediate.
 ///
 /// The code makes several assumptions about the representation of the loop
 /// in llvm.
 bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L,
                                                  bool &RecL0used,
                                                  bool &RecL1used) {
-  // This is just for sanity.
+  // This is just for validation..
   assert(L->getHeader() && "Loop without a header?");
 
   bool Changed = false;
   bool L0Used = false;
   bool L1Used = false;
 
   // Process nested loops first.
   for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) {

llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp

if (M >= 0) {
       M = (M & (SegLen-1)) + SegLen*OutIdx;
     }
     PackedMask[I] = M;
   }
 }
 
 static bool isPermutation(ArrayRef<int> Mask) {
   // Check by adding all numbers only works if there is no overflow.
-  assert(Mask.size() < 0x00007FFF && "Sanity failure");
+  assert(Mask.size() < 0x00007FFF && "Overflow failure");
   int Sum = 0;
   for (int Idx : Mask) {
     if (Idx == -1)
       return false;
     Sum += Idx;
   }
   int N = Mask.size();
   return 2*Sum == N*(N-1);
if (SegCount == 2) {
     // segment list instead.
     if (Seg0 == ~1u || Seg1 == ~1u) {
       if (Seg0 == Seg1) {
         Seg0 = SegList[0];
         Seg1 = SegList[1];
       } else if (Seg0 == ~1u) {
         Seg0 = SegList[0] != Seg1 ? SegList[0] : SegList[1];
       } else {
-        assert(Seg1 == ~1u); // Sanity
+        assert(Seg1 == ~1u);
         Seg1 = SegList[0] != Seg0 ? SegList[0] : SegList[1];
       }
     }
     assert(Seg0 != ~1u && Seg1 != ~1u);
 
     assert(Seg0 != Seg1 && "Expecting different segments");
     const SDLoc &dl(Results.InpNode);
     Results.push(Hexagon::A2_tfrsi, MVT::i32, {getConst32(SegLen, dl)});
if (Seg0 / 2 == Seg1 / 2) {
         auto Vs = (Seg0 == 0) ? std::make_pair(Va, Vb)  // AD
                               : std::make_pair(Vb, Va); // CB
         Results.push(Hexagon::V6_vmux, Ty, {Qt, Vs.first, Vs.second});
         Va = OpRef::res(Results.top());
         packSegmentMask(SM.Mask, {Seg0, Seg1}, SegLen, MaskH);
       } else {
         // BC or DA: this could be done via valign by SegLen.
         // Do nothing here, because valign (if possible) will be generated
-        // later on (make sure the Seg0 values are as expected, for sanity).
+        // later on (make sure the Seg0 values are as expected).
         assert(Seg0 == 1 || Seg0 == 3);
       }
     }
   }
 
   // Check if the arguments can be packed by valign(Va,Vb) or valign(Vb,Va).
 
   ShuffleMask SMH(MaskH);
OpRef HvxSelector::shuffs1(ShuffleMask SM, OpRef Va, ResultStack &Results) {
   assert(all_of(SM.Mask, [this](int M) { return M == -1 || M < int(HwLen); }));
 
   if (isIdentity(SM.Mask))
     return Va;
   if (isUndef(SM.Mask))
     return OpRef::undef(getSingleVT(MVT::i8));
 
   unsigned HalfLen = HwLen / 2;
-  assert(isPowerOf2_32(HalfLen)); // Sanity.
+  assert(isPowerOf2_32(HalfLen));
 
   // Handle special case where the output is the same half of the input
   // repeated twice, i.e. if Va = AB, then handle the output of AA or BB.
   std::pair<int, unsigned> Strip1 = findStrip(SM.Mask, 1, HalfLen);
   if ((Strip1.first & ~HalfLen) == 0 && Strip1.second == HalfLen) {
     std::pair<int, unsigned> Strip2 =
         findStrip(SM.Mask.drop_front(HalfLen), 1, HalfLen);
     if (Strip1 == Strip2) {

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV,
   unsigned ValWidth = ValTy.getSizeInBits();
   unsigned ElemWidth = VecTy.getVectorElementType().getSizeInBits();
   assert((VecWidth % ElemWidth) == 0);
   auto *IdxN = dyn_cast<ConstantSDNode>(IdxV);
 
   // Special case for v{8,4,2}i1 (the only boolean vectors legal in Hexagon
   // without any coprocessors).
   if (ElemWidth == 1) {
-    assert(VecWidth == VecTy.getVectorNumElements() && "Sanity failure");
+    assert(VecWidth == VecTy.getVectorNumElements() &&
+           "Vector elements should equal vector width size");
     assert(VecWidth == 8 || VecWidth == 4 || VecWidth == 2);
     // Check if this is an extract of the lowest bit.
     if (IdxN) {
       // Extracting the lowest bit is a no-op, but it changes the type,
       // so it must be kept as an operation to avoid errors related to
       // type mismatches.
       if (IdxN->isZero() && ValTy.getSizeInBits() == 1)
         return DAG.getNode(HexagonISD::TYPECAST, dl, MVT::i1, VecV);
while (Scale > 2) {
         SDValue T = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32,
                                 {W0, W1, WidthV, WidthV});
         Words[IdxW ^ 1].push_back(T);
       }
       IdxW ^= 1;
       Scale /= 2;
     }
 
-    // Another sanity check. At this point there should only be two words
-    // left, and Scale should be 2.
+    // At this point there should only be two words left, and Scale should be 2.
     assert(Scale == 2 && Words[IdxW].size() == 2);
 
     SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
                              Words[IdxW][1], Words[IdxW][0]);
     return DAG.getNode(HexagonISD::D2P, dl, VecTy, WW);
   }
 
   return SDValue();

llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp

if (MinNeeded <= MaxGiven) {
     // Calculate the address adjustment amount based on the address with the
     // maximum alignment. This is to allow a simple gep instruction instead
     // of potential bitcasts to i8*.
     int Adjust = -alignTo(OffAtMax - Start, MinNeeded.value());
     AlignAddr = createAdjustedPointer(Builder, WithMaxAlign.Addr,
                                       WithMaxAlign.ValTy, Adjust);
     int Diff = Start - (OffAtMax + Adjust);
     AlignVal = HVC.getConstInt(Diff);
-    // Sanity.
     assert(Diff >= 0);
     assert(static_cast<decltype(MinNeeded.value())>(Diff) < MinNeeded.value());
   } else {
     // WithMinOffset is the lowest address in the group,
     //   WithMinOffset.Addr = Base+Start.
     // Align instructions for both HVX (V6_valign) and scalar (S2_valignrb)
     // mask off unnecessary bits, so it's ok to just the original pointer as
     // the alignment amount.

llvm/test/CodeGen/Hexagon/abi-padding-2.ll

 ; RUN: llc -march=hexagon -mcpu=hexagonv65 < %s | FileCheck %s
 ; REQUIRES: hexagon
 
 ; C file was:
 ; struct S { char b; long long a; };
 ; void foo(int x, struct S arg1);
 ; void bar() {
 ;   struct S s;
 ;   s.b = 'a';
 ;   foo(42, s);
 ;}
 
 ;
 ; Test that while passing a 7-byte struct on the stack, the
 ; size of the struct is 16 bytes including padding since its
 ; largest member is of type long long. This was being handled
-; correctly but is a sanity check against any potential future
+; correctly but is a check against any potential future
 ; regressions.
 ;
 
 ; CHECK: memd(r{{[0-9]+}}+#8) =
 ; CHECK: memd(r{{[0-9]+}}+#0) =
 
 %struct.S = type { i8, i64 }
 

llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir

 # RUN: llc < %s -x mir -march=hexagon -run-pass=modulo-schedule-test -pipeliner-experimental-cg=true | FileCheck %s
 
-# Simple check for this sanity test; ensure all instructions are in stage 0 in
+# Simple check for this validation test; ensure all instructions are in stage 0 in
 # the prolog and stage 3 in the epilog.
 
 # CHECK-NOT: Stage-3
 # CHECK: J2_loop0r
 # CHECK:    intregs = S2_addasl_rrri %{{[0-9]+}}, %{{[0-9]+}}, 1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
 # CHECK:    intregs = L2_loadruh_io %{{[0-9]+}}, -4, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :: (load (s16) from %ir.cgep2, !tbaa !0)
 # CHECK:    intregs = S2_storerh_pi %{{[0-9]+}}, -2, %{{[0-9]+}}, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :: (store (s16) into %ir.lsr.iv, !tbaa !0)
 # CHECK:    intregs = nsw A2_addi %{{[0-9]+}}, -1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>