[clang][ARM] relax -mtp=cp15 for non-thumb cases

[nickdesaulniers]

Summary

Building -march=armv6k Linux kernels with -mtp=cp15 fails to
compile:

error: hardware TLS register is not supported for the arm
sub-architecture

@ardb found docs for ARM1176JZF-S (ARMv6K) that reference hard thread
pointer.

Relax our ARMv6 check for cases where we're targeting ARM via -marm (vs
Thumb1 via -mthumb). This more closely matches the KConfig requirements
for where we plan to use these (ie. ARMv6K, ARMv7 (arm or thumb2)).

As @peter.smith mentions:

on armv5 we can write the instruction to read/write to CP15 C13 with
the ThreadID opcode. However on no armv5 implementation will the CP15
C13 have a Thread ID register. The GCC intent seems to be whether the
instruction is encodable rather than check what the CPU supports.

Fixes: https://github.com/ClangBuiltLinux/linux/issues/1502
Link: https://developer.arm.com/documentation/ddi0301/h/system-control-coprocessor/system-control-processor-registers/c13--thread-and-process-id-registers

[peter.smith]

Apologies had to go on a bit of a dive through the documentation. I've put some comments inline and some links to other documents that may help.

clang/lib/Driver/ToolChains/Arch/ARM.cpp

150

Will be worth saying CP15 C13 ThreadID somewhere to make it easier to look up in the documentation.

155

Are we restricting based on whether the threadid register is present or whether the instructions are available to access the cp15 registers?

If we're going by whether the CPU has the register present then it will be

• A and R profile (not M profile, even the ones that have Thumb2)
• V6K (includes ARM1176 but not ARM1156t2-s which has Thumb-2!) and V7+ (A and R profile)

If we're going by the instructions to write to CP15 then it is:

• Arm state (everything)
• Thumb2 (v7 + v6t2)

The above seems to be a blend of the two. Is it worth choosing one form or the other? GCC seems to use the latter. I guess using this option falls into the I know what I'm doing area that accessing named system registers comes into. If the kernel supports it the stricter version may help catch more mistakes though.

The v7 A/R Arm ARM https://developer.arm.com/documentation/ddi0403/ed
has in D12.7.21 CP15 c13, Context ID support

 An ARMv6K implementation requires the Software Thread ID registers described in VMSA CP15 c13
register summary, Process, context and thread ID registers on page B3-1474.

The Arm 1156-s (the only v6t2 processor) TRM https://developer.arm.com/documentation/ddi0338/g/system-control-coprocessor/system-control-processor-registers/c13--process-id-register?lang=en which shows only one process ID register under opcode 1 accessed via:

MRC p15, 0, <Rd>, c13, c0, 1 ;Read Process ID Register

Whereas the ThreadID register is opcode 3 on CPUs that are v6k and v7.

[ardb]

clang/lib/Driver/ToolChains/Arch/ARM.cpp

155

The primary reason for tightening these checks was to avoid an assert in the backend when using -mtp=cp15 with a Thumb1 target, so I'd say this is more about whether the ISA has the opcode to begin with, rather than whether CPU x implements it or not.

[nickdesaulniers]

clang/lib/Driver/ToolChains/Arch/ARM.cpp

155

Arm state (everything)

Does that mean that -march=armv5 -marm has access/support for "CP15 C13 ThreadID" access?

[peter.smith]

clang/lib/Driver/ToolChains/Arch/ARM.cpp

155

The co-processor instructions are the same, but the effect of the instructions will depend on the CPU. For example on armv5 we can write the instruction to read/write to CP15 C13 with the ThreadID opcode. However on no armv5 implementation will the CP15 C13 have a Thread ID register.

The more complex stricter check will make sure that the implementations have the ThreadID register. As Ard mentions, the GCC intent seems to be whether the instruction is encodable rather than check what the CPU supports.

[nickdesaulniers]

• relax this further for -marm (for armv5 for example)

[nickdesaulniers]

clang/lib/Driver/ToolChains/Arch/ARM.cpp

155

I think this thread is resolved, so marking as done. Please reopen it though if I misunderstood.

[peter.smith]

I've made a suggestion to disallow v8-m.baseline (does not have Thumb 2 but has number > 7) and to simplify the expression.

clang/lib/Driver/ToolChains/Arch/ARM.cpp

155

I think the discussion about whether the MRC/MCR instructions are available is closed. I think the expression isn't quite right as > 7 will permit v8-m.baseline, which is the evolution of cortex-m0.

To match GCC I think you want the equivalent of ARM || hasThumb2Instructions()

I think you can do that with the equivalent of ArmTargetInfo::supportsThumb2() from lib/Basic/Targets/ARM.cpp

bool ARMTargetInfo::supportsThumb2() const {
  return CPUAttr.equals("6T2") ||
         (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE"));
}

Where CPUAttr.equals("8M_BASE") is equivalent to llvm::ARM::ArchKind::ARMV8MBaseline so I think you can use

return Triple.isARM() || (Ver >= 7 && AK != llvm::ARM::ArchKind::ARMV8MBaseline);

ARMV6K and ARMV6KZ can only MRC and MCR in ARM mode so are covered by Triple.isARM().

[peter.smith]

Apologies, missed a couple of small things out. Otherwise looks good to me.

clang/lib/Driver/ToolChains/Arch/ARM.cpp

150

Now we're permitting anything with the co-processor instructions I think the comment would be better expressed as:

We follow GCC and support when the backend has support for the MRC/MCR instructions that are used to set the hard thread pointer ("CP15 C13 //Thread id").

155

My apologies I missed out V6T2 in my comment above. I've added it back in below.

return Triple.isARM() || AK ==  llvm::ARM::ArchKind::ARMV6T2 || (Ver >= 7 && AK != llvm::ARM::ArchKind::ARMV8MBaseline);

[nickdesaulniers]

• use @peter.smith's suggestion re: ARMV8MBaseline

[nickdesaulniers]

• update for thumbv6t2, add test for that.

[peter.smith]

LGTM, thanks for the update.

clang/lib/Driver/ToolChains/Arch/ARM.h

 };
 
 FloatABI getDefaultFloatABI(const llvm::Triple &Triple);
 FloatABI getARMFloatABI(const ToolChain &TC, const llvm::opt::ArgList &Args);
 FloatABI getARMFloatABI(const Driver &D, const llvm::Triple &Triple,
                         const llvm::opt::ArgList &Args);
 void setFloatABIInTriple(const Driver &D, const llvm::opt::ArgList &Args,
                          llvm::Triple &triple);
+bool isHardTPSupported(const llvm::Triple &Triple);
 ReadTPMode getReadTPMode(const Driver &D, const llvm::opt::ArgList &Args,
                          const llvm::Triple &Triple);
 void setArchNameInTriple(const Driver &D, const llvm::opt::ArgList &Args,
                          types::ID InputType, llvm::Triple &Triple);
 
 bool useAAPCSForMachO(const llvm::Triple &T);
 void getARMArchCPUFromArgs(const llvm::opt::ArgList &Args,
                            llvm::StringRef &Arch, llvm::StringRef &CPU,

clang/lib/Driver/ToolChains/Arch/ARM.cpp

 bool arm::useAAPCSForMachO(const llvm::Triple &T) {
   // The backend is hardwired to assume AAPCS for M-class processors, ensure
   // the frontend matches that.
   return T.getEnvironment() == llvm::Triple::EABI ||
          T.getEnvironment() == llvm::Triple::EABIHF ||
          T.getOS() == llvm::Triple::UnknownOS || isARMMProfile(T);
 }
 
+// We follow GCC and support when the backend has support for the MRC/MCR
+// instructions that are used to set the hard thread pointer ("CP15 C13
+// Thread id").
+bool arm::isHardTPSupported(const llvm::Triple &Triple) {
+  int Ver = getARMSubArchVersionNumber(Triple);
+  llvm::ARM::ArchKind AK = llvm::ARM::parseArch(Triple.getArchName());
+  return Triple.isARM() || AK == llvm::ARM::ArchKind::ARMV6T2 ||
+         (Ver >= 7 && AK != llvm::ARM::ArchKind::ARMV8MBaseline);
+}
+
 // Select mode for reading thread pointer (-mtp=soft/cp15).
 arm::ReadTPMode arm::getReadTPMode(const Driver &D, const ArgList &Args,
                                    const llvm::Triple &Triple) {
   if (Arg *A = Args.getLastArg(options::OPT_mtp_mode_EQ)) {
     arm::ReadTPMode ThreadPointer =
         llvm::StringSwitch<arm::ReadTPMode>(A->getValue())
             .Case("cp15", ReadTPMode::Cp15)
             .Case("soft", ReadTPMode::Soft)
             .Default(ReadTPMode::Invalid);
-    if (ThreadPointer == ReadTPMode::Cp15 &&
-        getARMSubArchVersionNumber(Triple) < 7 &&
-        llvm::ARM::parseArch(Triple.getArchName()) !=
-            llvm::ARM::ArchKind::ARMV6T2) {
+    if (ThreadPointer == ReadTPMode::Cp15 && !isHardTPSupported(Triple)) {
       D.Diag(diag::err_target_unsupported_tp_hard) << Triple.getArchName();
       return ReadTPMode::Invalid;
     }
     if (ThreadPointer != ReadTPMode::Invalid)
       return ThreadPointer;
     if (StringRef(A->getValue()).empty())
       D.Diag(diag::err_drv_missing_arg_mtp) << A->getAsString(Args);
     else

 }
 
 void arm::getARMTargetFeatures(const Driver &D, const llvm::Triple &Triple,
                                const ArgList &Args, ArgStringList &CmdArgs,
                                std::vector<StringRef> &Features, bool ForAS) {
   bool KernelOrKext =
       Args.hasArg(options::OPT_mkernel, options::OPT_fapple_kext);
   arm::FloatABI ABI = arm::getARMFloatABI(D, Triple, Args);
-  arm::ReadTPMode ThreadPointer = arm::getReadTPMode(D, Args, Triple);
   llvm::Optional<std::pair<const Arg *, StringRef>> WaCPU, WaFPU, WaHDiv,
       WaArch;
 
   // This vector will accumulate features from the architecture
   // extension suffixes on -mcpu and -march (e.g. the 'bar' in
   // -mcpu=foo+bar). We want to apply those after the features derived
   // from the FPU, in case -mfpu generates a negative feature which
   // the +bar is supposed to override.
for (const Arg *A :
           WaHDiv = std::make_pair(A, Value.substr(8));
         } else if (Value.startswith("-march=")) {
           WaArch = std::make_pair(A, Value.substr(7));
         }
       }
     }
   }
 
-  if (ThreadPointer == arm::ReadTPMode::Cp15)
+  if (getReadTPMode(D, Args, Triple) == ReadTPMode::Cp15)
     Features.push_back("+read-tp-hard");
 
   const Arg *ArchArg = Args.getLastArg(options::OPT_march_EQ);
   const Arg *CPUArg = Args.getLastArg(options::OPT_mcpu_EQ);
   StringRef ArchName;
   StringRef CPUName;
   unsigned ArchArgFPUID = llvm::ARM::FK_INVALID;
   unsigned CPUArgFPUID = llvm::ARM::FK_INVALID;

clang/test/Driver/clang-translation.c

 // ARMV5E: "-cc1"
 // ARMV5E: "-target-cpu" "arm1022e"
 
 // RUN: %clang -target armv7-linux -mtp=cp15 -### -S %s 2>&1 | \
 // RUN: FileCheck -check-prefix=ARMv7_THREAD_POINTER-HARD %s
 // ARMv7_THREAD_POINTER-HARD: "-target-feature" "+read-tp-hard"
 
 // RUN: %clang -target armv6t2-linux -mtp=cp15 -### -S %s 2>&1 | \
-// RUN: FileCheck -check-prefix=ARMv6T2_THREAD_POINTER-HARD %s
-// ARMv6T2_THREAD_POINTER-HARD: "-target-feature" "+read-tp-hard"
-
+// RUN: FileCheck -check-prefix=ARM_THREAD_POINTER-HARD %s
+// RUN: %clang -target thumbv6t2-linux -mtp=cp15 -### -S %s 2>&1 | \
+// RUN: FileCheck -check-prefix=ARM_THREAD_POINTER-HARD %s
+// RUN: %clang -target armv6k-linux -mtp=cp15 -### -S %s 2>&1 | \
+// RUN: FileCheck -check-prefix=ARM_THREAD_POINTER-HARD %s
+// RUN: %clang -target armv6-linux -mtp=cp15 -### -S %s 2>&1 | \
+// RUN: FileCheck -check-prefix=ARM_THREAD_POINTER-HARD %s
 // RUN: %clang -target armv5t-linux -mtp=cp15 -### -S %s 2>&1 | \
-// RUN: FileCheck -check-prefix=ARMv5_THREAD_POINTER_UNSUPP %s
-// ARMv5_THREAD_POINTER_UNSUPP: hardware TLS register is not supported for the armv5 sub-architecture
+// RUN: FileCheck -check-prefix=ARM_THREAD_POINTER-HARD %s
+// ARM_THREAD_POINTER-HARD: "-target-feature" "+read-tp-hard"
 
-// RUN: %clang -target thumbv6-linux -mtp=cp15 -### -S %s 2>&1 | \
-// RUN: FileCheck -check-prefix=ARMv6_THREAD_POINTER_UNSUPP %s
-// ARMv6_THREAD_POINTER_UNSUPP: hardware TLS register is not supported for the armv6 sub-architecture
+// RUN: %clang -target armv6-linux -mthumb -mtp=cp15 -### -S %s 2>&1 | \
+// RUN: FileCheck -check-prefix=THUMBv6_THREAD_POINTER_UNSUPP %s
+// RUN: %clang -target thumbv6-linux -mthumb -mtp=cp15 -### -S %s 2>&1 | \
+// RUN: FileCheck -check-prefix=THUMBv6_THREAD_POINTER_UNSUPP %s
+// THUMBv6_THREAD_POINTER_UNSUPP: hardware TLS register is not supported for the thumbv6 sub-architecture
 
 // RUN: %clang -target armv7-linux -mtp=soft -### -S %s 2>&1 | \
 // RUN: FileCheck -check-prefix=ARMv7_THREAD_POINTER_SOFT %s
 // ARMv7_THREAD_POINTER_SOFT-NOT: "-target-feature" "+read-tp-hard"
 
 // RUN: %clang -target armv7-linux -### -S %s 2>&1 | \
 // RUN: FileCheck -check-prefix=ARMv7_THREAD_POINTER_NON %s
 // ARMv7_THREAD_POINTER_NON-NOT: "-target-feature" "+read-tp-hard"