[TypePromotion] Extend TypePromotion::isSafeWrap

[dmgreen]

Summary

This modifies the preconditions of TypePromotion's isSafeWrap method, to allow it to work from all constants from the ICmp. Using the code:

%a = add %x, C1
%c = icmp ult %a, C2

According to Alive, we can prove that is equivalent to icmp ult (add zext(%x), sext(C1)), zext(C2) given C1 <=s 0 and C1 >s C2.
https://alive2.llvm.org/ce/z/CECYZB
And can prove icmp ult (add zext(%x), sext(C1)), sext(C2) given C1 <=s 0 and C1 <=s C2.
https://alive2.llvm.org/ce/z/KKgyeL

The PrepareWrappingAdds method was removed, and the constants are now altered to sext or zext directly as required by the above methods.

[samparker]

Good bit of brain exercise for the morning... Nice addition and cleanup too, thanks. Just a couple of function renaming requests from me.

llvm/test/CodeGen/AArch64/typepromotion-overflow.ll

175–176

Good to change the function name before committing, same for the other altered test.

llvm/test/Transforms/TypePromotion/ARM/wrapping.ll

103

And in this file too :)

[dmgreen]

Cheers.

llvm/lib/CodeGen/TypePromotion.cpp

 namespace {
 class IRPromoter {
   LLVMContext &Ctx;
   IntegerType *OrigTy = nullptr;
   unsigned PromotedWidth = 0;
   SetVector<Value*> &Visited;
   SetVector<Value*> &Sources;
   SetVector<Instruction*> &Sinks;
-  SmallVectorImpl<Instruction*> &SafeWrap;
+  SmallPtrSetImpl<Instruction *> &SafeWrap;
   IntegerType *ExtTy = nullptr;
   SmallPtrSet<Value*, 8> NewInsts;
   SmallPtrSet<Instruction*, 4> InstsToRemove;
   DenseMap<Value*, SmallVector<Type*, 4>> TruncTysMap;
   SmallPtrSet<Value*, 8> Promoted;
 
   void ReplaceAllUsersOfWith(Value *From, Value *To);
-  void PrepareWrappingAdds(void);
   void ExtendSources(void);
   void ConvertTruncs(void);
   void PromoteTree(void);
   void TruncateSinks(void);
   void Cleanup(void);
 
 public:
   IRPromoter(LLVMContext &C, IntegerType *Ty, unsigned Width,
-             SetVector<Value*> &visited, SetVector<Value*> &sources,
-             SetVector<Instruction*> &sinks,
-             SmallVectorImpl<Instruction*> &wrap) :
-    Ctx(C), OrigTy(Ty), PromotedWidth(Width), Visited(visited),
+             SetVector<Value *> &visited, SetVector<Value *> &sources,
+             SetVector<Instruction *> &sinks,
+             SmallPtrSetImpl<Instruction *> &wrap)
+      : Ctx(C), OrigTy(Ty), PromotedWidth(Width), Visited(visited),
         Sources(sources), Sinks(sinks), SafeWrap(wrap) {
     ExtTy = IntegerType::get(Ctx, PromotedWidth);
     assert(OrigTy->getPrimitiveSizeInBits().getFixedSize() <
                ExtTy->getPrimitiveSizeInBits().getFixedSize() &&
            "Original type not smaller than extended type");
   }
 
   void Mutate();
 };
 
 class TypePromotion : public FunctionPass {
   unsigned TypeSize = 0;
   LLVMContext *Ctx = nullptr;
   unsigned RegisterBitWidth = 0;
   SmallPtrSet<Value*, 16> AllVisited;
   SmallPtrSet<Instruction*, 8> SafeToPromote;
-  SmallVector<Instruction*, 4> SafeWrap;
+  SmallPtrSet<Instruction *, 4> SafeWrap;
 
   // Does V have the same size result type as TypeSize.
   bool EqualTypeSize(Value *V);
   // Does V have the same size, or narrower, result type as TypeSize.
   bool LessOrEqualTypeSize(Value *V);
   // Does V have a result type that is wider than TypeSize.
   bool GreaterThanTypeSize(Value *V);
   // Does V have a result type that is narrower than TypeSize.
bool TypePromotion::isSafeWrap(Instruction *I) {
   // %add = 256
   //
   // (1 < 127) != (256 < 127)
 
   unsigned Opc = I->getOpcode();
   if (Opc != Instruction::Add && Opc != Instruction::Sub)
     return false;
 
-  if (!I->hasOneUse() ||
-      !isa<ICmpInst>(*I->user_begin()) ||
+  if (!I->hasOneUse() || !isa<ICmpInst>(*I->user_begin()) ||
       !isa<ConstantInt>(I->getOperand(1)))
     return false;
 
-  ConstantInt *OverflowConst = cast<ConstantInt>(I->getOperand(1));
-  bool NegImm = OverflowConst->isNegative();
-  bool IsDecreasing = ((Opc == Instruction::Sub) && !NegImm) ||
-                       ((Opc == Instruction::Add) && NegImm);
-  if (!IsDecreasing)
-    return false;
-
   // Don't support an icmp that deals with sign bits.
   auto *CI = cast<ICmpInst>(*I->user_begin());
   if (CI->isSigned() || CI->isEquality())
     return false;
 
-  ConstantInt *ICmpConst = nullptr;
+  ConstantInt *ICmpConstant = nullptr;
   if (auto *Const = dyn_cast<ConstantInt>(CI->getOperand(0)))
-    ICmpConst = Const;
+    ICmpConstant = Const;
   else if (auto *Const = dyn_cast<ConstantInt>(CI->getOperand(1)))
-    ICmpConst = Const;
+    ICmpConstant = Const;
   else
     return false;
 
-  // Now check that the result can't wrap on itself.
-  APInt Total = ICmpConst->getValue().zextOrSelf(RegisterBitWidth);
-  Total += OverflowConst->getValue().abs().zextOrSelf(RegisterBitWidth);
-
-  APInt Max = APInt::getAllOnes(TypeSize).zextOrSelf(RegisterBitWidth);
-
-  if (Total.ugt(Max))
+  const APInt &ICmpConst = ICmpConstant->getValue();
+  APInt OverflowConst = cast<ConstantInt>(I->getOperand(1))->getValue();
+  if (Opc == Instruction::Sub)
+    OverflowConst = -OverflowConst;
+  if (!OverflowConst.isNonPositive())
     return false;
 
-  LLVM_DEBUG(dbgs() << "IR Promotion: Allowing safe overflow for " << *I
-                    << "\n");
-  SafeWrap.push_back(I);
+  // Using C1 = OverflowConst and C2 = ICmpConst, we can use either prove that:
+  //   zext(x) + sext(C1) <u zext(C2)  if C1 < 0 and C1 >s C2
+  //   zext(x) + sext(C1) <u sext(C2)  if C1 < 0 and C1 <=s C2
+  if (OverflowConst.sgt(ICmpConst)) {
+    LLVM_DEBUG(dbgs() << "IR Promotion: Allowing safe overflow for sext "
+                      << "const of " << *I << "\n");
+    SafeWrap.insert(I);
     return true;
+  } else {
+    LLVM_DEBUG(dbgs() << "IR Promotion: Allowing safe overflow for sext "
+                      << "const of " << *I << " and " << *CI << "\n");
+    SafeWrap.insert(I);
+    SafeWrap.insert(CI);
+    return true;
+  }
+  return false;
 }
 
 bool TypePromotion::shouldPromote(Value *V) {
   if (!isa<IntegerType>(V->getType()) || isSink(V))
     return false;
 
   if (isSource(V))
     return true;

 }
 
 void IRPromoter::ReplaceAllUsersOfWith(Value *From, Value *To) {
   SmallVector<Instruction*, 4> Users;
   Instruction *InstTo = dyn_cast<Instruction>(To);
   bool ReplacedAll = true;
 
   LLVM_DEBUG(dbgs() << "IR Promotion: Replacing " << *From << " with " << *To
                     << "\n");
 
   for (Use &U : From->uses()) {
     auto *User = cast<Instruction>(U.getUser());
     if (InstTo && User->isIdenticalTo(InstTo)) {
       ReplacedAll = false;
       continue;
     }
     Users.push_back(User);
   }
 
   for (auto *U : Users)
     U->replaceUsesOfWith(From, To);
 
   if (ReplacedAll)
     if (auto *I = dyn_cast<Instruction>(From))
       InstsToRemove.insert(I);
 }
 
-void IRPromoter::PrepareWrappingAdds() {
-  LLVM_DEBUG(dbgs() << "IR Promotion: Prepare wrapping adds.\n");
-  IRBuilder<> Builder{Ctx};
-
-  // For adds that safely wrap and use a negative immediate as operand 1, we
-  // create an equivalent instruction using a positive immediate.
-  // That positive immediate can then be zext along with all the other
-  // immediates later.
-  for (auto *I : SafeWrap) {
-    if (I->getOpcode() != Instruction::Add)
-      continue;
-
-    LLVM_DEBUG(dbgs() << "IR Promotion: Adjusting " << *I << "\n");
-    assert((isa<ConstantInt>(I->getOperand(1)) &&
-            cast<ConstantInt>(I->getOperand(1))->isNegative()) &&
-           "Wrapping should have a negative immediate as the second operand");
-
-    auto Const = cast<ConstantInt>(I->getOperand(1));
-    auto *NewConst = ConstantInt::get(Ctx, Const->getValue().abs());
-    Builder.SetInsertPoint(I);
-    Value *NewVal = Builder.CreateSub(I->getOperand(0), NewConst);
-    if (auto *NewInst = dyn_cast<Instruction>(NewVal)) {
-      NewInst->copyIRFlags(I);
-      NewInsts.insert(NewInst);
-    }
-    InstsToRemove.insert(I);
-    I->replaceAllUsesWith(NewVal);
-    LLVM_DEBUG(dbgs() << "IR Promotion: New equivalent: " << *NewVal << "\n");
-  }
-  for (auto *I : NewInsts)
-    Visited.insert(I);
-}
-
 void IRPromoter::ExtendSources() {
   IRBuilder<> Builder{Ctx};
 
   auto InsertZExt = [&](Value *V, Instruction *InsertPt) {
     assert(V->getType() != ExtTy && "zext already extends to i32");
     LLVM_DEBUG(dbgs() << "IR Promotion: Inserting ZExt for " << *V << "\n");
     Builder.SetInsertPoint(InsertPt);
     if (auto *I = dyn_cast<Instruction>(V))
if (Sinks.count(I))
       continue;
 
     for (unsigned i = 0, e = I->getNumOperands(); i < e; ++i) {
       Value *Op = I->getOperand(i);
       if ((Op->getType() == ExtTy) || !isa<IntegerType>(Op->getType()))
         continue;
 
       if (auto *Const = dyn_cast<ConstantInt>(Op)) {
-        Constant *NewConst = ConstantExpr::getZExt(Const, ExtTy);
+        Constant *NewConst = SafeWrap.contains(I)
+                                 ? ConstantExpr::getSExt(Const, ExtTy)
+                                 : ConstantExpr::getZExt(Const, ExtTy);
         I->setOperand(i, NewConst);
       } else if (isa<UndefValue>(Op))
         I->setOperand(i, UndefValue::get(ExtTy));
     }
 
     // Mutate the result type, unless this is an icmp or switch.
     if (!isa<ICmpInst>(I) && !isa<SwitchInst>(I)) {
       I->mutateType(ExtTy);
void IRPromoter::Mutate() {
   }
   for (auto *V : Visited) {
     if (!isa<TruncInst>(V) || Sources.count(V))
       continue;
     auto *Trunc = cast<TruncInst>(V);
     TruncTysMap[Trunc].push_back(Trunc->getDestTy());
   }
 
-  // Convert adds using negative immediates to equivalent instructions that use
-  // positive constants.
-  PrepareWrappingAdds();
-
   // Insert zext instructions between sources and their users.
   ExtendSources();
 
   // Promote visited instructions, mutating their types in place.
   PromoteTree();
 
   // Convert any truncs, that aren't sources, into AND masks.
   ConvertTruncs();
bool TypePromotion::TryToPromote(Value *V, unsigned PromotedWidth) {
   TypeSize = OrigTy->getPrimitiveSizeInBits().getFixedSize();
   SafeToPromote.clear();
   SafeWrap.clear();
 
   if (!isSupportedValue(V) || !shouldPromote(V) || !isLegalToPromote(V))
     return false;
 
   LLVM_DEBUG(dbgs() << "IR Promotion: TryToPromote: " << *V << ", from "
                     << TypeSize << " bits to " << PromotedWidth << "\n");
 
   SetVector<Value*> WorkList;
   SetVector<Value*> Sources;
   SetVector<Instruction*> Sinks;
   SetVector<Value*> CurrentVisited;
   WorkList.insert(V);
 
   // Return true if V was added to the worklist as a supported instruction,

llvm/test/CodeGen/AArch64/and-mask-removal.ll

 ret_true:
   ret i1 true
 }
 
 define zeroext i1 @test8_5(i8 zeroext %x)  align 2 {
 ; CHECK-LABEL: test8_5:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    sub w8, w0, #123
-; CHECK-NEXT:    and w8, w8, #0xff
-; CHECK-NEXT:    cmp w8, #150
+; CHECK-NEXT:    cmn w8, #106
 ; CHECK-NEXT:    cset w0, hi
 ; CHECK-NEXT:    ret
 entry:
   %0 = add i8 %x, 133
   %1 = icmp uge i8 %0, -105
   br i1 %1, label %ret_true, label %ret_false
 ret_false:
   ret i1 false

llvm/test/CodeGen/AArch64/typepromotion-overflow.ll

 ; CHECK-NEXT:    cmp w8, w0, sxtb
 ; CHECK-NEXT:    mov w8, #16
 ; CHECK-NEXT:    csel w0, w9, w8, gt
 ; CHECK-NEXT:    ret
   %cmp = icmp slt i8 %a, -1
   %res = select i1 %cmp, i32 8, i32 16
   ret i32 %res
 }
 
-define i32 @unsafe_sub_underflow(i8 zeroext %a) {
-; CHECK-LABEL: unsafe_sub_underflow:
+; This is valid so long as the icmp immediate is sext.
+define i32 @sext_sub_underflow(i8 zeroext %a) {
+; CHECK-LABEL: sext_sub_underflow:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub w9, w0, #6
 ; CHECK-NEXT:    mov w8, #16
-; CHECK-NEXT:    and w9, w9, #0xff
-; CHECK-NEXT:    cmp w9, #250
+; CHECK-NEXT:    cmn w9, #6
 ; CHECK-NEXT:    mov w9, #8
 ; CHECK-NEXT:    csel w0, w9, w8, hi
 ; CHECK-NEXT:    ret
   %sub = add i8 %a, -6
   %cmp = icmp ugt i8 %sub, -6
   %res = select i1 %cmp, i32 8, i32 16
   ret i32 %res
 }

 ; CHECK-NEXT:    csel w0, w9, w8, hi
 ; CHECK-NEXT:    ret
   %sub = add i8 %a, -4
   %cmp = icmp ugt i8 %sub, -6
   %res = select i1 %cmp, i32 8, i32 16
   ret i32 %res
 }
 
-define i32 @unsafe_sub_underflow_neg(i8 zeroext %a) {
-; CHECK-LABEL: unsafe_sub_underflow_neg:
+; This is valid so long as the icmp immediate is sext.
+define i32 @sext_sub_underflow_neg(i8 zeroext %a) {
+; CHECK-LABEL: sext_sub_underflow_neg:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub w9, w0, #4
 ; CHECK-NEXT:    mov w8, #16
-; CHECK-NEXT:    and w9, w9, #0xff
-; CHECK-NEXT:    cmp w9, #253
+; CHECK-NEXT:    cmn w9, #3
 ; CHECK-NEXT:    mov w9, #8
 ; CHECK-NEXT:    csel w0, w9, w8, lo
 ; CHECK-NEXT:    ret
   %sub = add i8 %a, -4
   %cmp = icmp ult i8 %sub, -3
   %res = select i1 %cmp, i32 8, i32 16
   ret i32 %res
 }

llvm/test/Transforms/TypePromotion/ARM/casts.ll

 ; CHECK-LABEL: @or_icmp_ugt(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i8, i8* [[PTR:%.*]], align 1
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
 ; CHECK-NEXT:    [[TMP2:%.*]] = zext i8 [[TMP0]] to i32
 ; CHECK-NEXT:    [[MUL:%.*]] = shl nuw nsw i32 [[TMP2]], 1
 ; CHECK-NEXT:    [[ADD0:%.*]] = add nuw nsw i32 [[MUL]], 6
 ; CHECK-NEXT:    [[CMP0:%.*]] = icmp ne i32 [[ARG:%.*]], [[ADD0]]
-; CHECK-NEXT:    [[TMP3:%.*]] = sub i32 [[TMP1]], 1
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp ugt i32 [[TMP3]], 3
+; CHECK-NEXT:    [[ADD1:%.*]] = add i32 [[TMP1]], -1
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ugt i32 [[ADD1]], 3
 ; CHECK-NEXT:    [[OR:%.*]] = or i1 [[CMP0]], [[CMP1]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
 entry:
   %0 = load i8, i8* %ptr
   %1 = zext i8 %0 to i32
   %mul = shl nuw nsw i32 %1, 1
   %add0 = add nuw nsw i32 %mul, 6

llvm/test/Transforms/TypePromotion/ARM/clear-structures.ll

 ; CHECK-NEXT:    br label [[WHILE_COND10]]
 ; CHECK:       while.end18.split:
 ; CHECK-NEXT:    [[CMP20:%.*]] = icmp eq i8 [[TMP1]], 46
 ; CHECK-NEXT:    br i1 [[CMP20]], label [[IF_THEN22:%.*]], label [[COND_END:%.*]]
 ; CHECK:       if.then22:
 ; CHECK-NEXT:    [[INCDEC_PTR23:%.*]] = getelementptr inbounds i8, i8* [[FMT_ADDR_0_PN]], i32 2
 ; CHECK-NEXT:    [[DOTPR74:%.*]] = load i8, i8* [[INCDEC_PTR23]], align 1
 ; CHECK-NEXT:    [[TMP3:%.*]] = zext i8 [[DOTPR74]] to i32
-; CHECK-NEXT:    [[TMP4:%.*]] = sub i32 [[TMP3]], 48
-; CHECK-NEXT:    [[TMP5:%.*]] = icmp ult i32 [[TMP4]], 10
-; CHECK-NEXT:    br i1 [[TMP5]], label [[WHILE_COND24:%.*]], label [[COND_END]]
+; CHECK-NEXT:    [[DOTPR74_OFF:%.*]] = add i32 [[TMP3]], -48
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp ult i32 [[DOTPR74_OFF]], 10
+; CHECK-NEXT:    br i1 [[TMP4]], label [[WHILE_COND24:%.*]], label [[COND_END]]
 ; CHECK:       while.cond24:
 ; CHECK-NEXT:    br label [[WHILE_COND24]]
 ; CHECK:       cond.end:
 ; CHECK-NEXT:    [[FMT_ADDR_3]] = phi i8* [ [[FMT_ADDR_1]], [[WHILE_END18_SPLIT]] ], [ [[INCDEC_PTR23]], [[IF_THEN22]] ]
 ; CHECK-NEXT:    [[AND39:%.*]] = and i32 [[FLAGS_0]], 2048
 ; CHECK-NEXT:    [[TOBOOL40:%.*]] = icmp eq i32 [[AND39]], 0
 ; CHECK-NEXT:    br i1 [[TOBOOL40]], label [[WHILE_COND_OUTER_BACKEDGE]], label [[IF_THEN43:%.*]]
 ; CHECK:       while.cond.outer.backedge:

llvm/test/Transforms/TypePromotion/ARM/icmps.ll

entry:
   %res = select i1 %cmp, i32 35, i32 47
   ret i32 %res
 }
 
 define i32 @test_ugt_1_dec_imm(i8 zeroext %x) {
 ; CHECK-LABEL: @test_ugt_1_dec_imm(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 [[TMP0]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP1]], 1
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[TMP0]], -1
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[ADD]], 1
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i32 35, i32 47
 ; CHECK-NEXT:    ret i32 [[RES]]
 ;
 entry:
   %add = add i8 %x, -1
   %cmp = icmp ugt i8 %add, 1
   %res = select i1 %cmp, i32 35, i32 47
   ret i32 %res
;
   store i8 %sub, i8* %out, align 1
   ret void
 }
 
 define i32 @ugt_1_dec_imm(i8 zeroext %x) {
 ; CHECK-LABEL: @ugt_1_dec_imm(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 [[TMP0]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP1]], 1
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[TMP0]], -1
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[ADD]], 1
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i32 35, i32 47
 ; CHECK-NEXT:    ret i32 [[RES]]
 ;
 entry:
   %add = add i8 %x, -1
   %cmp = icmp ugt i8 %add, 1
   %res = select i1 %cmp, i32 35, i32 47
   ret i32 %res
;
   %res = select i1 %cmp, i32 21, i32 42
   ret i32 %res
 }
 
 define i32 @icmp_minus_imm(i8* %a) {
 ; CHECK-LABEL: @icmp_minus_imm(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1
-; CHECK-NEXT:    [[ADD_I:%.*]] = add i8 [[TMP0]], -7
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i8 [[ADD_I]], -5
+; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
+; CHECK-NEXT:    [[ADD_I:%.*]] = add i32 [[TMP1]], -7
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[ADD_I]], -5
 ; CHECK-NEXT:    [[CONV1:%.*]] = zext i1 [[CMP]] to i32
 ; CHECK-NEXT:    ret i32 [[CONV1]]
 ;
 entry:
   %0 = load i8, i8* %a, align 1
   %add.i = add i8 %0, -7
   %cmp = icmp ugt i8 %add.i, -5
   %conv1 = zext i1 %cmp to i32

llvm/test/Transforms/TypePromotion/ARM/wrapping.ll

 ; CHECK-NEXT:    ret i32 [[RES]]
 ;
   %add = add i8 %a, 1
   %cmp = icmp ugt i8 %add, 128
   %res = select i1 %cmp, i32 8, i32 16
   ret i32 %res
 }
 
 define i32 @unsafe_add_underflow(i8 zeroext %a) {
 ; CHECK-LABEL: @unsafe_add_underflow(
-; CHECK-NEXT:    [[ADD:%.*]] = add i8 [[A:%.*]], -2
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i8 [[ADD]], -2
+; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[TMP1]], -2
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[ADD]], -2
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i32 8, i32 16
 ; CHECK-NEXT:    ret i32 [[RES]]
 ;
   %add = add i8 %a, -2
   %cmp = icmp ugt i8 %add, 254
   %res = select i1 %cmp, i32 8, i32 16
   ret i32 %res
 }
 
 define i32 @safe_add_underflow(i8 zeroext %a) {
 ; CHECK-LABEL: @safe_add_underflow(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = sub i32 [[TMP1]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP2]], 254
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[TMP1]], -1
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[ADD]], 254
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i32 8, i32 16
 ; CHECK-NEXT:    ret i32 [[RES]]
 ;
   %add = add i8 %a, -1
   %cmp = icmp ugt i8 %add, 254
   %res = select i1 %cmp, i32 8, i32 16
   ret i32 %res
 }
 
 define i32 @safe_add_underflow_neg(i8 zeroext %a) {
 ; CHECK-LABEL: @safe_add_underflow_neg(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = sub i32 [[TMP1]], 2
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ule i32 [[TMP2]], 250
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[TMP1]], -2
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ule i32 [[ADD]], 250
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i32 8, i32 16
 ; CHECK-NEXT:    ret i32 [[RES]]
 ;
   %add = add i8 %a, -2
   %cmp = icmp ule i8 %add, -6
   %res = select i1 %cmp, i32 8, i32 16
   ret i32 %res
 }
 
 define i32 @overflow_sub_negative_const_limit(i8 zeroext %a) {
 ; CHECK-LABEL: @overflow_sub_negative_const_limit(
 ; CHECK-NEXT:    [[SUB:%.*]] = sub i8 [[A:%.*]], -1
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i8 [[SUB]], -128
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i32 8, i32 16
 ; CHECK-NEXT:    ret i32 [[RES]]
 ;
   %sub = sub i8 %a, -1
   %cmp = icmp ugt i8 %sub, 128
   %res = select i1 %cmp, i32 8, i32 16
   ret i32 %res
 }
 
-define i32 @unsafe_sub_underflow(i8 zeroext %a) {
-; CHECK-LABEL: @unsafe_sub_underflow(
-; CHECK-NEXT:    [[SUB:%.*]] = sub i8 [[A:%.*]], 6
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i8 [[SUB]], -6
+; This is valid so long as the icmp immediate is sext.
+define i32 @sext_sub_underflow(i8 zeroext %a) {
+; CHECK-LABEL: @sext_sub_underflow(
+; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32
+; CHECK-NEXT:    [[SUB:%.*]] = sub i32 [[TMP1]], 6
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[SUB]], -6
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i32 8, i32 16
 ; CHECK-NEXT:    ret i32 [[RES]]
 ;
   %sub = sub i8 %a, 6
   %cmp = icmp ugt i8 %sub, 250
   %res = select i1 %cmp, i32 8, i32 16
   ret i32 %res
 }

 ; CHECK-NEXT:    ret i32 [[RES]]
 ;
   %sub = sub i8 %a, 4
   %cmp = icmp uge i8 %sub, -5
   %res = select i1 %cmp, i32 8, i32 16
   ret i32 %res
 }
 
-define i32 @unsafe_sub_underflow_neg(i8 zeroext %a) {
-; CHECK-LABEL: @unsafe_sub_underflow_neg(
-; CHECK-NEXT:    [[SUB:%.*]] = sub i8 [[A:%.*]], 4
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[SUB]], -3
+; This is valid so long as the icmp immediate is sext.
+define i32 @sext_sub_underflow_neg(i8 zeroext %a) {
+; CHECK-LABEL: @sext_sub_underflow_neg(
+; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32
+; CHECK-NEXT:    [[SUB:%.*]] = sub i32 [[TMP1]], 4
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[SUB]], -3
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i32 8, i32 16
 ; CHECK-NEXT:    ret i32 [[RES]]
 ;
   %sub = sub i8 %a, 4
   %cmp = icmp ult i8 %sub, -3
   %res = select i1 %cmp, i32 8, i32 16
   ret i32 %res
 }

 define i8 @convert_add_order(i8 zeroext %arg) {
 ; CHECK-LABEL: @convert_add_order(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[ARG:%.*]] to i32
 ; CHECK-NEXT:    [[MASK_0:%.*]] = and i32 [[TMP1]], 1
 ; CHECK-NEXT:    [[MASK_1:%.*]] = and i32 [[TMP1]], 2
 ; CHECK-NEXT:    [[SHL:%.*]] = or i32 [[TMP1]], 1
 ; CHECK-NEXT:    [[ADD:%.*]] = add nuw i32 [[SHL]], 10
 ; CHECK-NEXT:    [[CMP_0:%.*]] = icmp ult i32 [[ADD]], 60
-; CHECK-NEXT:    [[TMP2:%.*]] = sub nsw i32 [[SHL]], 40
-; CHECK-NEXT:    [[CMP_1:%.*]] = icmp ult i32 [[TMP2]], 20
+; CHECK-NEXT:    [[SUB:%.*]] = add nsw i32 [[SHL]], -40
+; CHECK-NEXT:    [[CMP_1:%.*]] = icmp ult i32 [[SUB]], 20
 ; CHECK-NEXT:    [[MASK_SEL:%.*]] = select i1 [[CMP_1]], i32 [[MASK_0]], i32 [[MASK_1]]
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP_0]], i32 [[MASK_SEL]], i32 [[TMP1]]
-; CHECK-NEXT:    [[TMP3:%.*]] = trunc i32 [[RES]] to i8
-; CHECK-NEXT:    ret i8 [[TMP3]]
+; CHECK-NEXT:    [[TMP2:%.*]] = trunc i32 [[RES]] to i8
+; CHECK-NEXT:    ret i8 [[TMP2]]
 ;
   %mask.0 = and i8 %arg, 1
   %mask.1 = and i8 %arg, 2
   %shl = or i8 %arg, 1
   %add = add nuw i8 %shl, 10
   %cmp.0 = icmp ult i8 %add, 60
   %sub = add nsw i8 %shl, -40
   %cmp.1 = icmp ult i8 %sub, 20