[InstCombine] Canonicalize range test idiom

[nikic]

Summary

InstCombine converts range tests of the form (X > C1 && X < C2) or (X < C1 || X > C2) into checks of the form (X + C3 < C4) or (X + C3 > C4). It is possible to express all range tests in either of these forms (with different choices of constants), but currently neither of them is considered canonical. We may have equivalent range tests using either ult or ugt.

This proposes to canonicalize all range tests to use ult. An alternative would be to canonicalize to either ult or ugt depending on the specific constants involved -- e.g. in practice we currently generate ult for && style ranges and ugt for || style ranges when going through the insertRangeTest() helper. In fact, the "clamp like" fold was relying on this, which is why I had to tweak it to not assume whether inversion is needed based on just the predicate.

Proof: https://alive2.llvm.org/ce/z/_SP_rQ

[lebedev.ri]

LG

[xbolva00]

llvm/test/Transforms/InstCombine/2006-12-15-Range-Test.ll

58–60

Maybe prefer ugt? To keep positive numbers. (Common cases).

[nikic]

llvm/test/Transforms/InstCombine/2006-12-15-Range-Test.ll

58–60

Using ugt will not prefer positive numbers in general, it depends on the tested range. I did check that variant, and the impact is about the same, just for different test cases.

We would have to canonicalize to ugt/ult based on some heuristic involving the specific constants required, which seems a bit unusual for InstCombine.

[xbolva00]

llvm/test/Transforms/InstCombine/2006-12-15-Range-Test.ll

58–60

Ok.

[spatel]

LGTM
If I'm seeing it correctly, this is currently limited to ignore a canonical umax pattern from somewhere higher in the callers. We must have a test for that pattern somewhere, so it would be nice to put an explanatory comment on that (currently negative) test along with this patch.

[yiranwang]

This change is problematic, as something like
if (x >= '0' && x <= '9')
before this change is "if (x - '0‘ <u 10)", and now it becomes "if (245 <u x - '9')".
The later one is more expensive, as the ZExt followed by ADD(of type i32) is not removable, say, if the ISA does not have native i8-ADD instruction. While the former form is just OK, and the ZExt is removable.
So at least, if the type does not have native addition instruction, we should not do this. Or maybe, just don't do this in general, as no cannonicalization in that sense is possible.
Another issue is that some ISA may not like big constant integer. ISEL may be able to handle that, although.

llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp

Instruction *InstCombinerImpl::foldICmpAddConstant(ICmpInst &Cmp,
 
   // X+C >u C2 -> (X & ~C2) != C
   //   iff C & C2 == 0
   //       C2+1 is a power of 2
   if (Pred == ICmpInst::ICMP_UGT && (C + 1).isPowerOf2() && (*C2 & C) == 0)
     return new ICmpInst(ICmpInst::ICMP_NE, Builder.CreateAnd(X, ~C),
                         ConstantExpr::getNeg(cast<Constant>(Y)));
 
+  // The range test idiom can use either ult or ugt. Arbitrarily canonicalize
+  // to the ult form.
+  // X+C2 >u C -> X+(C2-C-1) <u ~C
+  if (Pred == ICmpInst::ICMP_UGT)
+    return new ICmpInst(ICmpInst::ICMP_ULT,
+                        Builder.CreateAdd(X, ConstantInt::get(Ty, *C2 - C - 1)),
+                        ConstantInt::get(Ty, ~C));
+
   return nullptr;
 }
 
 bool InstCombinerImpl::matchThreeWayIntCompare(SelectInst *SI, Value *&LHS,
                                                Value *&RHS, ConstantInt *&Less,
                                                ConstantInt *&Equal,
                                                ConstantInt *&Greater) {
   // TODO: Generalize this to work with other comparison idioms or ensure

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

static Value *canonicalizeClampLike(SelectInst &Sel0, ICmpInst &Cmp0,
                                     InstCombiner::BuilderTy &Builder) {
   Value *X = Sel0.getTrueValue();
   Value *Sel1 = Sel0.getFalseValue();
 
   // First match the condition of the outermost select.
   // Said condition must be one-use.
   if (!Cmp0.hasOneUse())
     return nullptr;
+  ICmpInst::Predicate Pred0 = Cmp0.getPredicate();
   Value *Cmp00 = Cmp0.getOperand(0);
   Constant *C0;
   if (!match(Cmp0.getOperand(1),
              m_CombineAnd(m_AnyIntegralConstant(), m_Constant(C0))))
     return nullptr;
-  // Canonicalize Cmp0 into the form we expect.
+
+  if (!isa<SelectInst>(Sel1)) {
+    Pred0 = ICmpInst::getInversePredicate(Pred0);
+    std::swap(X, Sel1);
+  }
+
+  // Canonicalize Cmp0 into ult or uge.
   // FIXME: we shouldn't care about lanes that are 'undef' in the end?
-  switch (Cmp0.getPredicate()) {
+  switch (Pred0) {
   case ICmpInst::Predicate::ICMP_ULT:
+  case ICmpInst::Predicate::ICMP_UGE:
     // Although icmp ult %x, 0 is an unusual thing to try and should generally
     // have been simplified, it does not verify with undef inputs so ensure we
     // are not in a strange state.
     if (!match(C0, m_SpecificInt_ICMP(
                        ICmpInst::Predicate::ICMP_NE,
                        APInt::getZero(C0->getType()->getScalarSizeInBits()))))
       return nullptr;
     break; // Great!
   case ICmpInst::Predicate::ICMP_ULE:
-    // We'd have to increment C0 by one, and for that it must not have all-ones
-    // element, but then it would have been canonicalized to 'ult' before
-    // we get here. So we can't do anything useful with 'ule'.
-    return nullptr;
   case ICmpInst::Predicate::ICMP_UGT:
-    // We want to canonicalize it to 'ult', so we'll need to increment C0,
-    // which again means it must not have any all-ones elements.
+    // We want to canonicalize it to 'ult' or 'uge', so we'll need to increment
+    // C0, which again means it must not have any all-ones elements.
     if (!match(C0,
                m_SpecificInt_ICMP(
                    ICmpInst::Predicate::ICMP_NE,
                    APInt::getAllOnes(C0->getType()->getScalarSizeInBits()))))
       return nullptr; // Can't do, have all-ones element[s].
     C0 = InstCombiner::AddOne(C0);
-    std::swap(X, Sel1);
     break;
-  case ICmpInst::Predicate::ICMP_UGE:
-    // The only way we'd get this predicate if this `icmp` has extra uses,
-    // but then we won't be able to do this fold.
-    return nullptr;
   default:
     return nullptr; // Unknown predicate.
   }
 
   // Now that we've canonicalized the ICmp, we know the X we expect;
   // the select in other hand should be one-use.
   if (!Sel1->hasOneUse())
     return nullptr;
case ICmpInst::Predicate::ICMP_SGE:
     break;
   default:
     return nullptr; // Unknown predicate.
   }
 
   // The thresholds of this clamp-like pattern.
   auto *ThresholdLowIncl = ConstantExpr::getNeg(C1);
   auto *ThresholdHighExcl = ConstantExpr::getSub(C0, C1);
+  if (Pred0 == ICmpInst::Predicate::ICMP_UGE)
+    std::swap(ThresholdLowIncl, ThresholdHighExcl);
 
   // The fold has a precondition 1: C2 s>= ThresholdLow
   auto *Precond1 = ConstantExpr::getICmp(ICmpInst::Predicate::ICMP_SGE, C2,
                                          ThresholdLowIncl);
   if (!match(Precond1, m_One()))
     return nullptr;
   // The fold has a precondition 2: C2 s<= ThresholdHigh
   auto *Precond2 = ConstantExpr::getICmp(ICmpInst::Predicate::ICMP_SLE, C2,

llvm/test/CodeGen/BPF/adjust-opt-icmp1.ll

entry:
   br i1 %cmp, label %if.then, label %lor.lhs.false
 
 ; CHECK:         [[REG1:r[0-9]+]] <<= 32
 ; CHECK:         [[REG1]] s>>= 32
 ; CHECK:         [[REG2:r[0-9]+]] = 1
 ; CHECK:         if [[REG2]] s> [[REG1]] goto
 ; CHECK:         if [[REG1]] s> 7 goto
 
-; CHECK-DISABLE: [[REG1:r[0-9]+]] += -1
+; CHECK-DISABLE: [[REG1:r[0-9]+]] += -8
 ; CHECK-DISABLE: [[REG1]] <<= 32
 ; CHECK-DISABLE: [[REG1]] >>= 32
-; CHECK-DISABLE: if [[REG1]] > 6 goto
+; CHECK-DISABLE: [[REG2:r[0-9]+]] = 4294967289
+; CHECK-DISABLE: if [[REG2]] > [[REG1]] goto
 
 lor.lhs.false:                                    ; preds = %entry
   %2 = load i32, i32* %ret, align 4, !tbaa !2
   %cmp1 = icmp sgt i32 %2, 7
   br i1 %cmp1, label %if.then, label %if.end
 
 if.then:                                          ; preds = %lor.lhs.false, %entry
   store i32 0, i32* %retval, align 4

llvm/test/CodeGen/BPF/adjust-opt-icmp2.ll

entry:
   br i1 %cmp, label %if.then, label %if.end
 
 ; CHECK:         [[REG1:r[0-9]+]] <<= 32
 ; CHECK:         [[REG1]] s>>= 32
 ; CHECK:         [[REG2:r[0-9]+]] = 1
 ; CHECK:         if [[REG2]] s> [[REG1]] goto
 ; CHECK:         if [[REG1]] s> 7 goto
 
-; CHECK-DISABLE: [[REG1:r[0-9]+]] += -1
+; CHECK-DISABLE: [[REG1:r[0-9]+]] += -8
 ; CHECK-DISABLE: [[REG1]] <<= 32
 ; CHECK-DISABLE: [[REG1]] >>= 32
-; CHECK-DISABLE: if [[REG1]] > 6 goto
+; CHECK-DISABLE: [[REG2:r[0-9]+]] = 4294967289
+; CHECK-DISABLE: if [[REG2]] > [[REG1]] goto
 
 if.then:                                          ; preds = %entry
   store i32 0, i32* %retval, align 4
   store i32 1, i32* %cleanup.dest.slot, align 4
   br label %cleanup
 
 if.end:                                           ; preds = %entry
   %2 = load i32, i32* %ret, align 4, !tbaa !2

llvm/test/Transforms/InstCombine/2006-12-15-Range-Test.ll

 ; CHECK-NEXT:    store i32 [[TMP16:%.*]], i32* [[TMP16_OUT:%.*]], align 4
 ; CHECK-NEXT:    ret i1 true
 ; CHECK:       cond_next23.exitStub:
 ; CHECK-NEXT:    store i32 [[TMP16]], i32* [[TMP16_OUT]], align 4
 ; CHECK-NEXT:    ret i1 false
 ; CHECK:       cond_true:
 ; CHECK-NEXT:    [[TMP15:%.*]] = getelementptr [17 x i32], [17 x i32]* @r, i32 0, i32 [[TMP12_RELOAD:%.*]]
 ; CHECK-NEXT:    [[TMP16]] = load i32, i32* [[TMP15]], align 4
-; CHECK-NEXT:    [[TMP16_OFF:%.*]] = add i32 [[TMP16]], 31
-; CHECK-NEXT:    [[TMP0:%.*]] = icmp ugt i32 [[TMP16_OFF]], 62
-; CHECK-NEXT:    br i1 [[TMP0]], label [[BB27_EXITSTUB:%.*]], label [[COND_NEXT23_EXITSTUB:%.*]]
+; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[TMP16]], -32
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[TMP0]], -63
+; CHECK-NEXT:    br i1 [[TMP1]], label [[BB27_EXITSTUB:%.*]], label [[COND_NEXT23_EXITSTUB:%.*]]
 ;
 newFuncRoot:
   br label %cond_true
 
 bb27.exitStub:          ; preds = %cond_true
   store i32 %tmp16, i32* %tmp16.out
   ret i1 true
 

 ; CHECK-NEXT:    store i32 [[TMP16:%.*]], i32* [[TMP16_OUT:%.*]], align 4
 ; CHECK-NEXT:    ret i1 true
 ; CHECK:       cond_next23.exitStub:
 ; CHECK-NEXT:    store i32 [[TMP16]], i32* [[TMP16_OUT]], align 4
 ; CHECK-NEXT:    ret i1 false
 ; CHECK:       cond_true:
 ; CHECK-NEXT:    [[TMP15:%.*]] = getelementptr [17 x i32], [17 x i32]* @r, i32 0, i32 [[TMP12_RELOAD:%.*]]
 ; CHECK-NEXT:    [[TMP16]] = load i32, i32* [[TMP15]], align 4
-; CHECK-NEXT:    [[TMP16_OFF:%.*]] = add i32 [[TMP16]], 31
-; CHECK-NEXT:    [[TMP0:%.*]] = icmp ugt i32 [[TMP16_OFF]], 62
-; CHECK-NEXT:    br i1 [[TMP0]], label [[BB27_EXITSTUB:%.*]], label [[COND_NEXT23_EXITSTUB:%.*]]
+; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[TMP16]], -32
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[TMP0]], -63
+; CHECK-NEXT:    br i1 [[TMP1]], label [[BB27_EXITSTUB:%.*]], label [[COND_NEXT23_EXITSTUB:%.*]]
 ;
 newFuncRoot:
   br label %cond_true
 
 bb27.exitStub:          ; preds = %cond_true
   store i32 %tmp16, i32* %tmp16.out
   ret i1 true
 

llvm/test/Transforms/InstCombine/2007-03-21-SignedRangeTest.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 ; For PR1248
 
 define i1 @test(i32 %tmp6) {
 ; CHECK-LABEL: @test(
-; CHECK-NEXT:    [[TMP6_OFF:%.*]] = add i32 %tmp6, 83
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[TMP6_OFF]], 11
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[TMP6:%.*]], 71
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -12
+; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %tmp7 = sdiv i32 %tmp6, 12
   icmp ne i32 %tmp7, -6
   ret i1 %1
 }
 
 define <2 x i1> @test_vec(<2 x i32> %tmp6) {
 ; CHECK-LABEL: @test_vec(
-; CHECK-NEXT:    [[TMP6_OFF:%.*]] = add <2 x i32> %tmp6, <i32 83, i32 83>
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt <2 x i32> [[TMP6_OFF]], <i32 11, i32 11>
-; CHECK-NEXT:    ret <2 x i1> [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[TMP6:%.*]], <i32 71, i32 71>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 -12, i32 -12>
+; CHECK-NEXT:    ret <2 x i1> [[TMP2]]
 ;
   %tmp7 = sdiv <2 x i32> %tmp6, <i32 12, i32 12>
   icmp ne <2 x i32> %tmp7, <i32 -6, i32 -6>
   ret <2 x i1> %1
 }
 

llvm/test/Transforms/InstCombine/2008-08-05-And.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 ; PR2629
 
 define void @f(i8* %x) nounwind  {
 ; CHECK-LABEL: @f(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[BB:%.*]]
 ; CHECK:       bb:
 ; CHECK-NEXT:    [[L1:%.*]] = load i8, i8* [[X:%.*]], align 1
-; CHECK-NEXT:    [[S1:%.*]] = add i8 [[L1]], -6
-; CHECK-NEXT:    [[C1:%.*]] = icmp ugt i8 [[S1]], 2
-; CHECK-NEXT:    [[S2:%.*]] = add i8 [[L1]], -10
-; CHECK-NEXT:    [[C2:%.*]] = icmp ugt i8 [[S2]], 2
+; CHECK-NEXT:    [[TMP0:%.*]] = add i8 [[L1]], -9
+; CHECK-NEXT:    [[C1:%.*]] = icmp ult i8 [[TMP0]], -3
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[L1]], -13
+; CHECK-NEXT:    [[C2:%.*]] = icmp ult i8 [[TMP1]], -3
 ; CHECK-NEXT:    [[A1:%.*]] = and i1 [[C1]], [[C2]]
 ; CHECK-NEXT:    br i1 [[A1]], label [[INCOMPATIBLE:%.*]], label [[OKAY:%.*]]
 ; CHECK:       okay:
 ; CHECK-NEXT:    ret void
 ; CHECK:       incompatible:
 ; CHECK-NEXT:    ret void
 ;
 entry:

 }
 
 define void @f_logical(i8* %x) nounwind  {
 ; CHECK-LABEL: @f_logical(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[BB:%.*]]
 ; CHECK:       bb:
 ; CHECK-NEXT:    [[L1:%.*]] = load i8, i8* [[X:%.*]], align 1
-; CHECK-NEXT:    [[S1:%.*]] = add i8 [[L1]], -6
-; CHECK-NEXT:    [[C1:%.*]] = icmp ugt i8 [[S1]], 2
-; CHECK-NEXT:    [[S2:%.*]] = add i8 [[L1]], -10
-; CHECK-NEXT:    [[C2:%.*]] = icmp ugt i8 [[S2]], 2
+; CHECK-NEXT:    [[TMP0:%.*]] = add i8 [[L1]], -9
+; CHECK-NEXT:    [[C1:%.*]] = icmp ult i8 [[TMP0]], -3
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[L1]], -13
+; CHECK-NEXT:    [[C2:%.*]] = icmp ult i8 [[TMP1]], -3
 ; CHECK-NEXT:    [[A1:%.*]] = and i1 [[C1]], [[C2]]
 ; CHECK-NEXT:    br i1 [[A1]], label [[INCOMPATIBLE:%.*]], label [[OKAY:%.*]]
 ; CHECK:       okay:
 ; CHECK-NEXT:    ret void
 ; CHECK:       incompatible:
 ; CHECK-NEXT:    ret void
 ;
 entry:

llvm/test/Transforms/InstCombine/and-or-icmps.ll

;
   %or = select i1 %cmp1, i1 true, i1 %cmp2
   ret i1 %or
 }
 
 ; (X != 40 | X != 39) -> X-39 >u 1
 
 define i1 @and_ne_with_diff_one(i32 %x) {
 ; CHECK-LABEL: @and_ne_with_diff_one(
-; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -39
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ugt i32 [[TMP1]], 1
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -41
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2
 ; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %cmp1 = icmp ne i32 %x, 40
   %cmp2 = icmp ne i32 %x, 39
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @and_ne_with_diff_one_logical(i32 %x) {
 ; CHECK-LABEL: @and_ne_with_diff_one_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -39
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ugt i32 [[TMP1]], 1
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -41
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2
 ; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %cmp1 = icmp ne i32 %x, 40
   %cmp2 = icmp ne i32 %x, 39
   %and = select i1 %cmp1, i1 %cmp2, i1 false
   ret i1 %and
 }
 
;
   %cmp1 = icmp eq i32 %x, 0
   %cmp2 = icmp eq i32 %x, -1
   %or = select i1 %cmp1, i1 true, i1 %cmp2
   ret i1 %or
 }
 
 define i1 @and_ne_with_diff_one_signed(i64 %x) {
 ; CHECK-LABEL: @and_ne_with_diff_one_signed(
-; CHECK-NEXT:    [[TMP1:%.*]] = add i64 [[X:%.*]], 1
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ugt i64 [[TMP1]], 1
+; CHECK-NEXT:    [[TMP1:%.*]] = add i64 [[X:%.*]], -1
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i64 [[TMP1]], -2
 ; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %cmp1 = icmp ne i64 %x, -1
   %cmp2 = icmp ne i64 %x, 0
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @and_ne_with_diff_one_signed_logical(i64 %x) {
 ; CHECK-LABEL: @and_ne_with_diff_one_signed_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = add i64 [[X:%.*]], 1
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ugt i64 [[TMP1]], 1
+; CHECK-NEXT:    [[TMP1:%.*]] = add i64 [[X:%.*]], -1
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i64 [[TMP1]], -2
 ; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %cmp1 = icmp ne i64 %x, -1
   %cmp2 = icmp ne i64 %x, 0
   %and = select i1 %cmp1, i1 %cmp2, i1 false
   ret i1 %and
 }
 
 ; Vectors with splat constants get the same folds.
 
 define <2 x i1> @or_eq_with_one_bit_diff_constants2_splatvec(<2 x i32> %x) {
 ; CHECK-LABEL: @or_eq_with_one_bit_diff_constants2_splatvec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 -33, i32 -33>
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP1]], <i32 65, i32 65>
 ; CHECK-NEXT:    ret <2 x i1> [[TMP2]]
 ;
   %cmp1 = icmp eq <2 x i32> %x, <i32 97, i32 97>
   %cmp2 = icmp eq <2 x i32> %x, <i32 65, i32 65>
   %or = or <2 x i1> %cmp1, %cmp2
   ret <2 x i1> %or
 }
 
 define <2 x i1> @and_ne_with_diff_one_splatvec(<2 x i32> %x) {
 ; CHECK-LABEL: @and_ne_with_diff_one_splatvec(
-; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 -39, i32 -39>
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ugt <2 x i32> [[TMP1]], <i32 1, i32 1>
+; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 -41, i32 -41>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 -2, i32 -2>
 ; CHECK-NEXT:    ret <2 x i1> [[TMP2]]
 ;
   %cmp1 = icmp ne <2 x i32> %x, <i32 40, i32 40>
   %cmp2 = icmp ne <2 x i32> %x, <i32 39, i32 39>
   %and = and <2 x i1> %cmp1, %cmp2
   ret <2 x i1> %and
 }
 
;
   %c1 = icmp uge i32 %x, 2147483648
   %c2 = icmp eq i32 %x, 0
   %c = select i1 %c1, i1 true, i1 %c2
   ret i1 %c
 }
 
 define i1 @PR42691_5(i32 %x) {
 ; CHECK-LABEL: @PR42691_5(
-; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[X_OFF]], 2147483645
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -2147483647
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483646
+; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %c1 = icmp slt i32 %x, 1
   %c2 = icmp eq i32 %x, 2147483647
   %c = or i1 %c1, %c2
   ret i1 %c
 }
 
 define i1 @PR42691_5_logical(i32 %x) {
 ; CHECK-LABEL: @PR42691_5_logical(
-; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[X_OFF]], 2147483645
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -2147483647
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483646
+; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %c1 = icmp slt i32 %x, 1
   %c2 = icmp eq i32 %x, 2147483647
   %c = select i1 %c1, i1 true, i1 %c2
   ret i1 %c
 }
 
 define i1 @PR42691_6(i32 %x) {
 ; CHECK-LABEL: @PR42691_6(
-; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], 2147483647
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[X_OFF]], 2147483645
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483646
+; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %c1 = icmp ult i32 %x, 2147483649
   %c2 = icmp eq i32 %x, 4294967295
   %c = or i1 %c1, %c2
   ret i1 %c
 }
 
 define i1 @PR42691_6_logical(i32 %x) {
 ; CHECK-LABEL: @PR42691_6_logical(
-; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], 2147483647
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[X_OFF]], 2147483645
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483646
+; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %c1 = icmp ult i32 %x, 2147483649
   %c2 = icmp eq i32 %x, 4294967295
   %c = select i1 %c1, i1 true, i1 %c2
   ret i1 %c
 }
 
 define i1 @PR42691_7(i32 %x) {

llvm/test/Transforms/InstCombine/canonicalize-signed-truncation-check.ll

 ; Where  KeptBits = bitwidth(%x) - MaskedBits
 
 ; ============================================================================ ;
 ; Basic positive tests
 ; ============================================================================ ;
 
 define i1 @p0(i8 %x) {
 ; CHECK-LABEL: @p0(
-; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X:%.*]], 4
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ugt i8 [[TMP1]], 7
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X:%.*]], -4
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i8 [[TMP1]], -8
 ; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %tmp0 = shl i8 %x, 5
   %tmp1 = ashr exact i8 %tmp0, 5
   %tmp2 = icmp ne i8 %tmp1, %x
   ret i1 %tmp2
 }
 

 }
 
 ; ============================================================================ ;
 ; Vector tests
 ; ============================================================================ ;
 
 define <2 x i1> @p1_vec_splat(<2 x i8> %x) {
 ; CHECK-LABEL: @p1_vec_splat(
-; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i8> [[X:%.*]], <i8 4, i8 4>
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ugt <2 x i8> [[TMP1]], <i8 7, i8 7>
+; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i8> [[X:%.*]], <i8 -4, i8 -4>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult <2 x i8> [[TMP1]], <i8 -8, i8 -8>
 ; CHECK-NEXT:    ret <2 x i1> [[TMP2]]
 ;
   %tmp0 = shl <2 x i8> %x, <i8 5, i8 5>
   %tmp1 = ashr exact <2 x i8> %tmp0, <i8 5, i8 5>
   %tmp2 = icmp ne <2 x i8> %tmp1, %x
   ret <2 x i1> %tmp2
 }
 

 ; Commutativity tests.
 ; ============================================================================ ;
 
 declare i8 @gen8()
 
 define i1 @c0() {
 ; CHECK-LABEL: @c0(
 ; CHECK-NEXT:    [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X]], 4
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ugt i8 [[TMP1]], 7
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X]], -4
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i8 [[TMP1]], -8
 ; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %x = call i8 @gen8()
   %tmp0 = shl i8 %x, 5
   %tmp1 = ashr exact i8 %tmp0, 5
   %tmp2 = icmp ne i8 %x, %tmp1 ; swapped order
   ret i1 %tmp2
 }
 
 ; ============================================================================ ;
 ; One-use tests.
 ; ============================================================================ ;
 
 declare void @use8(i8)
 
 define i1 @n_oneuse0(i8 %x) {
 ; CHECK-LABEL: @n_oneuse0(
 ; CHECK-NEXT:    [[TMP0:%.*]] = shl i8 [[X:%.*]], 5
 ; CHECK-NEXT:    call void @use8(i8 [[TMP0]])
-; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X]], 4
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ugt i8 [[TMP1]], 7
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X]], -4
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i8 [[TMP1]], -8
 ; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %tmp0 = shl i8 %x, 5
   call void @use8(i8 %tmp0)
   %tmp1 = ashr exact i8 %tmp0, 5
   %tmp2 = icmp ne i8 %tmp1, %x
   ret i1 %tmp2
 }

llvm/test/Transforms/InstCombine/icmp-add.ll

 ;
   %a6 = add i8 %in, 71
   %a18 = icmp ult i8 %a6, 12
   ret i1 %a18
 }
 
 define i1 @uge_add_nonuw(i32 %in) {
 ; CHECK-LABEL: @uge_add_nonuw(
-; CHECK-NEXT:    [[A6:%.*]] = add i32 [[IN:%.*]], 3
-; CHECK-NEXT:    [[A18:%.*]] = icmp ugt i32 [[A6]], 11
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[IN:%.*]], -9
+; CHECK-NEXT:    [[A18:%.*]] = icmp ult i32 [[TMP1]], -12
 ; CHECK-NEXT:    ret i1 [[A18]]
 ;
   %a6 = add i32 %in, 3
   %a18 = icmp uge i32 %a6, 12
   ret i1 %a18
 }
 
 ; Test unsigned add overflow patterns. The div ops are only here to
;
   %ov = icmp ugt <2 x i5> %t, <i5 24, i5 24>
   ret <2 x i1> %ov
 }
 
 ; negative test - constants must differ by SMAX
 
 define i1 @ugt_wrong_offset(i8 %a) {
 ; CHECK-LABEL: @ugt_wrong_offset(
-; CHECK-NEXT:    [[T:%.*]] = add i8 [[A:%.*]], 123
-; CHECK-NEXT:    [[OV:%.*]] = icmp ugt i8 [[T]], -5
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[A:%.*]], 127
+; CHECK-NEXT:    [[OV:%.*]] = icmp ult i8 [[TMP1]], 4
 ; CHECK-NEXT:    ret i1 [[OV]]
 ;
   %t = add i8 %a, 123
   %ov = icmp ugt i8 %t, 251
   ret i1 %ov
 }
 
 define i1 @ugt_offset_nuw(i8 %a) {

llvm/test/Transforms/InstCombine/icmp-sub.ll

 ;
   %y = sub nuw i64 10, %x
   %z = icmp slt i64 %y, 3
   ret i1 %z
 }
 
 define i1 @test_negative_nsw_and_unsigned_pred(i64 %x) {
 ; CHECK-LABEL: @test_negative_nsw_and_unsigned_pred(
-; CHECK-NEXT:    [[NOTSUB:%.*]] = add nsw i64 [[X:%.*]], -11
-; CHECK-NEXT:    [[Z:%.*]] = icmp ugt i64 [[NOTSUB]], -4
+; CHECK-NEXT:    [[TMP1:%.*]] = add i64 [[X:%.*]], -8
+; CHECK-NEXT:    [[Z:%.*]] = icmp ult i64 [[TMP1]], 3
 ; CHECK-NEXT:    ret i1 [[Z]]
 ;
   %y = sub nsw i64 10, %x
   %z = icmp ult i64 %y, 3
   ret i1 %z
 }
 
 define i1 @test_negative_combined_sub_unsigned_overflow(i64 %x) {

llvm/test/Transforms/InstCombine/icmp-topbitssame.ll

;
   %conv1.i = trunc i16 %add to i8
   %shr2.i = ashr i8 %conv1.i, 7
   %cmp.not.i = icmp eq i8 %conv.i, %shr2.i
   ret i1 %cmp.not.i
 }
 
 define i1 @testi16i8_ne(i16 %add) {
 ; CHECK-LABEL: @testi16i8_ne(
-; CHECK-NEXT:    [[TMP1:%.*]] = add i16 [[ADD:%.*]], 128
-; CHECK-NEXT:    [[CMP_NOT_I:%.*]] = icmp ugt i16 [[TMP1]], 255
+; CHECK-NEXT:    [[TMP1:%.*]] = add i16 [[ADD:%.*]], -128
+; CHECK-NEXT:    [[CMP_NOT_I:%.*]] = icmp ult i16 [[TMP1]], -256
 ; CHECK-NEXT:    ret i1 [[CMP_NOT_I]]
 ;
   %sh = lshr i16 %add, 8
   %conv.i = trunc i16 %sh to i8
   %conv1.i = trunc i16 %add to i8
   %shr2.i = ashr i8 %conv1.i, 7
   %cmp.not.i = icmp ne i8 %shr2.i, %conv.i
   ret i1 %cmp.not.i
 }
 
 define i1 @testi16i8_ne_com(i16 %add) {
 ; CHECK-LABEL: @testi16i8_ne_com(
-; CHECK-NEXT:    [[TMP1:%.*]] = add i16 [[ADD:%.*]], 128
-; CHECK-NEXT:    [[CMP_NOT_I:%.*]] = icmp ugt i16 [[TMP1]], 255
+; CHECK-NEXT:    [[TMP1:%.*]] = add i16 [[ADD:%.*]], -128
+; CHECK-NEXT:    [[CMP_NOT_I:%.*]] = icmp ult i16 [[TMP1]], -256
 ; CHECK-NEXT:    ret i1 [[CMP_NOT_I]]
 ;
   %sh = lshr i16 %add, 8
   %conv.i = trunc i16 %sh to i8
   %conv1.i = trunc i16 %add to i8
   %shr2.i = ashr i8 %conv1.i, 7
   %cmp.not.i = icmp ne i8 %conv.i, %shr2.i
   ret i1 %cmp.not.i
;
   %conv1.i = trunc i64 %add to i32
   %shr2.i = ashr i32 %conv1.i, 31
   %cmp.not.i = icmp eq i32 %shr2.i, %conv.i
   ret i1 %cmp.not.i
 }
 
 define i1 @testi64i32_ne(i64 %add) {
 ; CHECK-LABEL: @testi64i32_ne(
-; CHECK-NEXT:    [[TMP1:%.*]] = add i64 [[ADD:%.*]], 2147483648
-; CHECK-NEXT:    [[CMP_NOT_I:%.*]] = icmp ugt i64 [[TMP1]], 4294967295
+; CHECK-NEXT:    [[TMP1:%.*]] = add i64 [[ADD:%.*]], -2147483648
+; CHECK-NEXT:    [[CMP_NOT_I:%.*]] = icmp ult i64 [[TMP1]], -4294967296
 ; CHECK-NEXT:    ret i1 [[CMP_NOT_I]]
 ;
   %sh = lshr i64 %add, 32
   %conv.i = trunc i64 %sh to i32
   %conv1.i = trunc i64 %add to i32
   %shr2.i = ashr i32 %conv1.i, 31
   %cmp.not.i = icmp ne i32 %shr2.i, %conv.i
   ret i1 %cmp.not.i

llvm/test/Transforms/InstCombine/load-cmp.ll

;
   %P = getelementptr inbounds [6 x double], [6 x double]* @GD, i32 0, i32 %X
   %Q = load double, double* %P
   %R = fcmp ogt double %Q, 0.0
   ret i1 %R
 }
 
 define i1 @test7(i32 %X) {
 ; CHECK-LABEL: @test7(
-; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[R:%.*]] = icmp ugt i32 [[TMP1]], 2
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -4
+; CHECK-NEXT:    [[R:%.*]] = icmp ult i32 [[TMP1]], -3
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %P = getelementptr inbounds [6 x double], [6 x double]* @GD, i32 0, i32 %X
   %Q = load double, double* %P
   %R = fcmp olt double %Q, 0.0
   ret i1 %R
 }
 

llvm/test/Transforms/InstCombine/minmax-fold.ll

;
   %a = add nuw i32 %x, 15
   %c = icmp sgt i32 %a, 42
   %r = select i1 %c, i32 %a, i32 42
   ret i32 %r
 }
 
 ; Negative test
 
+; Without the nuw that would allow pushing the add through the umax, the
+; add + icmp ugt combination can be interpreted as a range check, and would
+; normally be canonicalized to use ult instead. However, this is not done when
+; used as part of a umax to avoid breaking the SPF pattern.
 define i32 @add_umax_wrong_wrap(i32 %x) {
 ; CHECK-LABEL: @add_umax_wrong_wrap(
 ; CHECK-NEXT:    [[A:%.*]] = add nsw i32 [[X:%.*]], 15
 ; CHECK-NEXT:    [[C:%.*]] = icmp ugt i32 [[A]], 42
 ; CHECK-NEXT:    [[R:%.*]] = select i1 [[C]], i32 [[A]], i32 42
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %a = add nsw i32 %x, 15

llvm/test/Transforms/InstCombine/or.ll

;
   %C = and i32 %A, 4
   ; %D = and int %B, 5
   %D = or i32 %B, %C
   ret i32 %D
 }
 
 define i1 @test18(i32 %A) {
 ; CHECK-LABEL: @test18(
-; CHECK-NEXT:    [[A_OFF:%.*]] = add i32 [[A:%.*]], -50
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[A_OFF]], 49
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[A:%.*]], -100
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -50
+; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %B = icmp sge i32 %A, 100
   %C = icmp slt i32 %A, 50
   %D = or i1 %B, %C
   ret i1 %D
 }
 
 define i1 @test18_logical(i32 %A) {
 ; CHECK-LABEL: @test18_logical(
-; CHECK-NEXT:    [[A_OFF:%.*]] = add i32 [[A:%.*]], -50
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[A_OFF]], 49
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[A:%.*]], -100
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -50
+; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %B = icmp sge i32 %A, 100
   %C = icmp slt i32 %A, 50
   %D = select i1 %B, i1 true, i1 %C
   ret i1 %D
 }
 
 ; FIXME: Vectors should fold too.

llvm/test/Transforms/InstCombine/overflow.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -instcombine < %s | FileCheck %s
 ; <rdar://problem/8558713>
 
 declare void @throwAnExceptionOrWhatever()
 
 define i32 @test1(i32 %a, i32 %b) nounwind ssp {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[SADD:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[B:%.*]], i32 [[A:%.*]])
 ; CHECK-NEXT:    [[TMP0:%.*]] = extractvalue { i32, i1 } [[SADD]], 1
 ; CHECK-NEXT:    br i1 [[TMP0]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
 ; CHECK:       if.then:
-; CHECK-NEXT:    tail call void @throwAnExceptionOrWhatever() #2
+; CHECK-NEXT:    tail call void @throwAnExceptionOrWhatever() #[[ATTR2:[0-9]+]]
 ; CHECK-NEXT:    br label [[IF_END]]
 ; CHECK:       if.end:
 ; CHECK-NEXT:    [[SADD_RESULT:%.*]] = extractvalue { i32, i1 } [[SADD]], 0
 ; CHECK-NEXT:    ret i32 [[SADD_RESULT]]
 ;
 entry:
   %conv = sext i32 %a to i64
   %conv2 = sext i32 %b to i64

 ; CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[A:%.*]] to i64
 ; CHECK-NEXT:    [[CONV2:%.*]] = sext i32 [[B:%.*]] to i64
 ; CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[CONV2]], [[CONV]]
 ; CHECK-NEXT:    [[ADD_OFF:%.*]] = add nsw i64 [[ADD]], 2147483648
 ; CHECK-NEXT:    store i64 [[ADD_OFF]], i64* [[P:%.*]], align 4
 ; CHECK-NEXT:    [[TMP0:%.*]] = icmp ugt i64 [[ADD_OFF]], 4294967295
 ; CHECK-NEXT:    br i1 [[TMP0]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
 ; CHECK:       if.then:
-; CHECK-NEXT:    tail call void @throwAnExceptionOrWhatever() #2
+; CHECK-NEXT:    tail call void @throwAnExceptionOrWhatever() #[[ATTR2]]
 ; CHECK-NEXT:    br label [[IF_END]]
 ; CHECK:       if.end:
 ; CHECK-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
 ; CHECK-NEXT:    ret i32 [[CONV9]]
 ;
 entry:
   %conv = sext i32 %a to i64
   %conv2 = sext i32 %b to i64

 ; This is illegal to transform because the high bits of the original add are
 ; live out.
 define i64 @test3(i32 %a, i32 %b) nounwind ssp {
 ; CHECK-LABEL: @test3(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[A:%.*]] to i64
 ; CHECK-NEXT:    [[CONV2:%.*]] = sext i32 [[B:%.*]] to i64
 ; CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[CONV2]], [[CONV]]
-; CHECK-NEXT:    [[ADD_OFF:%.*]] = add nsw i64 [[ADD]], 2147483648
-; CHECK-NEXT:    [[TMP0:%.*]] = icmp ugt i64 [[ADD_OFF]], 4294967295
-; CHECK-NEXT:    br i1 [[TMP0]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK-NEXT:    [[TMP0:%.*]] = add nsw i64 [[ADD]], -2147483648
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i64 [[TMP0]], -4294967296
+; CHECK-NEXT:    br i1 [[TMP1]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
 ; CHECK:       if.then:
-; CHECK-NEXT:    tail call void @throwAnExceptionOrWhatever() #2
+; CHECK-NEXT:    tail call void @throwAnExceptionOrWhatever() #[[ATTR2]]
 ; CHECK-NEXT:    br label [[IF_END]]
 ; CHECK:       if.end:
 ; CHECK-NEXT:    ret i64 [[ADD]]
 ;
 entry:
   %conv = sext i32 %a to i64
   %conv2 = sext i32 %b to i64
   %add = add nsw i64 %conv2, %conv

 
 define zeroext i8 @test4(i8 signext %a, i8 signext %b) nounwind ssp {
 ; CHECK-LABEL: @test4(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[SADD:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[B:%.*]], i8 [[A:%.*]])
 ; CHECK-NEXT:    [[CMP:%.*]] = extractvalue { i8, i1 } [[SADD]], 1
 ; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
 ; CHECK:       if.then:
-; CHECK-NEXT:    tail call void @throwAnExceptionOrWhatever() #2
+; CHECK-NEXT:    tail call void @throwAnExceptionOrWhatever() #[[ATTR2]]
 ; CHECK-NEXT:    unreachable
 ; CHECK:       if.end:
 ; CHECK-NEXT:    [[SADD_RESULT:%.*]] = extractvalue { i8, i1 } [[SADD]], 0
 ; CHECK-NEXT:    ret i8 [[SADD_RESULT]]
 ;
 entry:
   %conv = sext i8 %a to i32
   %conv2 = sext i8 %b to i32

 ; PR11438
 ; This is @test1, but the operands are not sign-extended.  Make sure
 ; we don't transform this case.
 
 define i32 @test8(i64 %a, i64 %b) nounwind ssp {
 ; CHECK-LABEL: @test8(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[ADD:%.*]] = add i64 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[ADD_OFF:%.*]] = add i64 [[ADD]], 2147483648
-; CHECK-NEXT:    [[TMP0:%.*]] = icmp ugt i64 [[ADD_OFF]], 4294967295
-; CHECK-NEXT:    br i1 [[TMP0]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK-NEXT:    [[TMP0:%.*]] = add i64 [[ADD]], -2147483648
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i64 [[TMP0]], -4294967296
+; CHECK-NEXT:    br i1 [[TMP1]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
 ; CHECK:       if.then:
-; CHECK-NEXT:    tail call void @throwAnExceptionOrWhatever() #2
+; CHECK-NEXT:    tail call void @throwAnExceptionOrWhatever() #[[ATTR2]]
 ; CHECK-NEXT:    br label [[IF_END]]
 ; CHECK:       if.end:
 ; CHECK-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
 ; CHECK-NEXT:    ret i32 [[CONV9]]
 ;
 entry:
   %add = add i64 %a, %b
   %add.off = add i64 %add, 2147483648

llvm/test/Transforms/InstCombine/smulo.ll

 ;
   %res = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %a, i8 2)
   %overflow = extractvalue { i8, i1 } %res, 1
   ret i1 %overflow
 }
 
 define i1 @test_constant3(i8 %a) {
 ; CHECK-LABEL: @test_constant3(
-; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[A:%.*]], 42
-; CHECK-NEXT:    [[OVERFLOW:%.*]] = icmp ugt i8 [[TMP1]], 84
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[A:%.*]], -43
+; CHECK-NEXT:    [[OVERFLOW:%.*]] = icmp ult i8 [[TMP1]], -85
 ; CHECK-NEXT:    ret i1 [[OVERFLOW]]
 ;
   %res = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %a, i8 3)
   %overflow = extractvalue { i8, i1 } %res, 1
   ret i1 %overflow
 }
 
 define i1 @test_constant4(i8 %a) {
 ; CHECK-LABEL: @test_constant4(
-; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[A:%.*]], 32
-; CHECK-NEXT:    [[OVERFLOW:%.*]] = icmp ugt i8 [[TMP1]], 63
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[A:%.*]], -32
+; CHECK-NEXT:    [[OVERFLOW:%.*]] = icmp ult i8 [[TMP1]], -64
 ; CHECK-NEXT:    ret i1 [[OVERFLOW]]
 ;
   %res = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %a, i8 4)
   %overflow = extractvalue { i8, i1 } %res, 1
   ret i1 %overflow
 }
 
 
 define i1 @test_constant127(i8 %a) {
 ; CHECK-LABEL: @test_constant127(
-; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[A:%.*]], 1
-; CHECK-NEXT:    [[OVERFLOW:%.*]] = icmp ugt i8 [[TMP1]], 2
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[A:%.*]], -2
+; CHECK-NEXT:    [[OVERFLOW:%.*]] = icmp ult i8 [[TMP1]], -3
 ; CHECK-NEXT:    ret i1 [[OVERFLOW]]
 ;
   %res = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %a, i8 127)
   %overflow = extractvalue { i8, i1 } %res, 1
   ret i1 %overflow
 }
 
 define i1 @test_constant128(i8 %a) {