[X86][FP16] add alias for f*mul_*ch intrinsics

[FreddyYe]

Summary

*_mul_*ch is to align with *_mul_*s, *_mul_*d and *_mul_*h.

[pengfei]

*_mul_pch is to align with *_mul_ps annd *_mul_pd

And *_mul_ph?

[FreddyYe]

In D112777#3095847, @pengfei wrote:

*_mul_pch is to align with *_mul_ps annd *_mul_pd

And *_mul_ph?

Yes. Corrected in summary.

[FreddyYe]

clang-formats.

[FreddyYe]

Ping.

[pengfei]

clang/lib/Headers/avx512fp16intrin.h

3174

Missing these?
How about define all use macro together somewhere with comment to say thay are just aliases?

[pengfei]

Also missing *_sch.

[craig.topper]

Not directly related to this patch, but why is the suffix _pch and _sch when the instruction names end in CPH and CSH? It kind of seems like the correct intrinsic name would have been _mm_fmulc_ph.

Why does the name here need to be aligned with mul_ps/pd? This a "complex" multiply which is a different operation. Is gcc also going to add aliases?

[FreddyYe]

In D112777#3114502, @craig.topper wrote:

Not directly related to this patch, but why is the suffix _pch and _sch when the instruction names end in CPH and CSH? It kind of seems like the correct intrinsic name would have been _mm_fmulc_ph.

Why does the name here need to be aligned with mul_ps/pd? This a "complex" multiply which is a different operation. Is gcc also going to add aliases?

I can answer the second question. The prefix "f" can be judged as the mnemonic to distinguish fma instrinsics. The suffix "c" can be judged as the mnemonic of "complex". So add "f" mnemonic in this multiply intrinsics is ambiguous. gcc will add aliases, too. The first question is also a good question. But for now, it's not very conflict to old intrinsics, I think.

[FreddyYe]

Thx for review. I found I missed many intrinsics, including _fcmul_* series. they need to be aliased with cmul_*. pls wait for update.

[craig.topper]

In D112777#3114560, @FreddyYe wrote:

In D112777#3114502, @craig.topper wrote:

Not directly related to this patch, but why is the suffix _pch and _sch when the instruction names end in CPH and CSH? It kind of seems like the correct intrinsic name would have been _mm_fmulc_ph.

Why does the name here need to be aligned with mul_ps/pd? This a "complex" multiply which is a different operation. Is gcc also going to add aliases?

I can answer the second question. The prefix "f" can be judged as the mnemonic to distinguish fma instrinsics. The suffix "c" can be judged as the mnemonic of "complex". So add "f" mnemonic in this multiply intrinsics is ambiguous. gcc will add aliases, too. The first question is also a good question. But for now, it's not very conflict to old intrinsics, I think.

But the mnemonic for the instructions here do include an 'F'. While the mulps/mulpd instruction names do not include an 'F'. So we're creating new intrinsics that are further away from the mnemonics of the instructions. Is your argument that the instruction mnemonics are wrong and shouldn't include an 'F'?

[FreddyYe]

In D112777#3114566, @craig.topper wrote:

In D112777#3114560, @FreddyYe wrote:

In D112777#3114502, @craig.topper wrote:

Not directly related to this patch, but why is the suffix _pch and _sch when the instruction names end in CPH and CSH? It kind of seems like the correct intrinsic name would have been _mm_fmulc_ph.

Why does the name here need to be aligned with mul_ps/pd? This a "complex" multiply which is a different operation. Is gcc also going to add aliases?

I can answer the second question. The prefix "f" can be judged as the mnemonic to distinguish fma instrinsics. The suffix "c" can be judged as the mnemonic of "complex". So add "f" mnemonic in this multiply intrinsics is ambiguous. gcc will add aliases, too. The first question is also a good question. But for now, it's not very conflict to old intrinsics, I think.

But the mnemonic for the instructions here do include an 'F'. While the mulps/mulpd instruction names do not include an 'F'. So we're creating new intrinsics that are further away from the mnemonics of the instructions. Is your argument that the instruction mnemonics are wrong and shouldn't include an 'F'?

Yes, our intrinsics naming convention after instruction name rule should be followed, too. So this patch is just adding the alias but not replacing them. Yes, from my opinion, it's wrong.

[FreddyYe]

address comments. add alias for 36 intrinsics in all.

[FreddyYe]

Ping.

[pengfei]

LGTM. Please wait one or two days for other comments.

clang/lib/Headers/avx512fp16intrin.h

 
 static __inline__ __m512h __DEFAULT_FN_ATTRS512 _mm512_fmul_pch(__m512h __A,
                                                                 __m512h __B) {
   return (__m512h)__builtin_ia32_vfmulcph512_mask(
       (__v16sf)__A, (__v16sf)__B, (__v16sf)_mm512_undefined_ph(), (__mmask16)-1,
       _MM_FROUND_CUR_DIRECTION);
 }
 
+static __inline__ __m512h __DEFAULT_FN_ATTRS512 _mm512_mul_pch(__m512h __A,
+                                                               __m512h __B) {
+  return _mm512_fmul_pch(__A, __B);
+}
+
 static __inline__ __m512h __DEFAULT_FN_ATTRS512
 _mm512_mask_fmul_pch(__m512h __W, __mmask16 __U, __m512h __A, __m512h __B) {
   return (__m512h)__builtin_ia32_vfmulcph512_mask((__v16sf)__A, (__v16sf)__B,
                                                   (__v16sf)__W, (__mmask16)__U,
                                                   _MM_FROUND_CUR_DIRECTION);
 }
 
 static __inline__ __m512h __DEFAULT_FN_ATTRS512
+_mm512_mask_mul_pch(__m512h __W, __mmask16 __U, __m512h __A, __m512h __B) {
+  return _mm512_mask_fmul_pch(__W, __U, __A, __B);
+}
+
+static __inline__ __m512h __DEFAULT_FN_ATTRS512
 _mm512_maskz_fmul_pch(__mmask16 __U, __m512h __A, __m512h __B) {
   return (__m512h)__builtin_ia32_vfmulcph512_mask(
       (__v16sf)__A, (__v16sf)__B, (__v16sf)_mm512_setzero_ph(), (__mmask16)__U,
       _MM_FROUND_CUR_DIRECTION);
 }
 
+static __inline__ __m512h __DEFAULT_FN_ATTRS512
+_mm512_maskz_mul_pch(__mmask16 __U, __m512h __A, __m512h __B) {
+  return _mm512_maskz_fmul_pch(__U, __A, __B);
+}
+
 #define _mm512_fmul_round_pch(A, B, R)                                         \
   ((__m512h)__builtin_ia32_vfmulcph512_mask(                                   \
       (__v16sf)(__m512h)(A), (__v16sf)(__m512h)(B),                            \
       (__v16sf)(__m512h)_mm512_undefined_ph(), (__mmask16)-1, (int)(R)))
 
 #define _mm512_mask_fmul_round_pch(W, U, A, B, R)                              \
   ((__m512h)__builtin_ia32_vfmulcph512_mask(                                   \
       (__v16sf)(__m512h)(A), (__v16sf)(__m512h)(B), (__v16sf)(__m512h)(W),     \
       (__mmask16)(U), (int)(R)))

clang/lib/Headers/avx512vlfp16intrin.h

 }
 
 static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_fmul_pch(__m128h __A,
                                                              __m128h __B) {
   return (__m128h)__builtin_ia32_vfmulcph128_mask(
       (__v4sf)__A, (__v4sf)__B, (__v4sf)_mm_undefined_ph(), (__mmask8)-1);
 }
 
+static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_mul_pch(__m128h __A,
+                                                            __m128h __B) {
+  return _mm_fmul_pch(__A, __B);
+}
+
 static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_mask_fmul_pch(__m128h __W,
                                                                   __mmask8 __U,
                                                                   __m128h __A,
                                                                   __m128h __B) {
   return (__m128h)__builtin_ia32_vfmulcph128_mask((__v4sf)__A, (__v4sf)__B,
                                                   (__v4sf)__W, (__mmask8)__U);
 }
 
+static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_mask_mul_pch(__m128h __W,
+                                                                 __mmask8 __U,
+                                                                 __m128h __A,
+                                                                 __m128h __B) {
+  return _mm_mask_fmul_pch(__W, __U, __A, __B);
+}
+
 static __inline__ __m128h __DEFAULT_FN_ATTRS128
 _mm_maskz_fmul_pch(__mmask8 __U, __m128h __A, __m128h __B) {
   return (__m128h)__builtin_ia32_vfmulcph128_mask(
       (__v4sf)__A, (__v4sf)__B, (__v4sf)_mm_setzero_ph(), (__mmask8)__U);
 }
 
+static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_maskz_mul_pch(__mmask8 __U,
+                                                                  __m128h __A,
+                                                                  __m128h __B) {
+  return _mm_maskz_fmul_pch(__U, __A, __B);
+}
+
 static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_fmul_pch(__m256h __A,
                                                                 __m256h __B) {
   return (__m256h)__builtin_ia32_vfmulcph256_mask(
       (__v8sf)__A, (__v8sf)__B, (__v8sf)_mm256_undefined_ph(), (__mmask8)-1);
 }
 
+static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_mul_pch(__m256h __A,
+                                                               __m256h __B) {
+  return _mm256_fmul_pch(__A, __B);
+}
+
 static __inline__ __m256h __DEFAULT_FN_ATTRS256
 _mm256_mask_fmul_pch(__m256h __W, __mmask8 __U, __m256h __A, __m256h __B) {
   return (__m256h)__builtin_ia32_vfmulcph256_mask((__v8sf)__A, (__v8sf)__B,
                                                   (__v8sf)__W, (__mmask8)__U);
 }
 
 static __inline__ __m256h __DEFAULT_FN_ATTRS256
+_mm256_mask_mul_pch(__m256h __W, __mmask8 __U, __m256h __A, __m256h __B) {
+  return _mm256_mask_fmul_pch(__W, __U, __A, __B);
+}
+
+static __inline__ __m256h __DEFAULT_FN_ATTRS256
 _mm256_maskz_fmul_pch(__mmask8 __U, __m256h __A, __m256h __B) {
   return (__m256h)__builtin_ia32_vfmulcph256_mask(
       (__v8sf)__A, (__v8sf)__B, (__v8sf)_mm256_setzero_ph(), (__mmask8)__U);
 }
 
+static __inline__ __m256h __DEFAULT_FN_ATTRS256
+_mm256_maskz_mul_pch(__mmask8 __U, __m256h __A, __m256h __B) {
+  return _mm256_maskz_fmul_pch(__U, __A, __B);
+}
+
 static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_fmadd_pch(__m128h __A,
                                                               __m128h __B,
                                                               __m128h __C) {
   return (__m128h)__builtin_ia32_vfmaddcph128_mask((__v4sf)__A, (__v4sf)__B,
                                                    (__v4sf)__C, (__mmask8)-1);
 }
 
 static __inline__ __m128h __DEFAULT_FN_ATTRS128

clang/test/CodeGen/X86/avx512fp16-builtins.c

 }
 
 __m512h test_mm512_fmul_pch(__m512h __A, __m512h __B) {
   // CHECK-LABEL: @test_mm512_fmul_pch
   // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.512
   return _mm512_fmul_pch(__A, __B);
 }
 
+__m512h test_mm512_mul_pch(__m512h __A, __m512h __B) {
+  // CHECK-LABEL: @test_mm512_mul_pch
+  // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.512
+  return _mm512_mul_pch(__A, __B);
+}
+
 __m512h test_mm512_mask_fmul_pch(__m512h __W, __mmask16 __U, __m512h __A, __m512h __B) {
   // CHECK-LABEL: @test_mm512_mask_fmul_pch
   // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.512
   return _mm512_mask_fmul_pch(__W, __U, __A, __B);
 }
 
+__m512h test_mm512_mask_mul_pch(__m512h __W, __mmask16 __U, __m512h __A, __m512h __B) {
+  // CHECK-LABEL: @test_mm512_mask_mul_pch
+  // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.512
+  return _mm512_mask_mul_pch(__W, __U, __A, __B);
+}
+
 __m512h test_mm512_maskz_fmul_pch(__mmask16 __U, __m512h __A, __m512h __B) {
   // CHECK-LABEL: @test_mm512_maskz_fmul_pch
   // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.512
   return _mm512_maskz_fmul_pch(__U, __A, __B);
 }
 
+__m512h test_mm512_maskz_mul_pch(__mmask16 __U, __m512h __A, __m512h __B) {
+  // CHECK-LABEL: @test_mm512_maskz_mul_pch
+  // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.512
+  return _mm512_maskz_mul_pch(__U, __A, __B);
+}
+
 __m512h test_mm512_fmul_round_pch(__m512h __A, __m512h __B) {
   // CHECK-LABEL: @test_mm512_fmul_round_pch
   // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.512
   return _mm512_fmul_round_pch(__A, __B, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
 }
 
 __m512h test_mm512_mask_fmul_round_pch(__m512h __W, __mmask16 __U, __m512h __A, __m512h __B) {
   // CHECK-LABEL: @test_mm512_mask_fmul_round_pch

clang/test/CodeGen/X86/avx512vlfp16-builtins.c

 }
 
 __m128h test_mm_fmul_pch(__m128h __A, __m128h __B) {
   // CHECK-LABEL: @test_mm_fmul_pch
   // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.128
   return _mm_fmul_pch(__A, __B);
 }
 
+__m128h test_mm_mul_pch(__m128h __A, __m128h __B) {
+  // CHECK-LABEL: @test_mm_mul_pch
+  // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.128
+  return _mm_mul_pch(__A, __B);
+}
+
 __m128h test_mm_mask_fmul_pch(__m128h __W, __mmask8 __U, __m128h __A, __m128h __B) {
   // CHECK-LABEL: @test_mm_mask_fmul_pch
   // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.128
   return _mm_mask_fmul_pch(__W, __U, __A, __B);
 }
 
+__m128h test_mm_mask_mul_pch(__m128h __W, __mmask8 __U, __m128h __A, __m128h __B) {
+  // CHECK-LABEL: @test_mm_mask_mul_pch
+  // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.128
+  return _mm_mask_mul_pch(__W, __U, __A, __B);
+}
+
 __m128h test_mm_maskz_fmul_pch(__mmask8 __U, __m128h __A, __m128h __B) {
   // CHECK-LABEL: @test_mm_maskz_fmul_pch
   // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.128
   return _mm_maskz_fmul_pch(__U, __A, __B);
 }
 
+__m128h test_mm_maskz_mul_pch(__mmask8 __U, __m128h __A, __m128h __B) {
+  // CHECK-LABEL: @test_mm_maskz_mul_pch
+  // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.128
+  return _mm_maskz_mul_pch(__U, __A, __B);
+}
+
 __m256h test_mm256_fmul_pch(__m256h __A, __m256h __B) {
   // CHECK-LABEL: @test_mm256_fmul_pch
   // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.256
   return _mm256_fmul_pch(__A, __B);
 }
 
+__m256h test_mm256_mul_pch(__m256h __A, __m256h __B) {
+  // CHECK-LABEL: @test_mm256_mul_pch
+  // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.256
+  return _mm256_mul_pch(__A, __B);
+}
+
 __m256h test_mm256_mask_fmul_pch(__m256h __W, __mmask8 __U, __m256h __A, __m256h __B) {
   // CHECK-LABEL: @test_mm256_mask_fmul_pch
   // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.256
   return _mm256_mask_fmul_pch(__W, __U, __A, __B);
 }
 
+__m256h test_mm256_mask_mul_pch(__m256h __W, __mmask8 __U, __m256h __A, __m256h __B) {
+  // CHECK-LABEL: @test_mm256_mask_mul_pch
+  // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.256
+  return _mm256_mask_mul_pch(__W, __U, __A, __B);
+}
+
 __m256h test_mm256_maskz_fmul_pch(__mmask8 __U, __m256h __A, __m256h __B) {
   // CHECK-LABEL: @test_mm256_maskz_fmul_pch
   // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.256
   return _mm256_maskz_fmul_pch(__U, __A, __B);
 }
 
+__m256h test_mm256_maskz_mul_pch(__mmask8 __U, __m256h __A, __m256h __B) {
+  // CHECK-LABEL: @test_mm256_maskz_mul_pch
+  // CHECK: @llvm.x86.avx512fp16.mask.vfmul.cph.256
+  return _mm256_maskz_mul_pch(__U, __A, __B);
+}
+
 __m128h test_mm_fmadd_pch(__m128h __A, __m128h __B, __m128h __C) {
   // CHECK-LABEL: @test_mm_fmadd_pch
   // CHECK: @llvm.x86.avx512fp16.mask.vfmadd.cph.128
   return _mm_fmadd_pch(__A, __B, __C);
 }
 
 __m128h test_mm_mask_fmadd_pch(__m128h __A, __mmask8 __U, __m128h __B, __m128h __C) {
   // CHECK-LABEL: @test_mm_mask_fmadd_pch