[lldb] [ABI/AArch64] Do not add subregs if some of them are present

[mgorny]

Summary

Fix a bug introduced while refactoring ABIAArch64::AugmentRegisterInfo()
that caused subregisters to be added even if they were already present.
Instead, abort immediately if at least one subregister is found
(following ABIX86). While at it, add a test for that.

lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp

 void ABIAArch64::AugmentRegisterInfo(
     std::vector<lldb_private::DynamicRegisterInfo::Register> &regs) {
   lldb_private::MCBasedABI::AugmentRegisterInfo(regs);
 
   lldb_private::ConstString sp_string{"sp"};
 
   std::array<llvm::Optional<uint32_t>, 32> x_regs;
   std::array<llvm::Optional<uint32_t>, 32> v_regs;
-  std::bitset<32> have_w_regs;
-  std::bitset<32> have_s_regs;
-  std::bitset<32> have_d_regs;
 
   for (auto it : llvm::enumerate(regs)) {
     lldb_private::DynamicRegisterInfo::Register &info = it.value();
     // GDB sends x31 as "sp".  Add the "x31" alt_name for convenience.
     if (info.name == sp_string && !info.alt_name)
       info.alt_name.SetCString("x31");
 
     unsigned int reg_num;
     auto get_reg = [&info, &reg_num](const char *prefix) {
       llvm::StringRef reg_name = info.name.GetStringRef();
       llvm::StringRef alt_name = info.alt_name.GetStringRef();
       return (reg_name.consume_front(prefix) &&
               llvm::to_integer(reg_name, reg_num, 10) && reg_num < 32) ||
              (alt_name.consume_front(prefix) &&
               llvm::to_integer(alt_name, reg_num, 10) && reg_num < 32);
     };
 
     if (get_reg("x"))
       x_regs[reg_num] = it.index();
-    if (get_reg("v"))
+    else if (get_reg("v"))
       v_regs[reg_num] = it.index();
-    if (get_reg("w"))
-      have_w_regs[reg_num] = true;
-    if (get_reg("s"))
-      have_s_regs[reg_num] = true;
-    if (get_reg("d"))
-      have_d_regs[reg_num] = true;
+    // if we have at least one subregister, abort
+    else if (get_reg("w") || get_reg("s") || get_reg("d"))
+      return;
   }
 
   // Create aliases for partial registers: wN for xN, and sN/dN for vN.
   addPartialRegisters(regs, x_regs, 8, "w{0}", 4, lldb::eEncodingUint,
                       lldb::eFormatHex);
   addPartialRegisters(regs, v_regs, 16, "s{0}", 4, lldb::eEncodingIEEE754,
                       lldb::eFormatFloat);
   addPartialRegisters(regs, v_regs, 16, "d{0}", 8, lldb::eEncodingIEEE754,
                       lldb::eFormatFloat);
 }

lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py

def test_aarch64_regs(self):
                    ["d31 = 64"])
 
         self.runCmd("register write s0 32")
         self.match("register read v0",
                    ["v0 = {0x00 0x00 0x00 0x42 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"])
         self.runCmd("register write v31 '{0x00 0x00 0x00 0x43 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'")
         self.match("register read s31",
                    ["s31 = 128"])
+
+    @skipIfXmlSupportMissing
+    @skipIfRemote
+    @skipIfLLVMTargetMissing("AArch64")
+    def test_aarch64_no_duplicate_subregs(self):
+        """Test that duplicate subregisters are not added."""
+        class MyResponder(MockGDBServerResponder):
+            reg_data = (
+                "0102030405060708"  # x0
+                "1112131415161718"  # x1
+            ) + 27 * (
+                "2122232425262728"  # x2..x28
+            ) + (
+                "3132333435363738"  # x29 (fp)
+                "4142434445464748"  # x30 (lr)
+                "5152535455565758"  # x31 (sp)
+                "6162636465666768"  # pc
+                "71727374"  # cpsr
+            )
+
+            def qXferRead(self, obj, annex, offset, length):
+                if annex == "target.xml":
+                    return """<?xml version="1.0"?>
+                        <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+                        <target>
+                          <architecture>aarch64</architecture>
+                          <feature name="org.gnu.gdb.aarch64.core">
+                            <reg name="x0" bitsize="64" type="int" regnum="0"/>
+                            <reg name="x1" bitsize="64" type="int" regnum="1"/>
+                            <reg name="x2" bitsize="64" type="int" regnum="2"/>
+                            <reg name="x3" bitsize="64" type="int" regnum="3"/>
+                            <reg name="x4" bitsize="64" type="int" regnum="4"/>
+                            <reg name="x5" bitsize="64" type="int" regnum="5"/>
+                            <reg name="x6" bitsize="64" type="int" regnum="6"/>
+                            <reg name="x7" bitsize="64" type="int" regnum="7"/>
+                            <reg name="x8" bitsize="64" type="int" regnum="8"/>
+                            <reg name="x9" bitsize="64" type="int" regnum="9"/>
+                            <reg name="x10" bitsize="64" type="int" regnum="10"/>
+                            <reg name="x11" bitsize="64" type="int" regnum="11"/>
+                            <reg name="x12" bitsize="64" type="int" regnum="12"/>
+                            <reg name="x13" bitsize="64" type="int" regnum="13"/>
+                            <reg name="x14" bitsize="64" type="int" regnum="14"/>
+                            <reg name="x15" bitsize="64" type="int" regnum="15"/>
+                            <reg name="x16" bitsize="64" type="int" regnum="16"/>
+                            <reg name="x17" bitsize="64" type="int" regnum="17"/>
+                            <reg name="x18" bitsize="64" type="int" regnum="18"/>
+                            <reg name="x19" bitsize="64" type="int" regnum="19"/>
+                            <reg name="x20" bitsize="64" type="int" regnum="20"/>
+                            <reg name="x21" bitsize="64" type="int" regnum="21"/>
+                            <reg name="x22" bitsize="64" type="int" regnum="22"/>
+                            <reg name="x23" bitsize="64" type="int" regnum="23"/>
+                            <reg name="x24" bitsize="64" type="int" regnum="24"/>
+                            <reg name="x25" bitsize="64" type="int" regnum="25"/>
+                            <reg name="x26" bitsize="64" type="int" regnum="26"/>
+                            <reg name="x27" bitsize="64" type="int" regnum="27"/>
+                            <reg name="x28" bitsize="64" type="int" regnum="28"/>
+                            <reg name="x29" bitsize="64" type="int" regnum="29"/>
+                            <reg name="x30" bitsize="64" type="int" regnum="30"/>
+                            <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/>
+                            <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/>
+                            <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/>
+                            <reg name="w0" bitsize="32" type="int" regnum="34" value_regnums="0"/>
+                          </feature>
+                        </target>""", False
+                else:
+                    return None, False
+
+            def readRegister(self, regnum):
+                return ""
+
+            def readRegisters(self):
+                return self.reg_data
+
+            def haltReason(self):
+                return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;"
+
+        self.server.responder = MyResponder()
+
+        target = self.createTarget("basic_eh_frame-aarch64.yaml")
+        process = self.connect(target)
+        lldbutil.expect_state_changes(self, self.dbg.GetListener(), process,
+                                      [lldb.eStateStopped])
+
+        self.match("register read x0",
+                   ["x0 = 0x0807060504030201"])
+        # w0 comes from target.xml
+        self.match("register read w0",
+                   ["w0 = 0x04030201"])
+        self.match("register read x1",
+                   ["x1 = 0x1817161514131211"])
+        # w1 should not be added
+        self.match("register read w1",
+                   ["error: Invalid register name 'w1'."],
+                   error=True)