[SystemZ][z/OS] Initial implementation for lowerCall on z/OS

[anirudhp]

Summary

• This patch provides the initial implementation for lowering a call on z/OS according to the XPLINK64 calling convention
• A series of changes have been made to SystemZCallingConv.td to account for these additional XPLINK64 changes including adding a new helper function to shadow the stack along with allocation of a register wherever appropriate
• For the cases of copying a f64 to a gr64 and a f128 / 128-bit vector type to a gr64, a CCBitConvertToType has been added and has been bitcasted appropriately in the lowering phase
• Support for the ADA register (R5) will be provided in a later patch.

[uweigand]

LGTM, thanks!

[anirudhp]

• Rebase on latest main

llvm/lib/Target/SystemZ/SystemZCallingConv.h

namespace SystemZ {
   const unsigned ELFNumArgFPRs = 4;
   extern const MCPhysReg ELFArgFPRs[ELFNumArgFPRs];
 
   const unsigned XPLINK64NumArgGPRs = 3;
   extern const MCPhysReg XPLINK64ArgGPRs[XPLINK64NumArgGPRs];
 
   const unsigned XPLINK64NumArgFPRs = 4;
   extern const MCPhysReg XPLINK64ArgFPRs[XPLINK64NumArgFPRs];
+
+  const unsigned XPLINK64NumArgVRs = 8;
+  extern const MCPhysReg XPLINK64ArgVRs[XPLINK64NumArgVRs];
 } // end namespace SystemZ
 
 class SystemZCCState : public CCState {
 private:
   /// Records whether the value was a fixed argument.
   /// See ISD::OutputArg::IsFixed.
   SmallVector<bool, 4> ArgIsFixed;
 
const SystemZSubtarget &Subtarget =
       State.getMachineFunction().getSubtarget<SystemZSubtarget>();
   if (Subtarget.isTargetELF())
     Reg = State.AllocateReg(SystemZ::ELFArgGPRs);
   else if (Subtarget.isTargetXPLINK64())
     Reg = State.AllocateReg(SystemZ::XPLINK64ArgGPRs);
   else
     llvm_unreachable("Unknown Calling Convention!");
 
-  unsigned Offset = Reg ? 0 : State.AllocateStack(8, Align(8));
+  unsigned Offset = Reg && !Subtarget.isTargetXPLINK64()
+                        ? 0
+                        : State.AllocateStack(8, Align(8));
 
   // Use that same location for all the pending parts.
   for (auto &It : PendingMembers) {
     if (Reg)
       It.convertToReg(Reg);
     else
       It.convertToMem(Offset);
     State.addLoc(It);
inline bool CC_XPLINK64_Shadow_Reg(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
   return false;
 }
 
 inline bool CC_XPLINK64_Allocate128BitVararg(unsigned &ValNo, MVT &ValVT,
                                              MVT &LocVT,
                                              CCValAssign::LocInfo &LocInfo,
                                              ISD::ArgFlagsTy &ArgFlags,
                                              CCState &State) {
-  if (LocVT.getSizeInBits() < 128)
-    return false;
-
-  if (static_cast<SystemZCCState *>(&State)->IsFixed(ValNo))
-    return false;
-
   // For any C or C++ program, this should always be
   // false, since it is illegal to have a function
   // where the first argument is variadic. Therefore
   // the first fixed argument should already have
   // allocated GPR1 either through shadowing it or
   // using it for parameter passing.
   State.AllocateReg(SystemZ::R1D);
 
   bool AllocGPR2 = State.AllocateReg(SystemZ::R2D);
   bool AllocGPR3 = State.AllocateReg(SystemZ::R3D);
 
   // If GPR2 and GPR3 are available, then we may pass vararg in R2Q.
-  if (AllocGPR2 && AllocGPR3) {
+  // If only GPR3 is available, we need to set custom handling to copy
+  // hi bits into GPR3.
+  // Either way, we allocate on the stack.
+  if (AllocGPR3) {
+    // For f128 and vector var arg case, set the bitcast flag to bitcast to
+    // i128.
+    LocVT = MVT::i128;
+    LocInfo = CCValAssign::BCvt;
+    auto Offset = State.AllocateStack(16, Align(8));
+    if (AllocGPR2)
       State.addLoc(
           CCValAssign::getReg(ValNo, ValVT, SystemZ::R2Q, LocVT, LocInfo));
-    return true;
-  }
-
-  // If only GPR3 is available, we allocate on stack but need to
-  // set custom handling to copy hi bits into GPR3.
-  if (!AllocGPR2 && AllocGPR3) {
-    auto Offset = State.AllocateStack(16, Align(8));
+    else
       State.addLoc(
           CCValAssign::getCustomMem(ValNo, ValVT, Offset, LocVT, LocInfo));
     return true;
   }
 
   return false;
 }
 
+inline bool CC_XPLINK64_Shadow_Stack(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
+                                     CCValAssign::LocInfo &LocInfo,
+                                     ISD::ArgFlagsTy &ArgFlags,
+                                     CCState &State) {
+  ArrayRef<MCPhysReg> RegList;
+
+  switch (LocVT.SimpleTy) {
+  case MVT::i64:
+    RegList = SystemZ::XPLINK64ArgGPRs;
+    break;
+  case MVT::v16i8:
+  case MVT::v8i16:
+  case MVT::v4i32:
+  case MVT::v2i64:
+  case MVT::v4f32:
+  case MVT::v2f64:
+    RegList = SystemZ::XPLINK64ArgVRs;
+    break;
+  case MVT::f32:
+  case MVT::f64:
+  case MVT::f128:
+    RegList = SystemZ::XPLINK64ArgFPRs;
+    break;
+  default:
+    return false;
+  }
+
+  unsigned UnallocatedRegisterIndex = State.getFirstUnallocated(RegList);
+  // Every time we can allocate a register, allocate on the stack.
+  if (UnallocatedRegisterIndex < RegList.size())
+    State.AllocateStack(LocVT.getSizeInBits() / 8, Align(8));
+
+  return false;
+}
+
 inline bool RetCC_SystemZ_Error(unsigned &, MVT &, MVT &,
                                 CCValAssign::LocInfo &, ISD::ArgFlagsTy &,
                                 CCState &) {
   llvm_unreachable("Return value calling convention currently unsupported.");
 }
 
 inline bool CC_SystemZ_Error(unsigned &, MVT &, MVT &, CCValAssign::LocInfo &,
                              ISD::ArgFlagsTy &, CCState &) {

llvm/lib/Target/SystemZ/SystemZCallingConv.cpp

 const MCPhysReg SystemZ::XPLINK64ArgGPRs[SystemZ::XPLINK64NumArgGPRs] = {
     SystemZ::R1D, SystemZ::R2D, SystemZ::R3D
 };
 
 // The XPLINK64 ABI-defined param passing floating point registers
 const MCPhysReg SystemZ::XPLINK64ArgFPRs[SystemZ::XPLINK64NumArgFPRs] = {
     SystemZ::F0D, SystemZ::F2D, SystemZ::F4D, SystemZ::F6D
 };
+
+const MCPhysReg SystemZ::XPLINK64ArgVRs[SystemZ::XPLINK64NumArgVRs] = {
+    SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27,
+    SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31};

llvm/lib/Target/SystemZ/SystemZCallingConv.td

 // The XPLINK64 Calling Convention is fully specified in Chapter 22 of the z/OS
 // Language Environment Vendor Interfaces. Appendix B of the same document contains
 // examples.
 
 def CC_SystemZ_XPLINK64 : CallingConv<[
   // XPLINK64 ABI compliant code widens integral types smaller than i64
   // to i64 before placing the parameters either on the stack or in registers.
   CCIfType<[i32], CCIfExtend<CCPromoteToType<i64>>>,
+  // Promote f32 to f64 and bitcast to i64, if it needs to be passed in GPRS.
+  CCIfType<[f32], CCIfNotFixed<CCPromoteToType<f64>>>,
+  CCIfType<[f64], CCIfNotFixed<CCBitConvertToType<i64>>>,
+  // long double, can only be passed in GPR2 and GPR3, if available,
+  // hence R2Q
+  CCIfType<[f128], CCIfNotFixed<CCCustom<"CC_XPLINK64_Allocate128BitVararg">>>,
+  // Non fixed vector arguments are treated in the same way as long
+  // doubles.
+  CCIfSubtarget<"hasVector()",
+    CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
+      CCIfNotFixed<CCCustom<"CC_XPLINK64_Allocate128BitVararg">>>>,
 
   // A SwiftSelf is passed in callee-saved R10.
   CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R10D]>>>,
 
   // A SwiftError is passed in R0.
   CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R0D]>>>,
 
   // First i128 values. These are already split into two i64 here,
   // so we have to use a custom handler and assign into registers, if possible
   // We need to deal with this first
   CCIfType<[i64], CCCustom<"CC_SystemZ_I128Indirect">>,
   // The first 3 integer arguments are passed in registers R1D-R3D.
   // The rest will be passed in the user area. The address offset of the user
   // area can be found in register R4D.
-  CCIfType<[i32], CCAssignToReg<[R1L, R2L, R3L]>>,
+  CCIfType<[i64], CCCustom<"CC_XPLINK64_Shadow_Stack">>,
   CCIfType<[i64], CCAssignToReg<[R1D, R2D, R3D]>>,
 
   // The first 8 named vector arguments are passed in V24-V31.  Sub-128 vectors
   // are passed in the same way, but they're widened to one of these types
   // during type legalization.
   CCIfSubtarget<"hasVector()",
     CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
              CCIfFixed<CCCustom<"CC_XPLINK64_Shadow_Reg">>>>,
   CCIfSubtarget<"hasVector()",
     CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
+             CCIfFixed<CCCustom<"CC_XPLINK64_Shadow_Stack">>>>,
+  CCIfSubtarget<"hasVector()",
+    CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
              CCIfFixed<CCAssignToReg<[V24, V25, V26, V27,
                                       V28, V29, V30, V31]>>>>,
 
   // The first 4 named  float and double arguments are passed in registers FPR0-FPR6.
   // The rest will be passed in the user area.
   CCIfType<[f32, f64], CCIfFixed<CCCustom<"CC_XPLINK64_Shadow_Reg">>>,
+  CCIfType<[f32, f64], CCIfFixed<CCCustom<"CC_XPLINK64_Shadow_Stack">>>,
   CCIfType<[f32], CCIfFixed<CCAssignToReg<[F0S, F2S, F4S, F6S]>>>,
   CCIfType<[f64], CCIfFixed<CCAssignToReg<[F0D, F2D, F4D, F6D]>>>,
   // The first 2 long double arguments are passed in register FPR0/FPR2
   // and FPR4/FPR6. The rest will be passed in the user area.
   CCIfType<[f128], CCIfFixed<CCCustom<"CC_XPLINK64_Shadow_Reg">>>,
+  CCIfType<[f128], CCIfFixed<CCCustom<"CC_XPLINK64_Shadow_Stack">>>,
   CCIfType<[f128], CCIfFixed<CCAssignToReg<[F0Q, F4Q]>>>,
 
-  // Non fixed floats are passed in GPRs
-  // Promote f32 to f64, if it needs to be passed in GPRs.
-  CCIfType<[f32], CCIfNotFixed<CCPromoteToType<f64>>>,
-  // Assign f64 varargs to their proper GPRs.
-  CCIfType<[f64], CCIfNotFixed<CCAssignToReg<[R1D, R2D, R3D]>>>,
-  // long double, can only be passed in GPR2 and GPR3, if available,
-  // hence R2Q
-  CCIfType<[f128], CCIfNotFixed<CCCustom<"CC_XPLINK64_Allocate128BitVararg">>>,
-
-  // Non fixed vector arguments are treated in the same way as long
-  // doubles.
-  CCIfSubtarget<"hasVector()",
-    CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
-      CCIfNotFixed<CCCustom<"CC_XPLINK64_Allocate128BitVararg">>>>,
-
   // Other arguments are passed in 8-byte-aligned 8-byte stack slots.
   CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
   // Other f128 arguments are passed in 8-byte-aligned 16-byte stack slots.
   CCIfType<[f128], CCAssignToStack<16, 8>>,
   // Vector arguments are passed in 8-byte-alinged 16-byte stack slots too.
   CCIfSubtarget<"hasVector()",
     CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
              CCAssignToStack<16, 8>>>

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

static SDValue convertValVTToLocVT(SelectionDAG &DAG, const SDLoc &DL,
                                    CCValAssign &VA, SDValue Value) {
   switch (VA.getLocInfo()) {
   case CCValAssign::SExt:
     return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
   case CCValAssign::ZExt:
     return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
   case CCValAssign::AExt:
     return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
-  case CCValAssign::BCvt:
-    // If this is a short vector argument to be stored to the stack,
+  case CCValAssign::BCvt: {
+    assert(VA.getLocVT() == MVT::i64 || VA.getLocVT() == MVT::i128);
+    assert(VA.getValVT().isVector() || VA.getValVT() == MVT::f64 ||
+           VA.getValVT() == MVT::f128);
+    MVT BitCastToType = VA.getValVT().isVector() && VA.getLocVT() == MVT::i64
+                            ? MVT::v2i64
+                            : VA.getLocVT();
+    Value = DAG.getNode(ISD::BITCAST, DL, BitCastToType, Value);
+    // For ELF, this is a short vector argument to be stored to the stack,
     // bitcast to v2i64 and then extract first element.
-    assert(VA.getLocVT() == MVT::i64);
-    assert(VA.getValVT().isVector());
-    Value = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Value);
+    if (BitCastToType == MVT::v2i64)
       return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value,
                          DAG.getConstant(0, DL, MVT::i32));
+    return Value;
+  }
   case CCValAssign::Full:
     return Value;
   default:
     llvm_unreachable("Unhandled getLocInfo()");
   }
 }
 
 static SDValue lowerI128ToGR128(SelectionDAG &DAG, SDValue In) {
if (VA.isRegLoc()) {
       case MVT::f32:
         NumFixedFPRs += 1;
         RC = &SystemZ::FP32BitRegClass;
         break;
       case MVT::f64:
         NumFixedFPRs += 1;
         RC = &SystemZ::FP64BitRegClass;
         break;
+      case MVT::f128:
+        NumFixedFPRs += 2;
+        RC = &SystemZ::FP128BitRegClass;
+        break;
       case MVT::v16i8:
       case MVT::v8i16:
       case MVT::v4i32:
       case MVT::v2i64:
       case MVT::v4f32:
       case MVT::v2f64:
         RC = &SystemZ::VR128BitRegClass;
         break;
if (VA.getLocInfo() == CCValAssign::Indirect) {
         InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address,
                                      MachinePointerInfo()));
         ++I;
       }
     } else
       InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
   }
 
-  if (IsVarArg) {
+  // FIXME: Add support for lowering varargs for XPLINK64 in a later patch.
+  if (IsVarArg && Subtarget.isTargetELF()) {
     // Save the number of non-varargs registers for later use by va_start, etc.
     FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
     FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
 
     // Likewise the address (in the form of a frame index) of where the
     // first stack vararg would be.  The 1-byte size here is arbitrary.
     int64_t StackSize = CCInfo.getNextStackOffset();
     FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
if (NumFixedFPRs < SystemZ::ELFNumArgFPRs && !useSoftFloat()) {
       }
       // Join the stores, which are independent of one another.
       Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
                           makeArrayRef(&MemOps[NumFixedFPRs],
                                        SystemZ::ELFNumArgFPRs-NumFixedFPRs));
     }
   }
 
+  // FIXME: For XPLINK64, Add in support for handling incoming "ADA" special
+  // register (R5)
   return Chain;
 }
 
 static bool canUseSiblingCall(const CCState &ArgCCInfo,
                               SmallVectorImpl<CCValAssign> &ArgLocs,
                               SmallVectorImpl<ISD::OutputArg> &Outs) {
   // Punt if there are any indirect or stack arguments, or if the call
   // needs the callee-saved argument register R6, or if the call uses
SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
   SDValue Chain = CLI.Chain;
   SDValue Callee = CLI.Callee;
   bool &IsTailCall = CLI.IsTailCall;
   CallingConv::ID CallConv = CLI.CallConv;
   bool IsVarArg = CLI.IsVarArg;
   MachineFunction &MF = DAG.getMachineFunction();
   EVT PtrVT = getPointerTy(MF.getDataLayout());
   LLVMContext &Ctx = *DAG.getContext();
+  SystemZCallingConventionRegisters *Regs = Subtarget.getSpecialRegisters();
+
+  // FIXME: z/OS support to be added in later.
+  if (Subtarget.isTargetXPLINK64())
+    IsTailCall = false;
 
   // Detect unsupported vector argument and return types.
   if (Subtarget.hasVector()) {
     VerifyVectorTypes(Outs);
     VerifyVectorTypes(Ins);
   }
 
   // Analyze the operands of the call, assigning locations to each operand.
   SmallVector<CCValAssign, 16> ArgLocs;
   SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, Ctx);
   ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
 
   // We don't support GuaranteedTailCallOpt, only automatically-detected
   // sibling calls.
   if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs, Outs))
     IsTailCall = false;
 
   // Get a count of how many bytes are to be pushed on the stack.
   unsigned NumBytes = ArgCCInfo.getNextStackOffset();
 
+  if (Subtarget.isTargetXPLINK64())
+    // Although the XPLINK specifications for AMODE64 state that minimum size
+    // of the param area is minimum 32 bytes and no rounding is otherwise
+    // specified, we round this area in 64 bytes increments to be compatible
+    // with existing compilers.
+    NumBytes = std::max(64U, (unsigned)alignTo(NumBytes, 64));
+
   // Mark the start of the call.
   if (!IsTailCall)
     Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
 
   // Copy argument values to their designated locations.
   SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
   SmallVector<SDValue, 8> MemOpChains;
   SDValue StackPtr;
if (VA.getLocInfo() == CCValAssign::Indirect) {
         assert((PartOffset + PartValue.getValueType().getStoreSize() <=
                 SlotVT.getStoreSize()) && "Not enough space for argument part!");
         ++I;
       }
       ArgValue = SpillSlot;
     } else
       ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
 
-    if (VA.isRegLoc())
+    if (VA.isRegLoc()) {
+      // In XPLINK64, for the 128-bit vararg case, ArgValue is bitcasted to a
+      // MVT::i128 type. We decompose the 128-bit type to a pair of its high
+      // and low values.
+      if (VA.getLocVT() == MVT::i128)
+        ArgValue = lowerI128ToGR128(DAG, ArgValue);
       // Queue up the argument copies and emit them at the end.
       RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
-    else {
+    } else {
       assert(VA.isMemLoc() && "Argument not register or memory");
 
       // Work out the address of the stack slot.  Unpromoted ints and
       // floats are passed as right-justified 8-byte values.
       if (!StackPtr.getNode())
-        StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
-      unsigned Offset = SystemZMC::ELFCallFrameSize + VA.getLocMemOffset();
+        StackPtr = DAG.getCopyFromReg(Chain, DL,
+                                      Regs->getStackPointerRegister(), PtrVT);
+      unsigned Offset = Regs->getStackPointerBias() + Regs->getCallFrameSize() +
+                        VA.getLocMemOffset();
       if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
         Offset += 4;
       SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
                                     DAG.getIntPtrConstant(Offset, DL));
 
       // Emit the store.
       MemOpChains.push_back(
           DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo()));
+
+      // Although long doubles or vectors are passed through the stack when
+      // they are vararg (non-fixed arguments), if a long double or vector
+      // occupies the third and fourth slot of the argument list GPR3 should
+      // still shadow the third slot of the argument list.
+      if (Subtarget.isTargetXPLINK64() && VA.needsCustom()) {
+        SDValue ShadowArgValue =
+            DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64, ArgValue,
+                        DAG.getIntPtrConstant(1, DL));
+        RegsToPass.push_back(std::make_pair(SystemZ::R3D, ShadowArgValue));
+      }
     }
   }
 
   // Join the stores, which are independent of one another.
   if (!MemOpChains.empty())
     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
 
   // Accept direct calls by converting symbolic call addresses to the
   // associated Target* opcodes.  Force %r1 to be used for indirect
   // tail calls.
   SDValue Glue;
+  // FIXME: Add support for XPLINK using the ADA register.
   if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
     Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
   } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
     Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
   } else if (IsTailCall) {
     Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);

llvm/lib/Target/SystemZ/SystemZRegisterInfo.h

public:
   /// \returns an array of all the callee saved registers.
   virtual const MCPhysReg *
   getCalleeSavedRegs(const MachineFunction *MF) const = 0;
 
   /// \returns the mask of all the call preserved registers.
   virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                                CallingConv::ID CC) const = 0;
 
+  /// \returns the offset to the locals area.
+  virtual int getCallFrameSize() = 0;
+
+  /// \returns the stack pointer bias.
+  virtual int getStackPointerBias() = 0;
+
   /// Destroys the object. Bogus destructor allowing derived classes
   /// to override it.
   virtual ~SystemZCallingConventionRegisters(){};
 };
 
 /// XPLINK64 calling convention specific use registers
 /// Particular to z/OS when in 64 bit mode
 class SystemZXPLINK64Registers : public SystemZCallingConventionRegisters {
public:
   int getAddressOfCalleeRegister() { return SystemZ::R6D; };
 
   const MCPhysReg *
   getCalleeSavedRegs(const MachineFunction *MF) const override final;
 
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID CC) const override final;
 
+  int getCallFrameSize() override final { return 128; }
+
+  int getStackPointerBias() override final { return 2048; }
+
   /// Destroys the object. Bogus destructor overriding base class destructor
   ~SystemZXPLINK64Registers(){};
 };
 
 /// ELF calling convention specific use registers
 /// Particular when on zLinux in 64 bit mode
 class SystemZELFRegisters : public SystemZCallingConventionRegisters {
 public:
   int getReturnFunctionAddressRegister() override final {
     return SystemZ::R14D;
   };
 
   int getStackPointerRegister() override final { return SystemZ::R15D; };
 
   int getFramePointerRegister() override final { return SystemZ::R11D; };
 
   const MCPhysReg *
   getCalleeSavedRegs(const MachineFunction *MF) const override final;
 
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID CC) const override final;
 
+  int getCallFrameSize() override final { return SystemZMC::ELFCallFrameSize; }
+
+  int getStackPointerBias() override final { return 0; }
+
   /// Destroys the object. Bogus destructor overriding base class destructor
   ~SystemZELFRegisters(){};
 };
 
 struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
 public:
   SystemZRegisterInfo(unsigned int RA);
 

llvm/lib/Target/TargetMachine.cpp

if (TT.isOSBinFormatCOFF()) {
     // the current DSO.
     if (GV->hasExternalWeakLinkage())
       return false;
 
     // Every other GV is local on COFF.
     return true;
   }
 
+  if (TT.isOSBinFormatGOFF())
+    return true;
+
   if (TT.isOSBinFormatMachO()) {
     if (RM == Reloc::Static)
       return true;
     return GV->isStrongDefinitionForLinker();
   }
 
   assert(TT.isOSBinFormatELF() || TT.isOSBinFormatWasm() ||
          TT.isOSBinFormatXCOFF());

llvm/test/CodeGen/SystemZ/call-zos-01.ll

+; Test the passing of scalar values in GPRs, FPRs in 64-bit calls on z/OS.
+;
+; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z10 | FileCheck %s
+
+; CHECK-LABEL: call_char:
+; CHECK: lghi  1, 8
+define i8 @call_char(){
+  %retval = call i8 (i8) @pass_char(i8 8)
+  ret i8 %retval
+}
+
+; CHECK-LABEL: call_short:
+; CHECK: lghi  1, 16
+define i16 @call_short() {
+entry:
+  %retval = call i16 (i16) @pass_short(i16 16)
+  ret i16 %retval
+}
+
+; CHECK-LABEL: call_int:
+; CHECK: lghi  1, 32
+; CHECK: lghi  2, 33
+define i32 @call_int() {
+entry:
+  %retval = call i32 (i32, i32) @pass_int(i32 32, i32 33)
+  ret i32 %retval
+}
+
+; CHECK-LABEL: call_long:
+; CHECK: lghi  1, 64
+; CHECK: lghi  2, 65
+; CHECK: lghi  3, 66
+define i64 @call_long() {
+entry:
+  %retval = call i64 (i64, i64, i64) @pass_long(i64 64, i64 65, i64 66)
+  ret i64 %retval
+}
+
+; CHECK-LABEL: call_ptr:
+; CHECK: lgr 1, 2
+define i32 @call_ptr(i32* %p1, i32* %p2) {
+entry:
+  %retval = call i32 (i32*) @pass_ptr(i32* %p2)
+  ret i32 %retval
+}
+
+; CHECK-LABEL: call_integrals:
+; CHECK: lghi  1, 64
+; CHECK: lghi  2, 32
+; CHECK: lghi  3, 16
+define i64 @call_integrals() {
+entry:
+  %retval = call i64 (i64, i32, i16, i64) @pass_integrals0(i64 64, i32 32, i16 16, i64 128)
+  ret i64 %retval
+}
+
+; CHECK-LABEL: pass_char:
+; CHECK: lgr 3, 1
+define signext i8 @pass_char(i8 signext %arg) {
+entry:
+  ret i8 %arg
+}
+
+; CHECK-LABEL: pass_short:
+; CHECK: lgr 3, 1
+define signext i16 @pass_short(i16 signext %arg) {
+entry:
+  ret i16 %arg
+}
+
+; CHECK-LABEL: pass_int:
+; CHECK: lgr 3, 2
+define signext i32 @pass_int(i32 signext %arg0, i32 signext %arg1) {
+entry:
+  ret i32 %arg1
+}
+
+; CHECK-LABEL: pass_long:
+; CHECK: agr 1, 2
+; CHECK: agr 3, 1
+define signext i64 @pass_long(i64 signext %arg0, i64 signext %arg1, i64 signext %arg2) {
+entry:
+  %N = add i64 %arg0, %arg1
+  %M = add i64 %N, %arg2
+  ret i64 %M
+}
+
+; CHECK-LABEL: pass_integrals0:
+; CHECK: ag  2, -{{[0-9]+}}(4)
+; CHECK-NEXT: lgr 3, 2
+define signext i64 @pass_integrals0(i64 signext %arg0, i32 signext %arg1, i16 signext %arg2, i64 signext %arg3) {
+entry:
+  %N = sext i32 %arg1 to i64
+  %M = add i64 %arg3, %N
+  ret i64 %M
+}
+
+; CHECK-LABEL: call_float:
+; CHECK: le 0, 0({{[0-9]}})
+define float @call_float() {
+entry:
+  %ret = call float (float) @pass_float(float 0x400921FB60000000)
+  ret float %ret
+}
+
+; CHECK-LABEL: call_double:
+; CHECK: larl  [[GENREG:[0-9]+]], @{{CPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: ld  0, 0([[GENREG]])
+define double @call_double() {
+entry:
+  %ret = call double (double) @pass_double(double 3.141000e+00)
+  ret double %ret
+}
+
+; CHECK-LABEL: call_longdouble:
+; CHECK: larl  [[GENREG:[0-9]+]], @{{CPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: ld  0, 0([[GENREG]])
+; CHECK-NEXT: ld  2, 8([[GENREG]])
+define fp128 @call_longdouble() {
+entry:
+  %ret = call fp128 (fp128) @pass_longdouble(fp128 0xLE0FC1518450562CD4000921FB5444261)
+  ret fp128 %ret
+}
+
+; CHECK-LABEL: call_floats0
+; CHECK: larl  [[GENREG:[0-9]+]], @{{CPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: ld  1, 0([[GENREG]])
+; CHECK-NEXT: ld  3, 8([[GENREG]])
+; CHECK: lxr 5, 0
+; CHECK: lxr 0, 1
+; CHECK: lxr 4, 5
+define i64 @call_floats0(fp128 %arg0, double %arg1) {
+entry:
+  %ret = call i64 (fp128, fp128, double) @pass_floats0(fp128 0xLE0FC1518450562CD4000921FB5444261, fp128 %arg0, double %arg1)
+  ret i64 %ret
+}
+
+; CHECK-LABEL: call_floats1
+; CHECK: lxr 1, 0
+; CHECK: ldr 0, 4
+; CHECK: lxr 4, 1
+define i64 @call_floats1(fp128 %arg0, double %arg1) {
+entry:
+  %ret = call i64 (double, fp128) @pass_floats1(double %arg1, fp128 %arg0)
+  ret i64 %ret
+}
+
+; CHECK-LABEL: pass_float:
+; CHECK: larl  1, @{{CPI[0-9]+_[0-9]+}}
+; CHECK: aeb 0, 0(1)
+define float @pass_float(float %arg) {
+entry:
+  %X = fadd float %arg, 0x400821FB60000000
+  ret float %X
+}
+
+; CHECK-LABEL: pass_double:
+; CHECK: larl  1, @{{CPI[0-9]+_[0-9]+}}
+; CHECK: adb 0, 0(1)
+define double @pass_double(double %arg) {
+entry:
+  %X = fadd double %arg, 1.414213e+00
+  ret double %X
+}
+
+; CHECK-LABEL: pass_longdouble
+; CHECK: larl  1, @{{CPI[0-9]+_[0-9]+}}
+; CHECK: lxdb  1, 0(1)
+; CHECK: axbr  0, 1
+define fp128 @pass_longdouble(fp128 %arg) {
+entry:
+  %X = fadd fp128 %arg, 0xL10000000000000004000921FB53C8D4F
+  ret fp128 %X
+}
+
+; CHECK-LABEL: pass_floats0
+; CHECK: larl  1, @{{CPI[0-9]+_[0-9]+}}
+; CHECK: axbr  0, 4
+; CHECK: axbr  1, 0
+; CHECK: cxbr  1, 5
+define i64 @pass_floats0(fp128 %arg0, fp128 %arg1, double %arg2) {
+  %X = fadd fp128 %arg0, %arg1
+  %arg2_ext = fpext double %arg2 to fp128
+  %Y = fadd fp128 %X, %arg2_ext
+  %ret_bool = fcmp ueq fp128 %Y, 0xLE0FC1518450562CD4000921FB5444261
+  %ret = sext i1 %ret_bool to i64
+  ret i64 %ret
+}
+
+declare i64 @pass_floats1(double %arg0, fp128 %arg1)
+declare i32 @pass_ptr(i32* %arg)

llvm/test/CodeGen/SystemZ/call-zos-vararg.ll

+; Test passing variable argument lists in 64-bit calls on z/OS.
+; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z14 | FileCheck %s -check-prefix=ARCH12
+; CHECK-LABEL: call_vararg_double0
+; CHECK:       llihf 3, 1074118262
+; CHECK-NEXT:  oilf  3, 3367254360
+; CHECK:       lghi  1, 1
+; CHECK:       lghi  2, 2
+define i64 @call_vararg_double0() {
+entry:
+  %retval = call i64 (i64, i64, ...) @pass_vararg0(i64 1, i64 2, double 2.718000e+00)
+  ret i64 %retval
+}
+
+; CHECK-LABEL:  call_vararg_double1
+; CHECK:        llihf 0, 1074118262
+; CHECK-NEXT:   oilf  0, 3367254360
+; CHECK:        llihf 3, 1074340036
+; CHECK-NEXT:   oilf  3, 2611340116
+; CHECK:        lghi  1, 1
+; CHECK:        lghi  2, 2
+; CHECK:        stg 0, 2200(4)
+define i64 @call_vararg_double1() {
+entry:
+  %retval = call i64 (i64, i64, ...) @pass_vararg0(i64 1, i64 2, double 3.141000e+00, double 2.718000e+00)
+  ret i64 %retval
+}
+
+; CHECK-LABEL: call_vararg_double2
+; CHECK-NOT:   llihf 0
+; CHECK-NOT:   oilf 0
+; CHECK:       llihf 2, 1074118262
+; CHECK-NEXT:  oilf  2, 3367254360
+; CHECK:       lghi  1, 8200
+define i64 @call_vararg_double2() {
+entry:
+  %retval = call i64 (i64, ...) @pass_vararg2(i64 8200, double 2.718000e+00)
+  ret i64 %retval
+}
+
+; CHECK-LABEL: call_vararg_double3
+; CHECK:       llihf   0, 1072703839
+; CHECK-NEXT:  oilf    0, 2861204133
+; CHECK:       llihf   1, 1074118262
+; CHECK-NEXT:  oilf    1, 3367254360
+; CHECK:       llihf   2, 1074340036
+; CHECK-NEXT:  oilf    2, 2611340116
+; CHECK:       llihf   3, 1073127358
+; CHECK-NEXT:  oilf    3, 1992864825
+; CHECK:       stg     0, 2200(4)
+define i64 @call_vararg_double3() {
+entry:
+  %retval = call i64 (...) @pass_vararg3(double 2.718000e+00, double 3.141000e+00, double 1.414000e+00, double 1.010101e+00)
+  ret i64 %retval
+}
+
+; CHECK-LABEL: call_vararg_both0
+; CHECK:       lgr   2, 1
+; CHECK:       lgdr  1, 0
+define i64 @call_vararg_both0(i64 %arg0, double %arg1) {
+  %retval  = call i64(...) @pass_vararg3(double %arg1, i64 %arg0)
+  ret i64 %retval
+}
+
+; CHECK-LABEL: call_vararg_long_double0
+; CHECK:       larl  1, @CPI5_0
+; CHECK-NEXT:  ld    0, 0(1)
+; CHECK-NEXT:  ld    2, 8(1)
+; CHECK-NEXT:  lgdr  3, 0
+; CHECK:       lghi  1, 1
+; CHECK:       lghi  2, 2
+; CHECK:       std   0, 2192(4)
+; CHECK-NEXT:  std   2, 2200(4)
+define i64 @call_vararg_long_double0() {
+entry:
+  %retval = call i64 (i64, i64, ...) @pass_vararg0(i64 1, i64 2, fp128 0xLE0FC1518450562CD4000921FB5444261)
+  ret i64 %retval
+}
+
+; CHECK-LABEL: call_vararg_long_double1
+; CHECK:       lgdr  3, 0
+; CHECK:       lghi  1, 1
+; CHECK:       lghi  2, 2
+; CHECK:       std   0, 2192(4)
+; CHECK-NEXT:  std   2, 2200(4)
+define i64 @call_vararg_long_double1(fp128 %arg0) {
+entry:
+  %retval = call i64 (i64, i64, ...) @pass_vararg0(i64 1, i64 2, fp128 %arg0)
+  ret i64 %retval
+}
+
+; CHECK-LABEL: call_vararg_long_double2
+; CHECK:      std   4, 2208(4)
+; CHECK-NEXT: std   6, 2216(4)
+; CHECK:      lgdr  3, 0
+; CHECK:      lghi  1, 1
+; CHECK:      lghi  2, 2
+; CHECK:      std   0, 2192(4)
+; CHECK-NEXT: std   2, 2200(4)
+define i64 @call_vararg_long_double2(fp128 %arg0, fp128 %arg1) {
+entry:
+  %retval = call i64 (i64, i64, ...) @pass_vararg0(i64 1, i64 2, fp128 %arg0, fp128 %arg1)
+  ret i64 %retval
+}
+
+; CHECK-LABEL: call_vararg_long_double3
+; CHECK:       lgdr 3, 2
+; CHECK-NEXT:  lgdr 2, 0
+define i64 @call_vararg_long_double3(fp128 %arg0) {
+entry:
+  %retval = call i64 (...) @pass_vararg3(fp128 %arg0)
+  ret i64 %retval
+}
+
+; ARCH12-LABEL: call_vec_vararg_test0
+; ARCH12: vlgvg 3, 24, 1
+; ARCH12: vlgvg 2, 24, 0
+; ARCH12: lghi  1, 1
+define void @call_vec_vararg_test0(<2 x double> %v) {
+  %retval = call i64(i64, ...) @pass_vararg2(i64 1, <2 x double> %v)
+  ret void
+}
+
+; ARCH12-LABEL: call_vec_vararg_test1
+; ARCH12: larl  1, @CPI10_0
+; ARCH12: vl    0, 0(1), 3
+; ARCH12: vlgvg 3, 24, 0
+; ARCH12: vrepg 2, 0, 1
+; ARCH12: vst   25, 2208(4), 3
+; ARCH12: vst   24, 2192(4), 3
+define void @call_vec_vararg_test1(<4 x i32> %v, <2 x i64> %w) {
+  %retval = call i64(fp128, ...) @pass_vararg1(fp128 0xLE0FC1518450562CD4000921FB5444261, <4 x i32> %v, <2 x i64> %w)
+  ret void
+}
+
+; ARCH12-LABEL: call_vec_char_vararg_straddle
+; ARCH12: vlgvg 3, 24, 0
+; ARCH12: lghi  1, 1
+; ARCH12: lghi  2, 2
+; ARCH12: vst   24, 2192(4), 3
+define void @call_vec_char_vararg_straddle(<16 x i8> %v) {
+  %retval = call i64(i64, i64, ...) @pass_vararg0(i64 1, i64 2, <16 x i8> %v)
+  ret void
+}
+
+; ARCH12-LABEL: call_vec_short_vararg_straddle
+; ARCH12: vlgvg 3, 24, 0
+; ARCH12: lghi  1, 1
+; ARCH12: lghi  2, 2
+; ARCH12: vst   24, 2192(4), 3
+define void @call_vec_short_vararg_straddle(<8 x i16> %v) {
+  %retval = call i64(i64, i64, ...) @pass_vararg0(i64 1, i64 2, <8 x i16> %v)
+  ret void
+}
+
+; ARCH12-LABEL: call_vec_int_vararg_straddle
+; ARCH12: vlgvg 3, 24, 0
+; ARCH12: lghi  1, 1
+; ARCH12: lghi  2, 2
+; ARCH12: vst 24, 2192(4), 3
+define void @call_vec_int_vararg_straddle(<4 x i32> %v) {
+  %retval = call i64(i64, i64, ...) @pass_vararg0(i64 1, i64 2, <4 x i32> %v)
+  ret void
+}
+
+; ARCH12-LABEL: call_vec_double_vararg_straddle
+; ARCH12: vlgvg 3, 24, 0
+; ARCH12: lghi  1, 1
+; ARCH12: lghi  2, 2
+; ARCH12: vst 24, 2192(4), 3
+define void @call_vec_double_vararg_straddle(<2 x double> %v) {
+  %retval = call i64(i64, i64, ...) @pass_vararg0(i64 1, i64 2, <2 x double> %v)
+  ret void
+}
+
+; CHECK-LABEL: call_vararg_integral0
+; Since arguments 0, 1, and 2 are already in the correct
+; registers, we should have no loads of any sort into
+; GPRs 1, 2, and 3.
+; CHECK-NOT: lg  1
+; CHECK-NOT: lgr  1
+; CHECK-NOT: lg  2
+; CHECK-NOT: lgr  2
+; CHECK-NOT: lg  3
+; CHECK-NOT: lgr  3
+define i64 @call_vararg_integral0(i32 signext %arg0, i16 signext %arg1, i64 signext %arg2, i8 signext %arg3) {
+entry:
+  %retval = call i64(...) @pass_vararg3(i32 signext %arg0, i16 signext %arg1, i64 signext %arg2, i8 signext %arg3)
+  ret i64 %retval
+}
+
+declare i64 @pass_vararg0(i64 %arg0, i64 %arg1, ...)
+declare i64 @pass_vararg1(fp128 %arg0, ...)
+declare i64 @pass_vararg2(i64 %arg0, ...)
+declare i64 @pass_vararg3(...)

llvm/test/CodeGen/SystemZ/call-zos-vec.ll

+; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z13 | FileCheck %s
+
+; CHECK-LABEL: sum_vecs0
+; CHECK: vag 24, 24, 25
+define <2 x i64> @sum_vecs0(<2 x i64> %v1, <2 x i64> %v2) {
+entry:
+  %add0 = add <2 x i64> %v1, %v2
+  ret <2 x i64> %add0
+}
+
+; CHECK-LABEL: sum_vecs1
+; CHECK: vaf 1, 24, 25
+; CHECK: vaf 1, 1, 26
+; CHECK: vaf 1, 1, 27
+; CHECK: vaf 1, 1, 28
+; CHECK: vaf 1, 1, 29
+; CHECK: vl  0, 32(4), 4
+; CHECK: vaf 1, 1, 30
+; CHECK: vaf 1, 1, 31
+; CHECK: vaf 24, 1, 0
+define <4 x i32> @sum_vecs1(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6, <4 x i32> %v7, <4 x i32> %v8, <4 x i32> %v9) {
+entry:
+  %add0 = add <4 x i32> %v1, %v2
+  %add1 = add <4 x i32> %add0, %v3
+  %add2 = add <4 x i32> %add1, %v4
+  %add3 = add <4 x i32> %add2, %v5
+  %add4 = add <4 x i32> %add3, %v6
+  %add5 = add <4 x i32> %add4, %v7
+  %add6 = add <4 x i32> %add5, %v8
+  %add7 = add <4 x i32> %add6, %v9
+  ret <4 x i32> %add7
+}
+
+; Verify that 3 is used for passing integral types if
+; only 24 is used.
+; CHECK-LABEL: call_vecs0
+; CHECK: lgr 3, 1
+define i64 @call_vecs0(i64 %n, <2 x i64> %v1) {
+entry:
+  %ret = call i64 (<2 x i64>, i64) @pass_vecs0(<2 x i64> %v1, i64 %n)
+  ret i64 %ret
+}
+
+; Verify that 3 is not allocated for passing integral types
+; if 24 and %f0 are used.
+; CHECK-LABEL: call_vecs1
+; CHECK: vlr 24, 25
+; CHECK: stg 1, 2200(4)
+define i64 @call_vecs1(i64 %n, <2 x i64> %v1, double %x, <2 x i64> %v2) {
+entry:
+  %ret = call i64 (<2 x i64>, double, i64) @pass_vecs1(<2 x i64> %v2, double %x, i64 %n)
+  ret i64 %ret
+}
+
+; Verify that 3 is not allocated for passing integral types
+; if 24 and 25 are used.
+; CHECK-LABEL: call_vecs2
+; CHECK: mvghi 2208(4), 55
+define i64 @call_vecs2(<2 x i64> %v1, <2 x i64> %v2) {
+  %ret = call i64 (<2 x i64>, <2 x i64>, i64) @pass_vecs2(<2 x i64> %v1, <2 x i64> %v2, i64 55)
+  ret i64 %ret
+}
+
+declare i64 @pass_vecs0(<2 x i64> %v1, i64 %n)
+declare i64 @pass_vecs1(<2 x i64> %v1, double %x, i64 %n)
+declare i64 @pass_vecs2(<2 x i64> %v1, <2 x i64> %v2, i64 %n)