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Differential D111549

[AMDGPU] Fix copying a machine operand
ClosedPublic

Authored by foad on Oct 11 2021, 7:15 AM.

Details

Reviewers
arsenm
rampitec
Commits
rG2e1ad93201e5: [AMDGPU] Fix copying a machine operand
Summary

Without this I get:

    • Bad machine code: Instruction has operand with wrong parent set ***
  • function: available_externally_test
  • basic block: %bb.0 (0x7dad598)
  • instruction: %0:r600_treg32_x = MOV 1, 0, 0, 0, $alu_literal_x, 0, 0, 0, -1, 1, $pred_sel_off, @available_externally, 0

Diff Detail

Event Timeline

foad created this revision.Oct 11 2021, 7:15 AM
Herald added subscribers: kerbowa, hiraditya, t-tye and 6 others. · View Herald TranscriptOct 11 2021, 7:15 AM
foad requested review of this revision.Oct 11 2021, 7:15 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 11 2021, 7:15 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Harbormaster completed remote builds in B128102: Diff 378657.Oct 11 2021, 8:05 AM
rampitec accepted this revision.Oct 11 2021, 11:35 AM
This revision is now accepted and ready to land.Oct 11 2021, 11:35 AM
Closed by commit rG2e1ad93201e5: [AMDGPU] Fix copying a machine operand (authored by foad). · Explain WhyOct 11 2021, 12:26 PM
This revision was automatically updated to reflect the committed changes.
foad added a commit: rG2e1ad93201e5: [AMDGPU] Fix copying a machine operand.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
4 lines
test/
CodeGen/
AMDGPU/
2 lines

Diff 378761

llvm/lib/Target/AMDGPU/R600ISelLowering.cpp

Show First 20 Lines • Show All 330 Lines • ▼ Show 20 Lines case R600::MOV_IMM_I32:
break; break;
case R600::MOV_IMM_GLOBAL_ADDR: { case R600::MOV_IMM_GLOBAL_ADDR: {
//TODO: Perhaps combine this instruction with the next if possible //TODO: Perhaps combine this instruction with the next if possible
auto MIB = TII->buildDefaultInstruction( auto MIB = TII->buildDefaultInstruction(
*BB, MI, R600::MOV, MI.getOperand(0).getReg(), R600::ALU_LITERAL_X); *BB, MI, R600::MOV, MI.getOperand(0).getReg(), R600::ALU_LITERAL_X);
int Idx = TII->getOperandIdx(*MIB, R600::OpName::literal); int Idx = TII->getOperandIdx(*MIB, R600::OpName::literal);
//TODO: Ugh this is rather ugly //TODO: Ugh this is rather ugly
MIB->getOperand(Idx) = MI.getOperand(1); const MachineOperand &MO = MI.getOperand(1);
MIB->getOperand(Idx).ChangeToGA(MO.getGlobal(), MO.getOffset(),
MO.getTargetFlags());
break; break;
} }
case R600::CONST_COPY: { case R600::CONST_COPY: {
MachineInstr *NewMI = TII->buildDefaultInstruction( MachineInstr *NewMI = TII->buildDefaultInstruction(
*BB, MI, R600::MOV, MI.getOperand(0).getReg(), R600::ALU_CONST); *BB, MI, R600::MOV, MI.getOperand(0).getReg(), R600::ALU_CONST);
TII->setImmOperand(*NewMI, R600::OpName::src0_sel, TII->setImmOperand(*NewMI, R600::OpName::src0_sel,
MI.getOperand(1).getImm()); MI.getOperand(1).getImm());
▲ Show 20 Lines • Show All 1,867 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/global-constant.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefix=R600 %s ; RUN: llc -mtriple=r600-- -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=R600 %s
@private1 = private unnamed_addr addrspace(4) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0] @private1 = private unnamed_addr addrspace(4) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0]
@private2 = private unnamed_addr addrspace(4) constant [4 x float] [float 4.0, float 5.0, float 6.0, float 7.0] @private2 = private unnamed_addr addrspace(4) constant [4 x float] [float 4.0, float 5.0, float 6.0, float 7.0]
@available_externally = available_externally addrspace(4) global [256 x i32] zeroinitializer @available_externally = available_externally addrspace(4) global [256 x i32] zeroinitializer
; GCN-LABEL: {{^}}private_test: ; GCN-LABEL: {{^}}private_test:
; GCN: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
Show All 37 Lines