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Differential D110567

[ARM] Delay reverting WLS in arm-block-placement
ClosedPublic

Authored by dmgreen on Sep 27 2021, 10:13 AM.

Details

Reviewers
SjoerdMeijer
samtebbs
momchil.velikov
lenary
simon_tatham
Commits
rGfdd8c1095954: [ARM] Delay reverting WLS in arm-block-placement
Summary

If we cannot fix up the block placement of WLS branches we revert WLS to DLS instructions. But in doing so can create new blocks, invalidating loop analyses and potentially running into invalid iterators. Prevent that by creating a list of all WLS instructions to revert and reverting them after processing all loops.

The test case it fairly large, but I have not managed to simplify it any further due to the issue coming up from invalid iterators.

Diff Detail

Event Timeline

dmgreen created this revision.Sep 27 2021, 10:13 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald TranscriptSep 27 2021, 10:13 AM
dmgreen requested review of this revision.Sep 27 2021, 10:13 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 27 2021, 10:13 AM
Harbormaster completed remote builds in B125919: Diff 375320.Sep 27 2021, 11:05 AM
SjoerdMeijer accepted this revision.Sep 28 2021, 3:39 AM

Looks like a good fix to me.

The test is indeed big, but I guess it is what it is if it's difficult to reduce.

llvm/lib/Target/ARM/ARMBlockPlacement.cpp
34

Nit: perhaps add a comment why we are adding/doing this bookkeeping (i.e. the description of this patch).

89

Unrelated nit: perhaps time to rename this to revertWhileToDoLoop while we are at it?

This revision is now accepted and ready to land.Sep 28 2021, 3:39 AM
This revision was landed with ongoing or failed builds.Sep 28 2021, 7:38 AM
Closed by commit rGfdd8c1095954: [ARM] Delay reverting WLS in arm-block-placement (authored by dmgreen). · Explain Why
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rGfdd8c1095954: [ARM] Delay reverting WLS in arm-block-placement.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
22 lines
test/
CodeGen/
Thumb2/
LowOverheadLoops/
1174 lines

Diff 375574

llvm/lib/Target/ARM/ARMBlockPlacement.cpp

Show All 25 Lines
#define DEBUG_PREFIX "ARM Block Placement: " #define DEBUG_PREFIX "ARM Block Placement: "
namespace llvm { namespace llvm {
class ARMBlockPlacement : public MachineFunctionPass { class ARMBlockPlacement : public MachineFunctionPass {
private: private:
const ARMBaseInstrInfo *TII; const ARMBaseInstrInfo *TII;
std::unique_ptr<ARMBasicBlockUtils> BBUtils = nullptr; std::unique_ptr<ARMBasicBlockUtils> BBUtils = nullptr;
MachineLoopInfo *MLI = nullptr; MachineLoopInfo *MLI = nullptr;
// A list of WLS instructions that need to be reverted to DLS.
SjoerdMeijerUnsubmitted
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Nit: perhaps add a comment why we are adding/doing this bookkeeping (i.e. the description of this patch).

SjoerdMeijer: Nit: perhaps add a comment why we are adding/doing this bookkeeping (i.e. the description of…
SmallVector<MachineInstr *> RevertedWhileLoops;
public: public:
static char ID; static char ID;
ARMBlockPlacement() : MachineFunctionPass(ID) {} ARMBlockPlacement() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
void moveBasicBlock(MachineBasicBlock *BB, MachineBasicBlock *Before); void moveBasicBlock(MachineBasicBlock *BB, MachineBasicBlock *Before);
bool blockIsBefore(MachineBasicBlock *BB, MachineBasicBlock *Other); bool blockIsBefore(MachineBasicBlock *BB, MachineBasicBlock *Other);
bool fixBackwardsWLS(MachineLoop *ML); bool fixBackwardsWLS(MachineLoop *ML);
bool processPostOrderLoops(MachineLoop *ML); bool processPostOrderLoops(MachineLoop *ML);
bool revertWhileToDo(MachineInstr *WLS, MachineLoop *ML); bool revertWhileToDoLoop(MachineInstr *WLS);
void getAnalysisUsage(AnalysisUsage &AU) const override { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineLoopInfo>(); AU.addRequired<MachineLoopInfo>();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
}; };
} // namespace llvm } // namespace llvm
Show All 26 Lines if (WlsInstr)
return WlsInstr; return WlsInstr;
if (Predecessor->pred_size() == 1) if (Predecessor->pred_size() == 1)
return findWLSInBlock(*Predecessor->pred_begin()); return findWLSInBlock(*Predecessor->pred_begin());
return nullptr; return nullptr;
} }
// Revert a WhileLoopStart to an equivalent DoLoopStart and branch. Note that // Revert a WhileLoopStart to an equivalent DoLoopStart and branch. Note that
// because of the branches this requires an extra block to be created. // because of the branches this requires an extra block to be created.
bool ARMBlockPlacement::revertWhileToDo(MachineInstr *WLS, MachineLoop *ML) { bool ARMBlockPlacement::revertWhileToDoLoop(MachineInstr *WLS) {
SjoerdMeijerUnsubmitted
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Unrelated nit: perhaps time to rename this to revertWhileToDoLoop while we are at it?

SjoerdMeijer: Unrelated nit: perhaps time to rename this to `revertWhileToDoLoop` while we are at it?
// lr = t2WhileLoopStartTP r0, r1, TgtBB // lr = t2WhileLoopStartTP r0, r1, TgtBB
// t2Br Ph // t2Br Ph
// -> // ->
// cmp r0, 0 // cmp r0, 0
// brcc TgtBB // brcc TgtBB
// block2: // block2:
// LR = t2DoLoopStartTP r0, r1 // LR = t2DoLoopStartTP r0, r1
// t2Br Ph // t2Br Ph
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines for (auto It = ++LoopExit->getIterator(); It != Predecessor->getIterator();
MachineBasicBlock *MBB = &*It; MachineBasicBlock *MBB = &*It;
for (auto &Terminator : MBB->terminators()) { for (auto &Terminator : MBB->terminators()) {
if (!isWhileLoopStart(Terminator)) if (!isWhileLoopStart(Terminator))
continue; continue;
MachineBasicBlock *WLSTarget = getWhileLoopStartTargetBB(Terminator); MachineBasicBlock *WLSTarget = getWhileLoopStartTargetBB(Terminator);
// TODO: Analyse the blocks to make a decision if it would be worth // TODO: Analyse the blocks to make a decision if it would be worth
// moving Preheader even if we'd introduce a backwards WLS // moving Preheader even if we'd introduce a backwards WLS
if (WLSTarget == Predecessor) { if (WLSTarget == Predecessor) {
LLVM_DEBUG( LLVM_DEBUG(dbgs() << DEBUG_PREFIX << "Can't move Predecessor block as "
dbgs() << DEBUG_PREFIX << "it would convert a WLS from forward to a "
<< "Can't move Predecessor" << "backwards branching WLS\n");
"block as it would convert a WLS from forward to a " RevertedWhileLoops.push_back(WlsInstr);
"backwards branching WLS\n"); return false;
return revertWhileToDo(WlsInstr, ML);
} }
} }
} }
moveBasicBlock(Predecessor, LoopExit); moveBasicBlock(Predecessor, LoopExit);
return true; return true;
} }
Show All 15 Linesbool ARMBlockPlacement::runOnMachineFunction(MachineFunction &MF) {
LLVM_DEBUG(dbgs() << DEBUG_PREFIX << "Running on " << MF.getName() << "\n"); LLVM_DEBUG(dbgs() << DEBUG_PREFIX << "Running on " << MF.getName() << "\n");
MLI = &getAnalysis<MachineLoopInfo>(); MLI = &getAnalysis<MachineLoopInfo>();
TII = static_cast<const ARMBaseInstrInfo *>(ST.getInstrInfo()); TII = static_cast<const ARMBaseInstrInfo *>(ST.getInstrInfo());
BBUtils = std::unique_ptr<ARMBasicBlockUtils>(new ARMBasicBlockUtils(MF)); BBUtils = std::unique_ptr<ARMBasicBlockUtils>(new ARMBasicBlockUtils(MF));
MF.RenumberBlocks(); MF.RenumberBlocks();
BBUtils->computeAllBlockSizes(); BBUtils->computeAllBlockSizes();
BBUtils->adjustBBOffsetsAfter(&MF.front()); BBUtils->adjustBBOffsetsAfter(&MF.front());
bool Changed = false; bool Changed = false;
RevertedWhileLoops.clear();
// Find loops with a backwards branching WLS and fix if possible. // Find loops with a backwards branching WLS and fix if possible.
for (auto *ML : *MLI) for (auto *ML : *MLI)
Changed |= processPostOrderLoops(ML); Changed |= processPostOrderLoops(ML);
// Revert any While loops still out of range to DLS loops.
for (auto *WlsInstr : RevertedWhileLoops)
Changed |= revertWhileToDoLoop(WlsInstr);
return Changed; return Changed;
} }
bool ARMBlockPlacement::blockIsBefore(MachineBasicBlock *BB, bool ARMBlockPlacement::blockIsBefore(MachineBasicBlock *BB,
MachineBasicBlock *Other) { MachineBasicBlock *Other) {
return BBUtils->getOffsetOf(Other) > BBUtils->getOffsetOf(BB); return BBUtils->getOffsetOf(Other) > BBUtils->getOffsetOf(BB);
} }
▲ Show 20 Lines • Show All 56 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/wls-revert-placement.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob %s -start-before=arm-block-placement --verify-machineinstrs -o - | FileCheck %s
# This is a large test for block placement, including reverting WLS to DLS. It
# should not crash or leave any VCTP instructions.
# CHECK-LABEL: test
# CHECK-NOT: vctp
--- |
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
@var_76 = external dso_local local_unnamed_addr global i64, align 8
@var_77 = external dso_local local_unnamed_addr global i8, align 1
@arr_163 = external dso_local local_unnamed_addr global [12 x [12 x i8]], align 1
@var_81 = external dso_local local_unnamed_addr global i32, align 4
@arr_239 = external dso_local local_unnamed_addr global [22 x i8], align 1
define i32 @test(i8 zeroext %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p, i32 %q) {
entry:
%tobool7.not = icmp eq i32 %i, 0
%cond11 = select i1 %tobool7.not, i32 %l, i32 %i
%tobool13 = icmp ne i32 %m, 0
%frombool = zext i1 %tobool13 to i8
%tobool23.not = icmp eq i8 %g, 0
%cond24 = select i1 %tobool23.not, i32 5, i32 0
%cmp27 = icmp sgt i32 %cond24, %m
%conv29 = zext i1 %cmp27 to i8
%conv36 = zext i8 %g to i32
%tobool38 = icmp ne i32 %n, 0
%tobool39 = icmp ne i32 %o, 0
%0 = select i1 %tobool38, i1 true, i1 %tobool39
%lor.ext = zext i1 %0 to i32
%cmp84 = icmp sgt i32 %k, 0
br i1 %cmp84, label %for.body.lr.ph, label %for.cond45.preheader
for.body.lr.ph: ; preds = %entry
%cmp2 = icmp slt i32 %n, 0
%cond = select i1 %cmp2, i32 %o, i32 0
%cmp1782.not = icmp eq i32 %i, -1514690832
%rem = srem i32 9, %p
br i1 %cmp1782.not, label %for.body.lr.ph.split, label %for.body.lr.ph.split.us
for.body.lr.ph.split.us: ; preds = %for.body.lr.ph
%1 = icmp slt i32 %rem, %cond
br i1 %1, label %for.body.lr.ph.split.us.split.us, label %for.body.lr.ph.split.us.split
for.body.lr.ph.split.us.split.us: ; preds = %for.body.lr.ph.split.us
%2 = sext i32 %cond11 to i64
%const19 = bitcast i32 1514690832 to i32
store i64 %2, i64* @var_76, align 8
store i8 %frombool, i8* @var_77, align 1
%3 = add i32 %i, %const19
%4 = add nsw i32 %k, -1
%xtraiter154 = and i32 %k, 3
%5 = icmp ult i32 %4, 3
br i1 %5, label %for.cond.for.cond45.preheader_crit_edge.loopexit135.unr-lcssa, label %for.body.lr.ph.split.us.split.us.new
for.body.lr.ph.split.us.split.us.new: ; preds = %for.body.lr.ph.split.us.split.us
%unroll_iter158 = and i32 %k, -4
br label %for.body.us.us
for.body.us.us: ; preds = %for.body.us.us, %for.body.lr.ph.split.us.split.us.new
%lsr.iv = phi [12 x [12 x i8]]* [ %6, %for.body.us.us ], [ bitcast (i8* getelementptr inbounds ([12 x [12 x i8]], [12 x [12 x i8]]* @arr_163, i32 0, i32 2, i32 0) to [12 x [12 x i8]]*), %for.body.lr.ph.split.us.split.us.new ]
%ac.085.us.us = phi i32 [ 0, %for.body.lr.ph.split.us.split.us.new ], [ %add43.us.us.3, %for.body.us.us ]
%lsr.iv3 = bitcast [12 x [12 x i8]]* %lsr.iv to i8*
%scevgep6 = getelementptr i8, i8* %lsr.iv3, i32 -24
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep6, i8 %conv29, i32 %3, i1 false)
%scevgep5 = getelementptr i8, i8* %lsr.iv3, i32 -12
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep5, i8 %conv29, i32 %3, i1 false)
call void @llvm.memset.p0i8.i32(i8* align 1 %lsr.iv3, i8 %conv29, i32 %3, i1 false)
%scevgep4 = getelementptr i8, i8* %lsr.iv3, i32 12
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep4, i8 %conv29, i32 %3, i1 false)
%add43.us.us.3 = add nuw i32 %ac.085.us.us, 4
%scevgep2 = getelementptr [12 x [12 x i8]], [12 x [12 x i8]]* %lsr.iv, i32 0, i32 4, i32 0
%6 = bitcast i8* %scevgep2 to [12 x [12 x i8]]*
%niter159.ncmp.3 = icmp eq i32 %unroll_iter158, %add43.us.us.3
br i1 %niter159.ncmp.3, label %for.cond.for.cond45.preheader_crit_edge.loopexit135.unr-lcssa, label %for.body.us.us
for.body.lr.ph.split.us.split: ; preds = %for.body.lr.ph.split.us
%7 = icmp eq i32 %m, 0
%const = bitcast i32 1514690832 to i32
%8 = add i32 %i, %const
%9 = add nsw i32 %k, -1
%xtraiter148 = and i32 %k, 3
br i1 %7, label %for.body.us.us115.preheader, label %for.body.us.preheader
for.body.us.preheader: ; preds = %for.body.lr.ph.split.us.split
%10 = icmp ult i32 %9, 3
br i1 %10, label %for.cond.for.cond45.preheader_crit_edge.loopexit147.unr-lcssa, label %for.body.us.preheader.new
for.body.us.preheader.new: ; preds = %for.body.us.preheader
%unroll_iter = and i32 %k, -4
br label %for.body.us
for.body.us.us115.preheader: ; preds = %for.body.lr.ph.split.us.split
%11 = icmp ult i32 %9, 3
br i1 %11, label %for.cond.for.cond45.preheader_crit_edge.loopexit.unr-lcssa, label %for.body.us.us115.preheader.new
for.body.us.us115.preheader.new: ; preds = %for.body.us.us115.preheader
%unroll_iter152 = and i32 %k, -4
br label %for.body.us.us115
for.body.us.us115: ; preds = %for.body.us.us115, %for.body.us.us115.preheader.new
%lsr.iv7 = phi [12 x [12 x i8]]* [ %12, %for.body.us.us115 ], [ bitcast (i8* getelementptr inbounds ([12 x [12 x i8]], [12 x [12 x i8]]* @arr_163, i32 0, i32 2, i32 0) to [12 x [12 x i8]]*), %for.body.us.us115.preheader.new ]
%ac.085.us.us116 = phi i32 [ 0, %for.body.us.us115.preheader.new ], [ %add43.us.us120.3, %for.body.us.us115 ]
%lsr.iv79 = bitcast [12 x [12 x i8]]* %lsr.iv7 to i8*
%scevgep12 = getelementptr i8, i8* %lsr.iv79, i32 -24
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep12, i8 %conv29, i32 %8, i1 false)
%scevgep11 = getelementptr i8, i8* %lsr.iv79, i32 -12
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep11, i8 %conv29, i32 %8, i1 false)
call void @llvm.memset.p0i8.i32(i8* align 1 %lsr.iv79, i8 %conv29, i32 %8, i1 false)
%scevgep10 = getelementptr i8, i8* %lsr.iv79, i32 12
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep10, i8 %conv29, i32 %8, i1 false)
%add43.us.us120.3 = add nuw i32 %ac.085.us.us116, 4
%scevgep8 = getelementptr [12 x [12 x i8]], [12 x [12 x i8]]* %lsr.iv7, i32 0, i32 4, i32 0
%12 = bitcast i8* %scevgep8 to [12 x [12 x i8]]*
%niter153.ncmp.3 = icmp eq i32 %unroll_iter152, %add43.us.us120.3
br i1 %niter153.ncmp.3, label %for.cond.for.cond45.preheader_crit_edge.loopexit.unr-lcssa, label %for.body.us.us115
for.body.us: ; preds = %for.body.us, %for.body.us.preheader.new
%lsr.iv13 = phi [12 x [12 x i8]]* [ %13, %for.body.us ], [ bitcast (i8* getelementptr inbounds ([12 x [12 x i8]], [12 x [12 x i8]]* @arr_163, i32 0, i32 2, i32 0) to [12 x [12 x i8]]*), %for.body.us.preheader.new ]
%ac.085.us = phi i32 [ 0, %for.body.us.preheader.new ], [ %add43.us.3, %for.body.us ]
%lsr.iv1315 = bitcast [12 x [12 x i8]]* %lsr.iv13 to i8*
%scevgep18 = getelementptr i8, i8* %lsr.iv1315, i32 -24
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep18, i8 %conv29, i32 %8, i1 false)
%scevgep17 = getelementptr i8, i8* %lsr.iv1315, i32 -12
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep17, i8 %conv29, i32 %8, i1 false)
call void @llvm.memset.p0i8.i32(i8* align 1 %lsr.iv1315, i8 %conv29, i32 %8, i1 false)
%scevgep16 = getelementptr i8, i8* %lsr.iv1315, i32 12
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep16, i8 %conv29, i32 %8, i1 false)
%add43.us.3 = add nuw i32 %ac.085.us, 4
%scevgep14 = getelementptr [12 x [12 x i8]], [12 x [12 x i8]]* %lsr.iv13, i32 0, i32 4, i32 0
%13 = bitcast i8* %scevgep14 to [12 x [12 x i8]]*
%niter.ncmp.3 = icmp eq i32 %unroll_iter, %add43.us.3
br i1 %niter.ncmp.3, label %for.cond.for.cond45.preheader_crit_edge.loopexit147.unr-lcssa, label %for.body.us
for.body.lr.ph.split: ; preds = %for.body.lr.ph
%14 = icmp slt i32 %rem, %cond
br i1 %14, label %for.body.lr.ph.split.split.us, label %for.body.lr.ph.split.split
for.body.lr.ph.split.split.us: ; preds = %for.body.lr.ph.split
%15 = icmp eq i32 %m, 0
%16 = sext i32 %cond11 to i64
store i64 %16, i64* @var_76, align 8
store i8 %frombool, i8* @var_77, align 1
%spec.select = select i1 %15, i32 %lor.ext, i32 %conv36
br label %for.cond.for.cond45.preheader_crit_edge
for.body.lr.ph.split.split: ; preds = %for.body.lr.ph.split
%17 = icmp eq i32 %m, 0
%spec.select143 = select i1 %17, i32 %lor.ext, i32 %conv36
br label %for.cond.for.cond45.preheader_crit_edge
for.cond.for.cond45.preheader_crit_edge.loopexit135.unr-lcssa: ; preds = %for.body.us.us, %for.body.lr.ph.split.us.split.us
%ac.085.us.us.unr = phi i32 [ 0, %for.body.lr.ph.split.us.split.us ], [ %add43.us.us.3, %for.body.us.us ]
%lcmp.mod157.not = icmp eq i32 %xtraiter154, 0
br i1 %lcmp.mod157.not, label %for.cond.for.cond45.preheader_crit_edge.loopexit135, label %for.body.us.us.epil
for.body.us.us.epil: ; preds = %for.cond.for.cond45.preheader_crit_edge.loopexit135.unr-lcssa
%scevgep140.epil = getelementptr [12 x [12 x i8]], [12 x [12 x i8]]* @arr_163, i32 0, i32 %ac.085.us.us.unr, i32 0
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep140.epil, i8 %conv29, i32 %3, i1 false)
%epil.iter.cmp156.not = icmp eq i32 %xtraiter154, 1
br i1 %epil.iter.cmp156.not, label %for.cond.for.cond45.preheader_crit_edge.loopexit135, label %for.body.us.us.epil.1
for.cond.for.cond45.preheader_crit_edge.loopexit135: ; preds = %for.body.us.us.epil.2, %for.body.us.us.epil.1, %for.body.us.us.epil, %for.cond.for.cond45.preheader_crit_edge.loopexit135.unr-lcssa
%18 = icmp eq i32 %m, 0
%cond41.us.us = select i1 %18, i32 %lor.ext, i32 %conv36
br label %for.cond.for.cond45.preheader_crit_edge
for.cond.for.cond45.preheader_crit_edge.loopexit.unr-lcssa: ; preds = %for.body.us.us115, %for.body.us.us115.preheader
%ac.085.us.us116.unr = phi i32 [ 0, %for.body.us.us115.preheader ], [ %add43.us.us120.3, %for.body.us.us115 ]
%lcmp.mod151.not = icmp eq i32 %xtraiter148, 0
br i1 %lcmp.mod151.not, label %for.cond.for.cond45.preheader_crit_edge, label %for.body.us.us115.epil
for.body.us.us115.epil: ; preds = %for.cond.for.cond45.preheader_crit_edge.loopexit.unr-lcssa
%scevgep138.epil = getelementptr [12 x [12 x i8]], [12 x [12 x i8]]* @arr_163, i32 0, i32 %ac.085.us.us116.unr, i32 0
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep138.epil, i8 %conv29, i32 %8, i1 false)
%epil.iter.cmp150.not = icmp eq i32 %xtraiter148, 1
br i1 %epil.iter.cmp150.not, label %for.cond.for.cond45.preheader_crit_edge, label %for.body.us.us115.epil.1
for.cond.for.cond45.preheader_crit_edge.loopexit147.unr-lcssa: ; preds = %for.body.us, %for.body.us.preheader
%ac.085.us.unr = phi i32 [ 0, %for.body.us.preheader ], [ %add43.us.3, %for.body.us ]
%lcmp.mod.not = icmp eq i32 %xtraiter148, 0
br i1 %lcmp.mod.not, label %for.cond.for.cond45.preheader_crit_edge, label %for.body.us.epil
for.body.us.epil: ; preds = %for.cond.for.cond45.preheader_crit_edge.loopexit147.unr-lcssa
%scevgep.epil = getelementptr [12 x [12 x i8]], [12 x [12 x i8]]* @arr_163, i32 0, i32 %ac.085.us.unr, i32 0
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep.epil, i8 %conv29, i32 %8, i1 false)
%epil.iter.cmp.not = icmp eq i32 %xtraiter148, 1
br i1 %epil.iter.cmp.not, label %for.cond.for.cond45.preheader_crit_edge, label %for.body.us.epil.1
for.cond.for.cond45.preheader_crit_edge: ; preds = %for.body.us.us115.epil.2, %for.body.us.us115.epil.1, %for.body.us.epil.2, %for.body.us.epil.1, %for.body.us.epil, %for.cond.for.cond45.preheader_crit_edge.loopexit147.unr-lcssa, %for.body.us.us115.epil, %for.cond.for.cond45.preheader_crit_edge.loopexit.unr-lcssa, %for.cond.for.cond45.preheader_crit_edge.loopexit135, %for.body.lr.ph.split.split, %for.body.lr.ph.split.split.us
%.us-phi = phi i32 [ %cond41.us.us, %for.cond.for.cond45.preheader_crit_edge.loopexit135 ], [ %spec.select, %for.body.lr.ph.split.split.us ], [ %spec.select143, %for.body.lr.ph.split.split ], [ %lor.ext, %for.body.us.us115.epil ], [ %lor.ext, %for.body.us.us115.epil.1 ], [ %lor.ext, %for.body.us.us115.epil.2 ], [ %lor.ext, %for.cond.for.cond45.preheader_crit_edge.loopexit.unr-lcssa ], [ %conv36, %for.body.us.epil ], [ %conv36, %for.body.us.epil.1 ], [ %conv36, %for.body.us.epil.2 ], [ %conv36, %for.cond.for.cond45.preheader_crit_edge.loopexit147.unr-lcssa ]
store i32 %.us-phi, i32* @var_81, align 4
br label %for.cond45.preheader
for.cond45.preheader: ; preds = %for.cond.for.cond45.preheader_crit_edge, %entry
%tobool54.not = icmp eq i32 %q, 0
%tobool56.not = icmp eq i32 %j, 0
%conv58 = select i1 %tobool56.not, i8 22, i8 0
br i1 %tobool54.not, label %for.cond45.us.preheader, label %for.cond45.preheader1
for.cond45.preheader1: ; preds = %for.cond45.preheader
br label %for.cond45
for.cond45.us.preheader: ; preds = %for.cond45.preheader
br label %for.cond45.us
for.cond45.us: ; preds = %for.cond45.us.preheader, %for.cond45.us
br label %for.cond45.us
for.cond45: ; preds = %for.cond45.preheader1, %for.cond45
%ag.0 = phi i32 [ %cond51.3, %for.cond45 ], [ 0, %for.cond45.preheader1 ]
%conv46 = and i32 %ag.0, 255
%tobool47.not = icmp eq i32 %conv46, 0
%cond51 = select i1 %tobool47.not, i32 %l, i32 %h
%idxprom = and i32 %cond51, 255
%arrayidx59 = getelementptr inbounds [22 x i8], [22 x i8]* @arr_239, i32 0, i32 %idxprom
store i8 %conv58, i8* %arrayidx59, align 1
%conv46.1 = and i32 %cond51, 255
%tobool47.not.1 = icmp eq i32 %conv46.1, 0
%cond51.1 = select i1 %tobool47.not.1, i32 %l, i32 %h
%idxprom.1 = and i32 %cond51.1, 255
%arrayidx59.1 = getelementptr inbounds [22 x i8], [22 x i8]* @arr_239, i32 0, i32 %idxprom.1
store i8 %conv58, i8* %arrayidx59.1, align 1
%conv46.2 = and i32 %cond51.1, 255
%tobool47.not.2 = icmp eq i32 %conv46.2, 0
%cond51.2 = select i1 %tobool47.not.2, i32 %l, i32 %h
%idxprom.2 = and i32 %cond51.2, 255
%arrayidx59.2 = getelementptr inbounds [22 x i8], [22 x i8]* @arr_239, i32 0, i32 %idxprom.2
store i8 %conv58, i8* %arrayidx59.2, align 1
%conv46.3 = and i32 %cond51.2, 255
%tobool47.not.3 = icmp eq i32 %conv46.3, 0
%cond51.3 = select i1 %tobool47.not.3, i32 %l, i32 %h
%idxprom.3 = and i32 %cond51.3, 255
%arrayidx59.3 = getelementptr inbounds [22 x i8], [22 x i8]* @arr_239, i32 0, i32 %idxprom.3
store i8 %conv58, i8* %arrayidx59.3, align 1
br label %for.cond45
for.body.us.epil.1: ; preds = %for.body.us.epil
%add43.us.epil = add nuw nsw i32 %ac.085.us.unr, 1
%scevgep.epil.1 = getelementptr [12 x [12 x i8]], [12 x [12 x i8]]* @arr_163, i32 0, i32 %add43.us.epil, i32 0
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep.epil.1, i8 %conv29, i32 %8, i1 false)
%epil.iter.cmp.1.not = icmp eq i32 %xtraiter148, 2
br i1 %epil.iter.cmp.1.not, label %for.cond.for.cond45.preheader_crit_edge, label %for.body.us.epil.2
for.body.us.epil.2: ; preds = %for.body.us.epil.1
%add43.us.epil.1 = add nuw nsw i32 %ac.085.us.unr, 2
%scevgep.epil.2 = getelementptr [12 x [12 x i8]], [12 x [12 x i8]]* @arr_163, i32 0, i32 %add43.us.epil.1, i32 0
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep.epil.2, i8 %conv29, i32 %8, i1 false)
br label %for.cond.for.cond45.preheader_crit_edge
for.body.us.us115.epil.1: ; preds = %for.body.us.us115.epil
%add43.us.us120.epil = add nuw nsw i32 %ac.085.us.us116.unr, 1
%scevgep138.epil.1 = getelementptr [12 x [12 x i8]], [12 x [12 x i8]]* @arr_163, i32 0, i32 %add43.us.us120.epil, i32 0
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep138.epil.1, i8 %conv29, i32 %8, i1 false)
%epil.iter.cmp150.1.not = icmp eq i32 %xtraiter148, 2
br i1 %epil.iter.cmp150.1.not, label %for.cond.for.cond45.preheader_crit_edge, label %for.body.us.us115.epil.2
for.body.us.us115.epil.2: ; preds = %for.body.us.us115.epil.1
%add43.us.us120.epil.1 = add nuw nsw i32 %ac.085.us.us116.unr, 2
%scevgep138.epil.2 = getelementptr [12 x [12 x i8]], [12 x [12 x i8]]* @arr_163, i32 0, i32 %add43.us.us120.epil.1, i32 0
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep138.epil.2, i8 %conv29, i32 %8, i1 false)
br label %for.cond.for.cond45.preheader_crit_edge
for.body.us.us.epil.1: ; preds = %for.body.us.us.epil
%add43.us.us.epil = add nuw nsw i32 %ac.085.us.us.unr, 1
%scevgep140.epil.1 = getelementptr [12 x [12 x i8]], [12 x [12 x i8]]* @arr_163, i32 0, i32 %add43.us.us.epil, i32 0
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep140.epil.1, i8 %conv29, i32 %3, i1 false)
%epil.iter.cmp156.1.not = icmp eq i32 %xtraiter154, 2
br i1 %epil.iter.cmp156.1.not, label %for.cond.for.cond45.preheader_crit_edge.loopexit135, label %for.body.us.us.epil.2
for.body.us.us.epil.2: ; preds = %for.body.us.us.epil.1
%add43.us.us.epil.1 = add nuw nsw i32 %ac.085.us.us.unr, 2
%scevgep140.epil.2 = getelementptr [12 x [12 x i8]], [12 x [12 x i8]]* @arr_163, i32 0, i32 %add43.us.us.epil.1, i32 0
call void @llvm.memset.p0i8.i32(i8* align 1 %scevgep140.epil.2, i8 %conv29, i32 %3, i1 false)
br label %for.cond.for.cond45.preheader_crit_edge.loopexit135
}
declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1 immarg)
...
---
name: test
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' }
- { reg: '$r2', virtual-reg: '' }
- { reg: '$r3', virtual-reg: '' }
fixedStack:
- { id: 0, type: default, offset: 24, size: 4, alignment: 8, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, type: default, offset: 20, size: 4, alignment: 4, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, type: default, offset: 16, size: 4, alignment: 8, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 3, type: default, offset: 12, size: 4, alignment: 4, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 4, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 5, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 6, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
stack:
- { id: 0, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -44, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: -48, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 3, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 4, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r11', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 5, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 6, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 7, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 8, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 9, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 10, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 11, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: |
bb.0.entry:
successors: %bb.1(0x50000000), %bb.61(0x30000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
$sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
frame-setup CFI_INSTRUCTION def_cfa_offset 36
frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r11, -8
frame-setup CFI_INSTRUCTION offset $r10, -12
frame-setup CFI_INSTRUCTION offset $r9, -16
frame-setup CFI_INSTRUCTION offset $r8, -20
frame-setup CFI_INSTRUCTION offset $r7, -24
frame-setup CFI_INSTRUCTION offset $r6, -28
frame-setup CFI_INSTRUCTION offset $r5, -32
frame-setup CFI_INSTRUCTION offset $r4, -36
$sp = frame-setup tSUBspi $sp, 3, 14 /* CC::al */, $noreg
frame-setup CFI_INSTRUCTION def_cfa_offset 48
$r9, $r6 = t2LDRDi8 $sp, 56, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.4, align 8), (load (s32) from %fixed-stack.3)
$r8, $r12 = t2LDRDi8 $sp, 48, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.6, align 8), (load (s32) from %fixed-stack.5)
tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
renamable $r11 = t2CSEL renamable $r12, renamable $r2, 0, implicit killed $cpsr
t2CMPri renamable $r9, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
renamable $lr = t2CSINC $zr, $zr, 0, implicit killed $cpsr
tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
renamable $r4 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
renamable $r7 = tLDRspi $sp, 16, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.2, align 8)
t2IT 0, 8, implicit-def $itstate
$r4 = tMOVi8 $noreg, 5, 0 /* CC::eq */, killed $cpsr, implicit killed renamable $r4, implicit killed $itstate
tCMPhir killed renamable $r4, renamable $r9, 14 /* CC::al */, $noreg, implicit-def $cpsr
renamable $r4 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
renamable $r5 = tLDRspi $sp, 18, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
tSTRspi killed renamable $r4, $sp, 2, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
dead renamable $r4 = t2ORRrr renamable $r6, renamable $r7, 14 /* CC::al */, $noreg, def $cpsr
renamable $r4 = t2CSINC $zr, $zr, 0, implicit killed $cpsr
t2CMPri renamable $r8, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
renamable $r10 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
t2Bcc %bb.61, 11 /* CC::lt */, killed $cpsr
bb.1.for.body.lr.ph:
successors: %bb.37(0x40000000), %bb.2(0x40000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $r5 = tLDRspi $sp, 17, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.1)
tSTRspi killed renamable $r4, $sp, 1, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1)
renamable $r4, dead $cpsr = tMOVi8 9, 14 /* CC::al */, $noreg
renamable $r4 = t2SDIV killed renamable $r4, renamable $r5, 14 /* CC::al */, $noreg
renamable $r7 = t2ANDrs killed renamable $r7, killed renamable $r6, 249, 14 /* CC::al */, $noreg, $noreg
renamable $r5, dead $cpsr = tMUL killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg
$r4 = t2MOVi16 42736, 14 /* CC::al */, $noreg
$r4 = t2MOVTi16 killed $r4, 42423, 14 /* CC::al */, $noreg
tCMPr renamable $r2, killed renamable $r4, 14 /* CC::al */, $noreg, implicit-def $cpsr
renamable $r6 = t2RSBri killed renamable $r5, 9, 14 /* CC::al */, $noreg, $noreg
t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr
bb.37.for.body.lr.ph.split:
successors: %bb.38(0x40000000), %bb.39(0x40000000)
liveins: $lr, $r0, $r1, $r3, $r6, $r7, $r9, $r10, $r11, $r12
tCMPr killed renamable $r6, killed renamable $r7, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2Bcc %bb.39, 10 /* CC::ge */, killed $cpsr
bb.38.for.body.lr.ph.split.split.us:
successors: %bb.39(0x80000000)
liveins: $lr, $r0, $r1, $r3, $r9, $r10, $r11, $r12
$r4 = t2MOVi16 target-flags(arm-lo16) @var_76, 14 /* CC::al */, $noreg
renamable $r2 = t2ASRri renamable $r11, 31, 14 /* CC::al */, $noreg, $noreg
$r4 = t2MOVTi16 killed $r4, target-flags(arm-hi16) @var_76, 14 /* CC::al */, $noreg
t2STRDi8 killed $r11, killed $r2, killed $r4, 0, 14 /* CC::al */, $noreg :: (store (s32) into @var_76, align 8), (store (s32) into @var_76 + 4, basealign 8)
$r2 = t2MOVi16 target-flags(arm-lo16) @var_77, 14 /* CC::al */, $noreg
$r2 = t2MOVTi16 killed $r2, target-flags(arm-hi16) @var_77, 14 /* CC::al */, $noreg
t2STRBi12 killed renamable $lr, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s8) into @var_77)
bb.39.for.body.lr.ph.split.split:
successors: %bb.59(0x80000000)
liveins: $r1, $r3, $r12, $r10, $r0, $r9
renamable $r2 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1)
t2CMPri killed renamable $r9, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
renamable $r0 = t2CSEL killed renamable $r2, killed renamable $r0, 0, implicit killed $cpsr
t2B %bb.59, 14 /* CC::al */, $noreg
bb.2.for.body.lr.ph.split.us:
successors: %bb.3(0x40000000), %bb.14(0x40000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r6, $r7, $r8, $r9, $r10, $r11, $r12
tCMPr killed renamable $r6, killed renamable $r7, 14 /* CC::al */, $noreg, implicit-def $cpsr
tSTRspi killed renamable $r3, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2)
t2Bcc %bb.14, 10 /* CC::ge */, killed $cpsr
bb.3.for.body.lr.ph.split.us.split.us:
successors: %bb.4(0x40000000), %bb.5(0x40000000)
liveins: $lr, $r0, $r1, $r2, $r8, $r9, $r10, $r11, $r12
$r4 = t2MOVi16 target-flags(arm-lo16) @var_76, 14 /* CC::al */, $noreg
renamable $r3 = t2ASRri renamable $r11, 31, 14 /* CC::al */, $noreg, $noreg
$r4 = t2MOVTi16 killed $r4, target-flags(arm-hi16) @var_76, 14 /* CC::al */, $noreg
t2STRDi8 killed $r11, killed $r3, killed $r4, 0, 14 /* CC::al */, $noreg :: (store (s32) into @var_76, align 8), (store (s32) into @var_76 + 4, basealign 8)
$r3 = t2MOVi16 target-flags(arm-lo16) @var_77, 14 /* CC::al */, $noreg
$r3 = t2MOVTi16 killed $r3, target-flags(arm-hi16) @var_77, 14 /* CC::al */, $noreg
t2STRBi12 killed renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s8) into @var_77)
$r3 = t2MOVi16 22800, 14 /* CC::al */, $noreg
$r3 = t2MOVTi16 killed $r3, 23112, 14 /* CC::al */, $noreg
renamable $r11 = t2ADDrr killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg
renamable $r2 = nsw t2SUBri renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg
tCMPi8 killed renamable $r2, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
renamable $r3 = t2ANDri renamable $r8, 3, 14 /* CC::al */, $noreg, $noreg
t2Bcc %bb.5, 2 /* CC::hs */, killed $cpsr
bb.4:
successors: %bb.41(0x80000000)
liveins: $r0, $r1, $r3, $r9, $r10, $r11, $r12
renamable $r4, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
bb.41.for.cond.for.cond45.preheader_crit_edge.loopexit135.unr-lcssa:
successors: %bb.45(0x30000000), %bb.42(0x50000000)
liveins: $r0, $r1, $r3, $r4, $r9, $r10, $r11, $r12
renamable $r7 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2Bcc %bb.45, 0 /* CC::eq */, killed $cpsr
bb.42.for.body.us.us.epil:
successors: %bb.44(0x40000000), %bb.43(0x40000000)
liveins: $r0, $r1, $r3, $r4, $r7, $r9, $r10, $r11, $r12
$r8 = t2MOVi16 target-flags(arm-lo16) @arr_163, 14 /* CC::al */, $noreg
renamable $r5 = t2ADDrs killed renamable $r4, renamable $r4, 10, 14 /* CC::al */, $noreg, $noreg
$r8 = t2MOVTi16 killed $r8, target-flags(arm-hi16) @arr_163, 14 /* CC::al */, $noreg
renamable $r2 = t2ADDri renamable $r11, 15, 14 /* CC::al */, $noreg, $noreg
renamable $r6 = t2ADDrs renamable $r8, renamable $r5, 18, 14 /* CC::al */, $noreg, $noreg
renamable $q0 = MVE_VDUP8 renamable $r7, 0, $noreg, $noreg, undef renamable $q0
renamable $r4, dead $cpsr = tLSRri killed renamable $r2, 4, 14 /* CC::al */, $noreg
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r4, renamable $r11, %bb.44, implicit-def dead $cpsr
t2B %bb.43, 14 /* CC::al */, $noreg
bb.43:
successors: %bb.43(0x40000000), %bb.44(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r6 = MVE_VSTRBU8_post renamable $q0, killed renamable $r6, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.43, implicit-def dead $cpsr
t2B %bb.44, 14 /* CC::al */, $noreg
bb.44.for.body.us.us.epil:
successors: %bb.45(0x40000000), %bb.74(0x40000000)
liveins: $r0, $r1, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r11, $r12
tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2Bcc %bb.45, 0 /* CC::eq */, killed $cpsr
bb.74.for.body.us.us.epil.1:
successors: %bb.76(0x40000000), %bb.75(0x40000000)
liveins: $r0, $r1, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r11, $r12
renamable $r5 = t2ADDrs killed renamable $r8, killed renamable $r5, 18, 14 /* CC::al */, $noreg, $noreg
renamable $r6 = t2ADDri renamable $r5, 12, 14 /* CC::al */, $noreg, $noreg
renamable $q0 = MVE_VDUP8 renamable $r7, 0, $noreg, $noreg, undef renamable $q0
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r4, renamable $r11, %bb.76, implicit-def dead $cpsr
t2B %bb.75, 14 /* CC::al */, $noreg
bb.75:
successors: %bb.75(0x40000000), %bb.76(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r6 = MVE_VSTRBU8_post renamable $q0, killed renamable $r6, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.75, implicit-def dead $cpsr
t2B %bb.76, 14 /* CC::al */, $noreg
bb.76.for.body.us.us.epil.1:
successors: %bb.45(0x40000000), %bb.77(0x40000000)
liveins: $r0, $r1, $r3, $r4, $r5, $r7, $r9, $r10, $r11, $r12
tCMPi8 killed renamable $r3, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2Bcc %bb.45, 0 /* CC::eq */, killed $cpsr
bb.77.for.body.us.us.epil.2:
successors: %bb.45(0x40000000), %bb.78(0x40000000)
liveins: $r0, $r1, $r4, $r5, $r7, $r9, $r10, $r11, $r12
renamable $r5, dead $cpsr = tADDi8 killed renamable $r5, 24, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VDUP8 killed renamable $r7, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2WhileLoopStartTP killed renamable $r4, renamable $r11, %bb.45, implicit-def dead $cpsr
t2B %bb.78, 14 /* CC::al */, $noreg
bb.78:
successors: %bb.78(0x40000000), %bb.45(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r5, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r11, 0, $noreg, $noreg
renamable $r11 = t2SUBri killed renamable $r11, 16, 14 /* CC::al */, $noreg, $noreg
MVE_VPST 8, implicit $vpr
renamable $r5 = MVE_VSTRBU8_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.78, implicit-def dead $cpsr
t2B %bb.45, 14 /* CC::al */, $noreg
bb.45.for.cond.for.cond45.preheader_crit_edge.loopexit135:
successors: %bb.58(0x80000000)
liveins: $r0, $r1, $r9, $r10, $r12
renamable $r2 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1)
t2CMPri killed renamable $r9, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
renamable $r0 = t2CSEL killed renamable $r2, killed renamable $r0, 0, implicit killed $cpsr
t2B %bb.58, 14 /* CC::al */, $noreg
bb.14.for.body.lr.ph.split.us.split:
successors: %bb.17(0x30000000), %bb.15(0x50000000)
liveins: $r0, $r1, $r2, $r8, $r9, $r10, $r12
$r3 = t2MOVi16 22800, 14 /* CC::al */, $noreg
$r3 = t2MOVTi16 killed $r3, 23112, 14 /* CC::al */, $noreg
renamable $r11 = t2ADDrr killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg
renamable $r2 = nsw t2SUBri renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg
t2CMPri killed renamable $r9, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
renamable $r9 = t2ANDri renamable $r8, 3, 14 /* CC::al */, $noreg, $noreg
t2Bcc %bb.17, 0 /* CC::eq */, killed $cpsr
bb.15.for.body.us.preheader:
successors: %bb.16(0x40000000), %bb.28(0x40000000)
liveins: $r0, $r1, $r2, $r8, $r9, $r10, $r11, $r12
$r3 = t2MOVi16 target-flags(arm-lo16) @arr_163, 14 /* CC::al */, $noreg
tCMPi8 killed renamable $r2, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
$r3 = t2MOVTi16 killed $r3, target-flags(arm-hi16) @arr_163, 14 /* CC::al */, $noreg
t2Bcc %bb.28, 2 /* CC::hs */, killed $cpsr
bb.16:
successors: %bb.54(0x80000000)
liveins: $r0, $r1, $r3, $r9, $r10, $r11, $r12
renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
bb.54.for.cond.for.cond45.preheader_crit_edge.loopexit147.unr-lcssa:
successors: %bb.58(0x30000000), %bb.55(0x50000000)
liveins: $r0, $r1, $r3, $r6, $r9, $r10, $r11, $r12
t2CMPri renamable $r9, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2Bcc %bb.58, 0 /* CC::eq */, killed $cpsr
bb.55.for.body.us.epil:
successors: %bb.57(0x40000000), %bb.56(0x40000000)
liveins: $r0, $r1, $r3, $r6, $r9, $r10, $r11, $r12
renamable $r2 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
renamable $r5 = t2ADDrs killed renamable $r6, renamable $r6, 10, 14 /* CC::al */, $noreg, $noreg
renamable $q0 = MVE_VDUP8 killed renamable $r2, 0, $noreg, $noreg, undef renamable $q0
renamable $r2 = t2ADDri renamable $r11, 15, 14 /* CC::al */, $noreg, $noreg
renamable $r6 = t2ADDrs renamable $r3, renamable $r5, 18, 14 /* CC::al */, $noreg, $noreg
renamable $r4, dead $cpsr = tLSRri killed renamable $r2, 4, 14 /* CC::al */, $noreg
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r4, renamable $r11, %bb.57, implicit-def dead $cpsr
t2B %bb.56, 14 /* CC::al */, $noreg
bb.56:
successors: %bb.56(0x40000000), %bb.57(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r6 = MVE_VSTRBU8_post renamable $q0, killed renamable $r6, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.56, implicit-def dead $cpsr
t2B %bb.57, 14 /* CC::al */, $noreg
bb.57.for.body.us.epil:
successors: %bb.58(0x40000000), %bb.64(0x40000000)
liveins: $r0, $r1, $r3, $r4, $r5, $r9, $r10, $r11, $r12
t2CMPri renamable $r9, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2Bcc %bb.58, 0 /* CC::eq */, killed $cpsr
bb.64.for.body.us.epil.1:
successors: %bb.66(0x40000000), %bb.65(0x40000000)
liveins: $r0, $r1, $r3, $r4, $r5, $r9, $r10, $r11, $r12
renamable $r5 = t2ADDrs killed renamable $r3, killed renamable $r5, 18, 14 /* CC::al */, $noreg, $noreg
renamable $r3 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
renamable $r6 = t2ADDri renamable $r5, 12, 14 /* CC::al */, $noreg, $noreg
renamable $q0 = MVE_VDUP8 renamable $r3, 0, $noreg, $noreg, undef renamable $q0
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r4, renamable $r11, %bb.66, implicit-def dead $cpsr
t2B %bb.65, 14 /* CC::al */, $noreg
bb.65:
successors: %bb.65(0x40000000), %bb.66(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r6 = MVE_VSTRBU8_post renamable $q0, killed renamable $r6, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.65, implicit-def dead $cpsr
t2B %bb.66, 14 /* CC::al */, $noreg
bb.66.for.body.us.epil.1:
successors: %bb.58(0x40000000), %bb.67(0x40000000)
liveins: $r0, $r1, $r3, $r4, $r5, $r9, $r10, $r11, $r12
t2CMPri killed renamable $r9, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2Bcc %bb.58, 0 /* CC::eq */, killed $cpsr
bb.67.for.body.us.epil.2:
successors: %bb.58(0x40000000), %bb.68(0x40000000)
liveins: $r0, $r1, $r3, $r4, $r5, $r10, $r11, $r12
renamable $r5, dead $cpsr = tADDi8 killed renamable $r5, 24, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VDUP8 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2WhileLoopStartTP killed renamable $r4, renamable $r11, %bb.58, implicit-def dead $cpsr
t2B %bb.68, 14 /* CC::al */, $noreg
bb.68:
successors: %bb.68(0x40000000), %bb.58(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r5, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r11, 0, $noreg, $noreg
renamable $r11 = t2SUBri killed renamable $r11, 16, 14 /* CC::al */, $noreg, $noreg
MVE_VPST 8, implicit $vpr
renamable $r5 = MVE_VSTRBU8_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.68, implicit-def dead $cpsr
t2B %bb.58, 14 /* CC::al */, $noreg
bb.5.for.body.lr.ph.split.us.split.us.new:
successors: %bb.6(0x80000000)
liveins: $r0, $r1, $r3, $r8, $r9, $r10, $r11, $r12
$r2 = t2MOVi16 target-flags(arm-lo16) @arr_163, 14 /* CC::al */, $noreg
$r2 = t2MOVTi16 killed $r2, target-flags(arm-hi16) @arr_163, 14 /* CC::al */, $noreg
renamable $r5 = nuw t2ADDri killed renamable $r2, 24, 14 /* CC::al */, $noreg, $noreg
renamable $r2 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
renamable $r6 = t2BICri killed renamable $r8, 3, 14 /* CC::al */, $noreg, $noreg
renamable $q0 = MVE_VDUP8 killed renamable $r2, 0, $noreg, $noreg, undef renamable $q0
renamable $r2 = t2ADDri renamable $r11, 15, 14 /* CC::al */, $noreg, $noreg
renamable $r4, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
renamable $r8 = t2LSRri killed renamable $r2, 4, 14 /* CC::al */, $noreg, $noreg
t2B %bb.6, 14 /* CC::al */, $noreg
bb.40.for.body.us.us (align 4):
successors: %bb.41(0x04000000), %bb.6(0x7c000000)
liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12
renamable $r4, dead $cpsr = nuw tADDi8 killed renamable $r4, 4, 14 /* CC::al */, $noreg
tCMPr renamable $r6, renamable $r4, 14 /* CC::al */, $noreg, implicit-def $cpsr
renamable $r5 = t2ADDri killed renamable $r5, 48, 14 /* CC::al */, $noreg, $noreg
t2Bcc %bb.41, 0 /* CC::eq */, killed $cpsr
bb.6.for.body.us.us:
successors: %bb.8(0x40000000), %bb.7(0x40000000)
liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12
renamable $r7 = t2SUBri renamable $r5, 24, 14 /* CC::al */, $noreg, $noreg
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r8, renamable $r11, %bb.8, implicit-def dead $cpsr
t2B %bb.7, 14 /* CC::al */, $noreg
bb.7:
successors: %bb.7(0x40000000), %bb.8(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.7, implicit-def dead $cpsr
t2B %bb.8, 14 /* CC::al */, $noreg
bb.8.for.body.us.us:
successors: %bb.10(0x40000000), %bb.9(0x40000000)
liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12
renamable $r7 = t2SUBri renamable $r5, 12, 14 /* CC::al */, $noreg, $noreg
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r8, renamable $r11, %bb.10, implicit-def dead $cpsr
t2B %bb.9, 14 /* CC::al */, $noreg
bb.9:
successors: %bb.9(0x40000000), %bb.10(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.9, implicit-def dead $cpsr
t2B %bb.10, 14 /* CC::al */, $noreg
bb.10.for.body.us.us:
successors: %bb.12(0x40000000), %bb.11(0x40000000)
liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12
$r7 = tMOVr $r5, 14 /* CC::al */, $noreg
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r8, renamable $r11, %bb.12, implicit-def dead $cpsr
t2B %bb.11, 14 /* CC::al */, $noreg
bb.11:
successors: %bb.11(0x40000000), %bb.12(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.11, implicit-def dead $cpsr
t2B %bb.12, 14 /* CC::al */, $noreg
bb.12.for.body.us.us:
successors: %bb.40(0x40000000), %bb.13(0x40000000)
liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12
renamable $r7 = t2ADDri renamable $r5, 12, 14 /* CC::al */, $noreg, $noreg
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r8, renamable $r11, %bb.40, implicit-def dead $cpsr
t2B %bb.13, 14 /* CC::al */, $noreg
bb.13:
successors: %bb.13(0x40000000), %bb.40(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.13, implicit-def dead $cpsr
t2B %bb.40, 14 /* CC::al */, $noreg
bb.17.for.body.us.us115.preheader:
successors: %bb.18(0x40000000), %bb.19(0x40000000)
liveins: $r1, $r2, $r8, $r9, $r10, $r11, $r12
tCMPi8 killed renamable $r2, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2Bcc %bb.19, 2 /* CC::hs */, killed $cpsr
bb.18:
successors: %bb.47(0x80000000)
liveins: $r1, $r9, $r10, $r11, $r12
renamable $r3 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
bb.47.for.cond.for.cond45.preheader_crit_edge.loopexit.unr-lcssa:
successors: %bb.48(0x30000000), %bb.49(0x50000000)
liveins: $r0, $r1, $r3, $r9, $r10, $r11, $r12
t2CMPri renamable $r9, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2Bcc %bb.48, 0 /* CC::eq */, killed $cpsr
bb.49.for.body.us.us115.epil:
successors: %bb.51(0x40000000), %bb.50(0x40000000)
liveins: $r0, $r1, $r3, $r9, $r10, $r11, $r12
$r5 = t2MOVi16 target-flags(arm-lo16) @arr_163, 14 /* CC::al */, $noreg
renamable $r4 = t2ADDrs killed renamable $r0, renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
$r5 = t2MOVTi16 killed $r5, target-flags(arm-hi16) @arr_163, 14 /* CC::al */, $noreg
renamable $r0 = t2ADDri renamable $r11, 15, 14 /* CC::al */, $noreg, $noreg
renamable $r6 = t2ADDrs renamable $r5, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
renamable $q0 = MVE_VDUP8 renamable $r3, 0, $noreg, $noreg, undef renamable $q0
renamable $r0, dead $cpsr = tLSRri killed renamable $r0, 4, 14 /* CC::al */, $noreg
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r0, renamable $r11, %bb.51, implicit-def dead $cpsr
t2B %bb.50, 14 /* CC::al */, $noreg
bb.50:
successors: %bb.50(0x40000000), %bb.51(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r6 = MVE_VSTRBU8_post renamable $q0, killed renamable $r6, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.50, implicit-def dead $cpsr
t2B %bb.51, 14 /* CC::al */, $noreg
bb.51.for.body.us.us115.epil:
successors: %bb.48(0x40000000), %bb.52(0x40000000)
liveins: $r0, $r1, $r3, $r4, $r5, $r9, $r10, $r11, $r12
t2CMPri renamable $r9, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2Bcc %bb.52, 1 /* CC::ne */, killed $cpsr
bb.48:
successors: %bb.58(0x80000000)
liveins: $r10, $r1, $r12
renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1)
bb.58:
successors: %bb.59(0x80000000)
liveins: $r0, $r1, $r12, $r10
renamable $r3 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2)
bb.59.for.cond.for.cond45.preheader_crit_edge:
successors: %bb.60(0x80000000)
liveins: $r0, $r1, $r3, $r12, $r10
renamable $r5 = tLDRspi $sp, 18, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
bb.60.for.cond.for.cond45.preheader_crit_edge:
successors: %bb.61(0x80000000)
liveins: $r0, $r1, $r3, $r5, $r10, $r12
$r2 = t2MOVi16 target-flags(arm-lo16) @var_81, 14 /* CC::al */, $noreg
$r2 = t2MOVTi16 killed $r2, target-flags(arm-hi16) @var_81, 14 /* CC::al */, $noreg
tSTRi killed renamable $r0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into @var_81)
bb.61.for.cond45.preheader:
successors: %bb.79(0x30000000), %bb.62(0x50000000)
liveins: $r1, $r3, $r5, $r10, $r12
tCMPi8 killed renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 0, 8, implicit-def $itstate
$r10 = t2MOVi 22, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed renamable $r10, implicit killed $itstate
tCMPi8 killed renamable $r5, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2Bcc %bb.79, 0 /* CC::eq */, killed $cpsr
bb.62.for.cond45.preheader1:
successors: %bb.63(0x80000000)
liveins: $r1, $r10, $r12
$r0 = t2MOVi16 target-flags(arm-lo16) @arr_239, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
$r0 = t2MOVTi16 killed $r0, target-flags(arm-hi16) @arr_239, 14 /* CC::al */, $noreg
bb.63.for.cond45 (align 4):
successors: %bb.63(0x80000000)
liveins: $r0, $r1, $r2, $r10, $r12
dead renamable $r2, $cpsr = tLSLri killed renamable $r2, 24, 14 /* CC::al */, $noreg
renamable $r2 = t2CSEL renamable $r12, renamable $r1, 0, implicit killed $cpsr
renamable $r2 = tUXTB killed renamable $r2, 14 /* CC::al */, $noreg
tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2STRBs renamable $r10, renamable $r0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx59)
renamable $r2 = t2CSEL renamable $r12, renamable $r1, 0, implicit killed $cpsr
renamable $r2 = tUXTB killed renamable $r2, 14 /* CC::al */, $noreg
tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2STRBs renamable $r10, renamable $r0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx59.1)
renamable $r2 = t2CSEL renamable $r12, renamable $r1, 0, implicit killed $cpsr
renamable $r2 = tUXTB killed renamable $r2, 14 /* CC::al */, $noreg
tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2STRBs renamable $r10, renamable $r0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx59.2)
renamable $r2 = t2CSEL renamable $r12, renamable $r1, 0, implicit killed $cpsr
renamable $r3 = tUXTB renamable $r2, 14 /* CC::al */, $noreg
t2STRBs renamable $r10, renamable $r0, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx59.3)
t2B %bb.63, 14 /* CC::al */, $noreg
bb.79.for.cond45.us (align 4):
successors: %bb.79(0x80000000)
t2B %bb.79, 14 /* CC::al */, $noreg
bb.28.for.body.us.preheader.new:
successors: %bb.29(0x80000000)
liveins: $r0, $r1, $r3, $r8, $r9, $r10, $r11, $r12
renamable $r2 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
renamable $r4 = nuw t2ADDri renamable $r3, 24, 14 /* CC::al */, $noreg, $noreg
renamable $q0 = MVE_VDUP8 killed renamable $r2, 0, $noreg, $noreg, undef renamable $q0
renamable $r2 = t2ADDri renamable $r11, 15, 14 /* CC::al */, $noreg, $noreg
renamable $r8 = t2BICri killed renamable $r8, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
renamable $r5, dead $cpsr = tLSRri killed renamable $r2, 4, 14 /* CC::al */, $noreg
t2B %bb.29, 14 /* CC::al */, $noreg
bb.53.for.body.us (align 4):
successors: %bb.54(0x04000000), %bb.29(0x7c000000)
liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12
renamable $r6, dead $cpsr = nuw tADDi8 killed renamable $r6, 4, 14 /* CC::al */, $noreg
tCMPhir renamable $r8, renamable $r6, 14 /* CC::al */, $noreg, implicit-def $cpsr
renamable $r4 = t2ADDri killed renamable $r4, 48, 14 /* CC::al */, $noreg, $noreg
t2Bcc %bb.54, 0 /* CC::eq */, killed $cpsr
bb.29.for.body.us:
successors: %bb.31(0x40000000), %bb.30(0x40000000)
liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12
renamable $r7 = t2SUBri renamable $r4, 24, 14 /* CC::al */, $noreg, $noreg
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r5, renamable $r11, %bb.31, implicit-def dead $cpsr
t2B %bb.30, 14 /* CC::al */, $noreg
bb.30:
successors: %bb.30(0x40000000), %bb.31(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.30, implicit-def dead $cpsr
t2B %bb.31, 14 /* CC::al */, $noreg
bb.31.for.body.us:
successors: %bb.33(0x40000000), %bb.32(0x40000000)
liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12
renamable $r7 = t2SUBri renamable $r4, 12, 14 /* CC::al */, $noreg, $noreg
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r5, renamable $r11, %bb.33, implicit-def dead $cpsr
t2B %bb.32, 14 /* CC::al */, $noreg
bb.32:
successors: %bb.32(0x40000000), %bb.33(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.32, implicit-def dead $cpsr
t2B %bb.33, 14 /* CC::al */, $noreg
bb.33.for.body.us:
successors: %bb.35(0x40000000), %bb.34(0x40000000)
liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12
$r7 = tMOVr $r4, 14 /* CC::al */, $noreg
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r5, renamable $r11, %bb.35, implicit-def dead $cpsr
t2B %bb.34, 14 /* CC::al */, $noreg
bb.34:
successors: %bb.34(0x40000000), %bb.35(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.34, implicit-def dead $cpsr
t2B %bb.35, 14 /* CC::al */, $noreg
bb.35.for.body.us:
successors: %bb.53(0x40000000), %bb.36(0x40000000)
liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12
renamable $r7 = t2ADDri renamable $r4, 12, 14 /* CC::al */, $noreg, $noreg
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r5, renamable $r11, %bb.53, implicit-def dead $cpsr
t2B %bb.36, 14 /* CC::al */, $noreg
bb.36:
successors: %bb.36(0x40000000), %bb.53(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.36, implicit-def dead $cpsr
t2B %bb.53, 14 /* CC::al */, $noreg
bb.19.for.body.us.us115.preheader.new:
successors: %bb.20(0x80000000)
liveins: $r1, $r8, $r9, $r10, $r11, $r12
$r0 = t2MOVi16 target-flags(arm-lo16) @arr_163, 14 /* CC::al */, $noreg
renamable $r3 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
$r0 = t2MOVTi16 killed $r0, target-flags(arm-hi16) @arr_163, 14 /* CC::al */, $noreg
renamable $r2 = t2ADDri renamable $r11, 15, 14 /* CC::al */, $noreg, $noreg
renamable $r4 = nuw t2ADDri killed renamable $r0, 24, 14 /* CC::al */, $noreg, $noreg
renamable $r5 = t2BICri killed renamable $r8, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VDUP8 renamable $r3, 0, $noreg, $noreg, undef renamable $q0
renamable $r6, dead $cpsr = tLSRri killed renamable $r2, 4, 14 /* CC::al */, $noreg
t2B %bb.20, 14 /* CC::al */, $noreg
bb.46.for.body.us.us115 (align 4):
successors: %bb.47(0x04000000), %bb.20(0x7c000000)
liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r9, $r10, $r11, $r12
renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
tCMPr renamable $r5, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
renamable $r4 = t2ADDri killed renamable $r4, 48, 14 /* CC::al */, $noreg, $noreg
t2Bcc %bb.47, 0 /* CC::eq */, killed $cpsr
bb.20.for.body.us.us115:
successors: %bb.22(0x40000000), %bb.21(0x40000000)
liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r9, $r10, $r11, $r12
renamable $r7 = t2SUBri renamable $r4, 24, 14 /* CC::al */, $noreg, $noreg
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r6, renamable $r11, %bb.22, implicit-def dead $cpsr
t2B %bb.21, 14 /* CC::al */, $noreg
bb.21:
successors: %bb.21(0x40000000), %bb.22(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.21, implicit-def dead $cpsr
t2B %bb.22, 14 /* CC::al */, $noreg
bb.22.for.body.us.us115:
successors: %bb.24(0x40000000), %bb.23(0x40000000)
liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r9, $r10, $r11, $r12
renamable $r7 = t2SUBri renamable $r4, 12, 14 /* CC::al */, $noreg, $noreg
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r6, renamable $r11, %bb.24, implicit-def dead $cpsr
t2B %bb.23, 14 /* CC::al */, $noreg
bb.23:
successors: %bb.23(0x40000000), %bb.24(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.23, implicit-def dead $cpsr
t2B %bb.24, 14 /* CC::al */, $noreg
bb.24.for.body.us.us115:
successors: %bb.26(0x40000000), %bb.25(0x40000000)
liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r9, $r10, $r11, $r12
$r7 = tMOVr $r4, 14 /* CC::al */, $noreg
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r6, renamable $r11, %bb.26, implicit-def dead $cpsr
t2B %bb.25, 14 /* CC::al */, $noreg
bb.25:
successors: %bb.25(0x40000000), %bb.26(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.25, implicit-def dead $cpsr
t2B %bb.26, 14 /* CC::al */, $noreg
bb.26.for.body.us.us115:
successors: %bb.46(0x40000000), %bb.27(0x40000000)
liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r9, $r10, $r11, $r12
renamable $r7 = t2ADDri renamable $r4, 12, 14 /* CC::al */, $noreg, $noreg
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r6, renamable $r11, %bb.46, implicit-def dead $cpsr
t2B %bb.27, 14 /* CC::al */, $noreg
bb.27:
successors: %bb.27(0x40000000), %bb.46(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.27, implicit-def dead $cpsr
t2B %bb.46, 14 /* CC::al */, $noreg
bb.52.for.body.us.us115.epil.1:
successors: %bb.70(0x40000000), %bb.69(0x40000000)
liveins: $r0, $r1, $r3, $r4, $r5, $r9, $r10, $r11, $r12
renamable $r4 = t2ADDrs killed renamable $r5, killed renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
renamable $r5 = t2ADDri renamable $r4, 12, 14 /* CC::al */, $noreg, $noreg
renamable $q0 = MVE_VDUP8 renamable $r3, 0, $noreg, $noreg, undef renamable $q0
$r2 = tMOVr $r11, 14 /* CC::al */, $noreg
renamable $lr = t2WhileLoopStartTP renamable $r0, renamable $r11, %bb.70, implicit-def dead $cpsr
t2B %bb.69, 14 /* CC::al */, $noreg
bb.69:
successors: %bb.69(0x40000000), %bb.70(0x40000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr
renamable $r5 = MVE_VSTRBU8_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.69, implicit-def dead $cpsr
t2B %bb.70, 14 /* CC::al */, $noreg
bb.70.for.body.us.us115.epil.1:
successors: %bb.73(0x40000000), %bb.71(0x40000000)
liveins: $r0, $r1, $r3, $r4, $r9, $r10, $r11, $r12
renamable $r5 = tLDRspi $sp, 18, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
t2CMPri killed renamable $r9, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2Bcc %bb.73, 0 /* CC::eq */, killed $cpsr
bb.71.for.body.us.us115.epil.2:
successors: %bb.73(0x40000000), %bb.72(0x40000000)
liveins: $r0, $r1, $r3, $r4, $r5, $r10, $r11, $r12
renamable $r4, dead $cpsr = tADDi8 killed renamable $r4, 24, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VDUP8 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2WhileLoopStartTP killed renamable $r0, renamable $r11, %bb.73, implicit-def dead $cpsr
t2B %bb.72, 14 /* CC::al */, $noreg
bb.72:
successors: %bb.72(0x40000000), %bb.73(0x40000000)
liveins: $lr, $q0, $r1, $r4, $r5, $r10, $r11, $r12
renamable $vpr = MVE_VCTP8 renamable $r11, 0, $noreg, $noreg
renamable $r11 = t2SUBri killed renamable $r11, 16, 14 /* CC::al */, $noreg, $noreg
MVE_VPST 8, implicit $vpr
renamable $r4 = MVE_VSTRBU8_post renamable $q0, killed renamable $r4, 16, 1, killed renamable $vpr, renamable $lr
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.72, implicit-def dead $cpsr
t2B %bb.73, 14 /* CC::al */, $noreg
bb.73.for.body.us.us115.epil.2:
successors: %bb.60(0x80000000)
liveins: $r1, $r12, $r5, $r10
$r3, $r0 = t2LDRDi8 $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2), (load (s32) from %stack.1)
t2B %bb.60, 14 /* CC::al */, $noreg
...