[AArch64] Improve adrp schedule modelling on the Cortex-A55

[NickGuy]

Summary

Enables the FuseAddress feature in the Cortex-A55 scheduling model

[dmgreen]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

3215 ↗

(On Diff #370910)

This seems like a separate feature from adding FeatureFuseAddress for A55.

ReadAdrBase seems to be for the "base resister of a reg-offset LD/ST", where as this is the base register of a imm-offset LD/ST.
Having a Read for this would sound useful, but it would probably be best for it to be on all Imm offset base registers, not just this one, and sounds like a separate change.

[NickGuy]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

3215 ↗

(On Diff #370910)

I've pulled it out of this change, and I'll push it up for review separately.

[dmgreen]

OK. Can you add a test? Something that would schedule instructions apart before and keep them together now.

[NickGuy]

In D109323#2985421, @dmgreen wrote:

OK. Can you add a test? Something that would schedule instructions apart before and keep them together now.

Done, I've pre-committed the test locally so the actual change is easier to see.

[dmgreen]

llvm/test/CodeGen/AArch64/a55-fuse-address.mir

2

Should this be running a pass? -run-pass=machine-scheduler? And be updated using update_mir_test_checks?

[NickGuy]

Updated test

llvm/test/CodeGen/AArch64/a55-fuse-address.mir

2

Done. I feel like there was a reason why I didn't in the first place (i.e. it wasn't working for whatever reason), but it works now so ¯\_(ツ)_/¯

[dmgreen]

Thanks. The Cortex-A55 software optimization guide does mention "dedicated forwarding paths" for this case. LGTM

llvm/lib/Target/AArch64/AArch64.td

def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
                                    FeatureFPARMv8,
                                    FeatureFuseAES,
                                    FeatureNEON,
                                    FeatureFullFP16,
                                    FeatureDotProd,
                                    FeatureRCPC,
                                    FeaturePerfMon,
                                    FeaturePostRAScheduler,
+                                   FeatureFuseAddress,
                                    ]>;
 
 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
                                    "Cortex-A57 ARM processors", [
                                    FeatureBalanceFPOps,
                                    FeatureCRC,
                                    FeatureCrypto,
                                    FeatureCustomCheapAsMoveHandling,

llvm/test/CodeGen/AArch64/a55-fuse-address.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -o - %s -mtriple=aarch64 -run-pass=machine-scheduler -verify-machineinstrs | FileCheck %s
+--- |
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64-arm-none-eabi"
+
+  @a = dso_local global i32 2, align 4
+  @b = dso_local global i32 4, align 4
+
+  define i32 @fuseaddress(i32 %num) #0 {
+  entry:
+    %0 = load i32, i32* @a, align 4
+    %1 = load i32, i32* @b, align 4
+    %mul = mul nsw i32 %0, %1
+    ret i32 %mul
+  }
+
+  attributes #0 = { "target-cpu"="cortex-a55" }
+
+---
+name: fuseaddress
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+liveins:
+  - { reg: '$w0' }
+body: |
+  bb.0.entry:
+    liveins: $w0
+    ; CHECK-LABEL: name: fuseaddress
+    ; CHECK: liveins: $w0
+    ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @a
+    ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @a :: (dereferenceable load (s32) from @a)
+    ; CHECK: [[ADRP1:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @b
+    ; CHECK: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[ADRP1]], target-flags(aarch64-pageoff, aarch64-nc) @b :: (dereferenceable load (s32) from @b)
+    ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = nsw MADDWrrr [[LDRWui]], [[LDRWui1]], $wzr
+    ; CHECK: $w0 = COPY [[MADDWrrr]]
+    ; CHECK: RET_ReallyLR implicit $w0
+    %1:gpr64common = ADRP target-flags(aarch64-page) @a
+    %4:gpr64common = ADRP target-flags(aarch64-page) @b
+    %2:gpr32 = LDRWui killed %1:gpr64common, target-flags(aarch64-pageoff, aarch64-nc) @a :: (dereferenceable load (s32) from @a)
+    %5:gpr32 = LDRWui killed %4:gpr64common, target-flags(aarch64-pageoff, aarch64-nc) @b :: (dereferenceable load (s32) from @b)
+    %6:gpr32 = nsw MADDWrrr killed %2:gpr32, killed %5:gpr32, $wzr
+    $w0 = COPY %6:gpr32
+    RET_ReallyLR implicit $w0